gpuwm-hex 0.2.0__tar.gz → 0.2.2__tar.gz

This diff represents the content of publicly available package versions that have been released to one of the supported registries. The information contained in this diff is provided for informational purposes only and reflects changes between package versions as they appear in their respective public registries.
Files changed (375) hide show
  1. {gpuwm_hex-0.2.0/src/gpuwm_hex.egg-info → gpuwm_hex-0.2.2}/PKG-INFO +54 -40
  2. {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/README.md +52 -38
  3. {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/docs/declared-divergences.md +26 -8
  4. {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/docs/manual/02-quickstart.md +12 -11
  5. {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/docs/manual/04-meshes-and-static.md +36 -1
  6. {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/docs/manual/08-troubleshooting.md +2 -2
  7. {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/docs/manual/09-reference.md +5 -5
  8. {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/docs/manual/index.md +4 -4
  9. {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/pyproject.toml +11 -9
  10. {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2/src/gpuwm_hex.egg-info}/PKG-INFO +54 -40
  11. {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/src/gpuwm_hex.egg-info/SOURCES.txt +3 -0
  12. {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/src/gpuwm_hex.egg-info/requires.txt +1 -1
  13. {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/src/hexcore/cuda_arwen_physics_v841.py +12 -12
  14. {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/src/hexcore/engine_pin.py +55 -18
  15. {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/src/hexcore/libm_identity.py +59 -0
  16. {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/src/hexcore/mesh.py +151 -0
  17. {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/src/hexcore/mesh_spec_gates.py +149 -16
  18. {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/src/hexcore/physics_seam.py +135 -11
  19. {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/src/hexcore/rkind_libm.py +1 -1
  20. {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/src/hexcore/swath/sizing.py +35 -1
  21. {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/src/hexcore/vertical.py +1 -1
  22. {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/tests/test_convection_admission.py +42 -18
  23. {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/tests/test_cuda_v841_full_physics_x4.py +2 -2
  24. {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/tests/test_engine_pin.py +35 -15
  25. {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/tests/test_libm_identity.py +2 -2
  26. {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/tests/test_mesh_spec_gates.py +180 -20
  27. {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/tests/test_mesh_validation.py +137 -0
  28. gpuwm_hex-0.2.2/tests/test_p3_seam_ab.py +309 -0
  29. {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/tests/test_packaging_declaration.py +6 -5
  30. {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/tests/test_proof_guard_pins.py +2 -2
  31. {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/tests/test_regional_physics_seam.py +113 -0
  32. {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/tests/test_swath_door.py +101 -5
  33. gpuwm_hex-0.2.2/tests/test_tier_membership.py +201 -0
  34. gpuwm_hex-0.2.2/tests/test_tracked_file_writers_keep_lf.py +185 -0
  35. {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/tests/test_vertical_vectorized_equivalence.py +42 -0
  36. gpuwm_hex-0.2.2/tools/battery/cpu_files.txt +213 -0
  37. {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/tools/battery/gpu_gates.txt +8 -0
  38. {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/tools/mpas_mesh_binding.py +96 -0
  39. {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/tools/probe_swath_spec_generable.py +35 -6
  40. {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/tools/run_cuda_v841_full_physics_x4.py +3 -3
  41. gpuwm_hex-0.2.0/tools/battery/cpu_files.txt +0 -92
  42. {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/LICENSE +0 -0
  43. {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/MANIFEST.in +0 -0
  44. {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/NOTICE +0 -0
  45. {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/docs/cycle-door.md +0 -0
  46. {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/docs/device-memory-ledger.md +0 -0
  47. {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/docs/init-door.md +0 -0
  48. {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/docs/manual/01-what-this-is.md +0 -0
  49. {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/docs/manual/03-concepts.md +0 -0
  50. {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/docs/manual/05-initial-conditions.md +0 -0
  51. {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/docs/manual/06-forecast.md +0 -0
  52. {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/docs/manual/07-render.md +0 -0
  53. {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/docs/native-free-init-admission.md +0 -0
  54. {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/docs/obs-referee.md +0 -0
  55. {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/docs/render-door.md +0 -0
  56. {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/docs/source-matrix.md +0 -0
  57. {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/evidence/EVIDENCE.md +0 -0
  58. {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/setup.cfg +0 -0
  59. {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/src/gpuwm_hex.egg-info/dependency_links.txt +0 -0
  60. {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/src/gpuwm_hex.egg-info/entry_points.txt +0 -0
  61. {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/src/gpuwm_hex.egg-info/top_level.txt +0 -0
  62. {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/src/hexcore/__init__.py +0 -0
  63. {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/src/hexcore/__main__.py +0 -0
  64. {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/src/hexcore/acoustic.py +0 -0
  65. {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/src/hexcore/acoustic_v841.py +0 -0
  66. {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/src/hexcore/cascade_row.py +0 -0
  67. {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/src/hexcore/cell_coordination_admission.py +0 -0
  68. {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/src/hexcore/cli.py +0 -0
  69. {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/src/hexcore/config.py +0 -0
  70. {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/src/hexcore/config_lts.py +0 -0
  71. {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/src/hexcore/config_v841.py +0 -0
  72. {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/src/hexcore/convection_admission.py +0 -0
  73. {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/src/hexcore/cuda_acoustic.py +0 -0
  74. {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/src/hexcore/cuda_acoustic_lts.py +0 -0
  75. {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/src/hexcore/cuda_acoustic_v841.py +0 -0
  76. {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/src/hexcore/cuda_backend/__init__.py +0 -0
  77. {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/src/hexcore/cuda_backend/arch_admission.py +0 -0
  78. {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/src/hexcore/cuda_backend/compile_contract.py +0 -0
  79. {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/src/hexcore/cuda_backend/containers.py +0 -0
  80. {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/src/hexcore/cuda_backend/recovery.py +0 -0
  81. {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/src/hexcore/cuda_backend/regional_admission.py +0 -0
  82. {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/src/hexcore/cuda_backend/runtime.py +0 -0
  83. {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/src/hexcore/cuda_driver.py +0 -0
  84. {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/src/hexcore/cuda_driver_lts.py +0 -0
  85. {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/src/hexcore/cuda_dualrun.py +0 -0
  86. {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/src/hexcore/cuda_dynamics_v841.py +0 -0
  87. {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/src/hexcore/cuda_fp32.py +0 -0
  88. {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/src/hexcore/cuda_ftz.py +0 -0
  89. {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/src/hexcore/cuda_ftz_v841.py +0 -0
  90. {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/src/hexcore/cuda_gwdo_v841.py +0 -0
  91. {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/src/hexcore/cuda_horizontal.py +0 -0
  92. {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/src/hexcore/cuda_horizontal_v841.py +0 -0
  93. {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/src/hexcore/cuda_physics_prep_v841.py +0 -0
  94. {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/src/hexcore/cuda_physics_tier_park_v841.py +0 -0
  95. {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/src/hexcore/cuda_physics_v841.py +0 -0
  96. {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/src/hexcore/cuda_regional_forecast_v841.py +0 -0
  97. {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/src/hexcore/cuda_regional_v841.py +0 -0
  98. {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/src/hexcore/cuda_transport.py +0 -0
  99. {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/src/hexcore/cuda_transport_v841.py +0 -0
  100. {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/src/hexcore/cuda_v841.py +0 -0
  101. {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/src/hexcore/cull_door.py +0 -0
  102. {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/src/hexcore/cycle/__init__.py +0 -0
  103. {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/src/hexcore/cycle/chain.py +0 -0
  104. {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/src/hexcore/cycle/delayed_start.py +0 -0
  105. {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/src/hexcore/cycle/door.py +0 -0
  106. {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/src/hexcore/cycle/errors.py +0 -0
  107. {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/src/hexcore/damping_v841.py +0 -0
  108. {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/src/hexcore/data/swath/placement-policy.v2.json +0 -0
  109. {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/src/hexcore/data/swath/threat-metrics.v3.json +0 -0
  110. {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/src/hexcore/device_admission.py +0 -0
  111. {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/src/hexcore/diagnostics.py +0 -0
  112. {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/src/hexcore/doctor.py +0 -0
  113. {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/src/hexcore/driver.py +0 -0
  114. {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/src/hexcore/dt_admission.py +0 -0
  115. {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/src/hexcore/dual_edge_admission.py +0 -0
  116. {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/src/hexcore/dynamics.py +0 -0
  117. {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/src/hexcore/dynamics_v841.py +0 -0
  118. {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/src/hexcore/engines.py +0 -0
  119. {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/src/hexcore/errors.py +0 -0
  120. {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/src/hexcore/forecast_door.py +0 -0
  121. {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/src/hexcore/horizontal.py +0 -0
  122. {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/src/hexcore/init_door.py +0 -0
  123. {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/src/hexcore/initialization.py +0 -0
  124. {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/src/hexcore/integration.py +0 -0
  125. {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/src/hexcore/integration_v841.py +0 -0
  126. {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/src/hexcore/lbc.py +0 -0
  127. {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/src/hexcore/lts_v841.py +0 -0
  128. {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/src/hexcore/mesh_plan_door.py +0 -0
  129. {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/src/hexcore/mesh_row_candidate.py +0 -0
  130. {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/src/hexcore/mixing.py +0 -0
  131. {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/src/hexcore/mixing_v841.py +0 -0
  132. {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/src/hexcore/nomix_oracle.py +0 -0
  133. {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/src/hexcore/obs_referee/__init__.py +0 -0
  134. {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/src/hexcore/obs_referee/__main__.py +0 -0
  135. {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/src/hexcore/obs_referee/acquire.py +0 -0
  136. {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/src/hexcore/obs_referee/align.py +0 -0
  137. {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/src/hexcore/obs_referee/bootstrap.py +0 -0
  138. {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/src/hexcore/obs_referee/bundle.py +0 -0
  139. {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/src/hexcore/obs_referee/canonical.py +0 -0
  140. {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/src/hexcore/obs_referee/cli.py +0 -0
  141. {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/src/hexcore/obs_referee/errors.py +0 -0
  142. {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/src/hexcore/obs_referee/manifest.py +0 -0
  143. {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/src/hexcore/obs_referee/metrics.py +0 -0
  144. {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/src/hexcore/obs_referee/report.py +0 -0
  145. {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/src/hexcore/obs_referee/runner.py +0 -0
  146. {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/src/hexcore/obs_referee/scorecard.py +0 -0
  147. {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/src/hexcore/obs_referee/treatment.py +0 -0
  148. {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/src/hexcore/offcentering_v841.py +0 -0
  149. {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/src/hexcore/oracle.py +0 -0
  150. {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/src/hexcore/output.py +0 -0
  151. {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/src/hexcore/partition_assets_v841.py +0 -0
  152. {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/src/hexcore/partition_device_scheduler_v841.py +0 -0
  153. {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/src/hexcore/partition_executor_v841.py +0 -0
  154. {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/src/hexcore/partition_local_mesh_v841.py +0 -0
  155. {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/src/hexcore/partition_net_v841.py +0 -0
  156. {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/src/hexcore/partition_state_v841.py +0 -0
  157. {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/src/hexcore/pbl_cadence.py +0 -0
  158. {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/src/hexcore/physics_backend_admission.py +0 -0
  159. {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/src/hexcore/physics_seam_v841.py +0 -0
  160. {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/src/hexcore/regional_v841.py +0 -0
  161. {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/src/hexcore/regrid.py +0 -0
  162. {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/src/hexcore/render_door.py +0 -0
  163. {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/src/hexcore/rust_renderer.py +0 -0
  164. {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/src/hexcore/shipped_sources.py +0 -0
  165. {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/src/hexcore/state.py +0 -0
  166. {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/src/hexcore/step_oracle.py +0 -0
  167. {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/src/hexcore/swath/__init__.py +0 -0
  168. {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/src/hexcore/swath/detect.py +0 -0
  169. {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/src/hexcore/swath/door.py +0 -0
  170. {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/src/hexcore/swath/errors.py +0 -0
  171. {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/src/hexcore/swath/geometry.py +0 -0
  172. {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/src/hexcore/swath/history.py +0 -0
  173. {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/src/hexcore/swath/hysteresis.py +0 -0
  174. {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/src/hexcore/swath/plan.py +0 -0
  175. {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/src/hexcore/swath/rank.py +0 -0
  176. {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/src/hexcore/swath/registry.py +0 -0
  177. {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/src/hexcore/swath/track.py +0 -0
  178. {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/src/hexcore/terrain.py +0 -0
  179. {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/src/hexcore/timestep_admission.py +0 -0
  180. {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/src/hexcore/tracer_oracle.py +0 -0
  181. {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/src/hexcore/transport.py +0 -0
  182. {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/src/hexcore/vector.py +0 -0
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  356. {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/tools/run_v841_compiled_endpoint_gate.py +0 -0
  357. {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/tools/run_v841_smagorinsky_authority_pin.py +0 -0
  358. {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/tools/scale_region_about_centroid.py +0 -0
  359. {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/tools/step_match_pbl_cadence_dt5.py +0 -0
  360. {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/tools/v841_partstream_common.py +0 -0
  361. {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/tools/validate_cuda_x1_163842_remote_evidence.py +0 -0
  362. {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/verification/CANONICAL-BUNDLE-CONTRACT.md +0 -0
  363. {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/verification/GF-HOOK-CONTRACT.md +0 -0
  364. {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/verification/README.md +0 -0
  365. {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/verification/fixtures/build_synthetic_suite.py +0 -0
  366. {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/verification/manifests/obs-referee-283.production.json +0 -0
  367. {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/verification/producers/README.md +0 -0
  368. {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/verification/producers/model_bundle.py +0 -0
  369. {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/verification/producers/observation_bundles.py +0 -0
  370. {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/verification/producers/select_control_cases.py +0 -0
  371. {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/verification/schemas/gf-subsidence-treatment-v1.schema.json +0 -0
  372. {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/verification/schemas/normalized-artifact-receipt-v1.schema.json +0 -0
  373. {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/verification/vertical-specs/legacy41-v1.json +0 -0
  374. {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/verification/vertical-specs/native-comparison-policy.NOT-MEASURED.json +0 -0
  375. {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/verification/vertical-specs/tc55-v1.json +0 -0
@@ -1,6 +1,6 @@
1
1
  Metadata-Version: 2.4
2
2
  Name: gpuwm-hex
3
- Version: 0.2.0
3
+ Version: 0.2.2
4
4
  Summary: GPU global atmospheric model on unstructured Voronoi meshes: a CUDA port of the MPAS-A v8.4.1 dycore with ArWen physics, arbitrary mesh generation, and single-card mesh streaming for 12-16 GB GPUs.
5
5
  License-Expression: Apache-2.0
6
6
  Project-URL: Homepage, https://github.com/FahrenheitResearch/gpuwm-hex
@@ -24,7 +24,7 @@ License-File: NOTICE
24
24
  Requires-Dist: numpy>=2.0
25
25
  Requires-Dist: netCDF4>=1.6
26
26
  Requires-Dist: scipy>=1.11
27
- Requires-Dist: gpuwm<2.5.9,>=2.5.8
27
+ Requires-Dist: gpuwm<2.6.2,>=2.6.1
28
28
  Provides-Extra: gpu-cu12
29
29
  Requires-Dist: cupy-cuda12x[ctk]>=14.0; extra == "gpu-cu12"
30
30
  Provides-Extra: gpu-cu13
@@ -182,7 +182,7 @@ verdict for each divergence is in
182
182
  | Python | 3.11 or newer |
183
183
  | GPU | A CUDA device. Memory is set by mesh size *and* by the card, and not by a line through the two: the footprint is a per-card core, plus the Grell-Freitas and YSU column workspaces charged at `min(cells, tile)`, plus a per-cell term, all in `hexcore.device_admission`. Measured 2026-08-26 on an RTX 5090 at the merged tip: the published 40,962-cell global mesh (x1.40962, about 120 km) peaked at **8,874 MiB — inside a 12 GiB card's budget**; the 163,842-cell mesh (x4.163842, about 24 km) peaked at **20,446 MiB**, and every free-memory gate admits at the measured floor — the prediction plus that card's own margin, **about 21.7 GiB free at x4** — so x4 remains in practice a 32 GiB-card configuration. The core is a property of the card, not the mesh, and the door reads the card's multiprocessor count at the decision rather than assuming a 5090: the 16 GiB and 10 GiB parts each carry their own measured row, and a card nobody has measured gets a derived row that is labelled derived. A card with its own #264 ledger can still supply it with `--device-fixed-mib` / `--device-bytes-per-cell`. Receipts: `evidence/memory-row-refit-20260826/node2/`, `evidence/l6-capacity-20260825/` and `evidence/memory-shape-20260827/`. |
184
184
  | CUDA | CuPy matching your driver's CUDA major — there is no way for pip to detect it, so you choose (below). |
185
- | Engine | The `gpuwm` distribution, `>=2.5.8,<2.5.9` — a bounded range, and pip resolves it for you: the physics seam, and the bundle that carries the MPAS bridge binaries the doors drive. **Plus a `gpuwm` source checkout at `v2.5.8` for the forecast lane** — see *The engine pin*. |
185
+ | Engine | The `gpuwm` distribution, `>=2.6.1,<2.6.2` — a bounded range, and pip resolves it for you: the physics seam, and the bundle that carries the MPAS bridge binaries the doors drive. **Plus a `gpuwm` source checkout at `v2.6.1` for the forecast lane** — see *The engine pin*. |
186
186
  | Assets | A mesh grid file, a matching static file, and (for the init door) a vertical-grid declaration — normally a `--vertical-spec` JSON; a native-minted init file as a capsule is the compatibility mode. **gpuwm-hex ships none of these and has no fetch path for them.** See *Assets you must supply*. |
187
187
  | Rust binaries | `rw_mpas_init` for the init door; `rw_mpas_convert` and `rw_wrfbatch` for the render door. They are built from the `gpuwm` source tree — see *Building the Rust engines*. |
188
188
 
@@ -242,40 +242,43 @@ unchanged.
242
242
 
243
243
  ### The engine pin
244
244
 
245
- gpuwm-hex depends on `gpuwm>=2.5.8,<2.5.9` — a **bounded range**, and the
245
+ gpuwm-hex depends on `gpuwm>=2.6.1,<2.6.2` — a **bounded range**, and the
246
246
  bound is the point. The port pins the engine's physics seam by the SHA-256 of
247
247
  **sixteen individual gpuwm source files**, and the gap between a published
248
- stamp and the pinned bytes has recurred at every cut. Re-measured 2026-08-28
249
- against the real published bytes of every 2.5.x release, plus the `v2.5.5` tag
250
- that has no release at all — JSON at
251
- `evidence/repin-258-20260828/engine-verdicts.json`, instrument beside it:
248
+ stamp and the pinned bytes has recurred at every cut. Re-measured 2026-09-01
249
+ against the real published bytes of every 2.5.x and 2.6.x release, plus the
250
+ `v2.5.5` tag that has no release at all — JSON at
251
+ `evidence/repin-261-20260901/engine-verdicts.json`, instrument at
252
+ `evidence/standalone-20260827/measure_engine_verdicts.py`:
252
253
 
253
254
  | gpuwm | on PyPI | seam pin | `--offline` build road |
254
255
  | --- | --- | --- | --- |
255
- | 2.5.0 | yes | 10 of 16 moved | complete |
256
- | 2.5.1 | yes | 10 of 16 moved | complete |
257
- | 2.5.2 | yes | 9 of 16 moved | complete |
258
- | 2.5.3 | yes | 6 of 16 moved | complete |
259
- | 2.5.4 | yes | 6 of 16 moved | complete |
260
- | 2.5.5 | **no — a git tag with no release** | 4 of 16 moved | **broken** |
261
- | 2.5.6 | yes | 4 of 16 moved | complete |
262
- | 2.5.7 | yes | 3 of 16 moved | complete |
263
- | **2.5.8** | yes | **matches** | complete |
264
-
265
- **2.5.8 is the only published engine whose bytes match the pin**, so it is the
256
+ | 2.5.0 | yes | 11 of 16 moved | complete |
257
+ | 2.5.1 | yes | 11 of 16 moved | complete |
258
+ | 2.5.2 | yes | 10 of 16 moved | complete |
259
+ | 2.5.3 | yes | 7 of 16 moved | complete |
260
+ | 2.5.4 | yes | 7 of 16 moved | complete |
261
+ | 2.5.5 | **no — a git tag with no release** | 7 of 16 moved | **broken** |
262
+ | 2.5.6 | yes | 7 of 16 moved | complete |
263
+ | 2.5.7 | yes | 6 of 16 moved | complete |
264
+ | 2.5.8 | yes | 5 of 16 moved | complete |
265
+ | 2.6.0 | yes | 3 of 16 moved | complete |
266
+ | **2.6.1** | yes | **matches** | complete |
267
+
268
+ **2.6.1 is the only published engine whose bytes match the pin**, so it is the
266
269
  floor, and with the exclusive ceiling one patch above it, it is the whole
267
270
  range.
268
271
 
269
- That is a narrower claim than this page carried before 2026-08-28, and the
272
+ That is the same narrow claim this page has carried since 2026-08-28, and the
270
273
  reason is not that an engine regressed. The `moved` column is measured against
271
274
  **this port's** seam manifest, so re-pinning that manifest moves every row at
272
- once, including rows for engines cut long before it: 2.5.6 read `matches`
273
- under the previous manifest and reads `4 of 16 moved` under this one. A row
275
+ once, including rows for engines cut long before it: 2.6.0 read `matches`
276
+ under the previous manifest and reads `3 of 16 moved` under this one. A row
274
277
  from the old table is not comparable with a row from this one, and neither is
275
278
  a row anyone patches by hand.
276
279
 
277
280
  The consequence is worth stating rather than discovering: **this port has no
278
- fallback engine.** If 2.5.8 were withdrawn, the answer would be to publish a
281
+ fallback engine.** If 2.6.1 were withdrawn, the answer would be to publish a
279
282
  new engine and re-measure, not to widen the range.
280
283
 
281
284
  Two facts about 2.5.5 that this page used to give as floor reasons are still
@@ -296,7 +299,7 @@ stops there with `failed to open file .../cc/src/target/generated.rs`.
296
299
  > reported the estate healthy and exited 0. A green install and a dead run.
297
300
  >
298
301
  > The ceiling is exclusive and sits at the first engine that is not measured
299
- > usable, so a future 2.5.9 is excluded exactly as 2.5.7 is today. Admitting a
302
+ > usable, so a future 2.6.2 is excluded exactly as 2.6.0 is today. Admitting a
300
303
  > new engine is a deliberate act: re-run
301
304
  > `evidence/standalone-20260827/measure_engine_verdicts.py`, splice its JSON
302
305
  > into the table in `hexcore.engine_pin` with
@@ -316,22 +319,22 @@ rows landed the day after the 2.5.2 upload, so published 2.5.2 stages none of
316
319
  them through `gpuwm fetch-bridges`. Both front doors drive those binaries, so
317
320
  a user who resolved onto a 2.5.2 engine could open **neither door**. That is a
318
321
  stranded install rather than a degraded one, and a dependency floor is the
319
- only place pip can refuse it. Measured 2026-08-28 on the pinned engine:
322
+ only place pip can refuse it. Measured 2026-08-28 on the then-pinned engine:
320
323
  `gpuwm fetch-bridges` from a published 2.5.8 install downloads
321
324
  `gpuwm-bridges-v2.5.8-win-x86_64.zip` and stages **26 of 26 artifacts, each
322
325
  verified against the packaged pin** — the four above, plus `rw_wrfbatch` and
323
326
  the `rw_mpas_lbc` the limited-area lane needs.
324
327
 
325
328
  *(The gpuwm source tree publishes too: `github.com/FahrenheitResearch/arwen`
326
- carries tags `v2.5.0` through `v2.5.8` with the full tree, `docs/mpas-seam.md`
329
+ carries tags `v2.5.0` through `v2.6.1` with the full tree, `docs/mpas-seam.md`
327
330
  and `gpuwm/core/mpas_column_batch.py` included. The table above was taken by
328
- cloning all nine of those tags and hashing the pinned files, so the build road
329
- below is open to anyone, subject to the 2.5.5 vendor gap noted above.)*
331
+ hashing the pinned files at all eleven of those tags, so the build road below
332
+ is open to anyone, subject to the 2.5.5 vendor gap noted above.)*
330
333
 
331
334
  **Installing `gpuwm` is necessary but not sufficient for the forecast lane.**
332
335
  The `forecast` door refuses without `--gpuwm-checkout`: a gpuwm **git
333
336
  checkout** at the pinned commit (`--arwen-checkout` on the driver beneath it),
334
- in addition to the installed distribution. Clone `v2.5.8`. This is stated
337
+ in addition to the installed distribution. Clone `v2.6.1`. This is stated
335
338
  plainly because the alternative — discovering it as a `FileNotFoundError` deep
336
339
  in a launch — is the trap; the `forecast` door refuses by name instead, and so
337
340
  does `gpuwm-hex doctor`.
@@ -469,7 +472,7 @@ bundle carries `rw_wrfbatch` and **not** `rw_mpas_init` or `rw_mpas_convert`.
469
472
  On that engine `gpuwm fetch-bridges` gives you the renderer and nothing that
470
473
  opens either MPAS door. That measurement is why the dependency floor cleared
471
474
  2.5.3 and never fell back: 2.5.3 is where the four MPAS bridge binaries
472
- enter the bundle, and the current `gpuwm>=2.5.8,<2.5.9` range keeps that
475
+ enter the bundle, and the current `gpuwm>=2.6.1,<2.6.2` range keeps that
473
476
  guarantee, so pip cannot resolve you onto an engine that strands both doors. A
474
477
  conforming install therefore never sees the 2.5.2 shortfall; it is recorded
475
478
  here because it is the reason the floor first moved.
@@ -574,7 +577,7 @@ bytes can be named by commit, and an install has no commit — and a **gpuwm-hex
574
577
  source checkout** for the drivers under `tools/`, which verify their own
575
578
  executing modules by SHA-256 and therefore cannot live inside the wheel.
576
579
  `gpuwm-hex doctor` reports the same two gaps. The gpuwm one is no longer about
577
- a pinned file the wheel cannot reach: at 2.5.8 all sixteen resolve from an
580
+ a pinned file the wheel cannot reach: since 2.5.8 all sixteen resolve from an
578
581
  install (*The engine pin*).
579
582
 
580
583
  Its inputs are a mesh, a static file and an init. The registry makes the first
@@ -794,15 +797,25 @@ Measured over 24 h, two independent weather cases, two mixing regimes,
794
797
  They entered this repository already finished on 2026-08-20, and there is no
795
798
  receipt directory, no card and no run commit for them anywhere in the tree.
796
799
  What can be established is a ceiling: the commit that introduced them pinned
797
- engine `629ddb6f0`, so they were measured at or before that pin. Three engine
800
+ engine `629ddb6f0`, so they were measured at or before that pin. Five engine
798
801
  pin moves have landed since — `0d04db712` (2026-08-24), `26daaab7e`
799
- (2026-08-25) and `659962929` (2026-08-28). The **last** of the three is
800
- measured to change nothing: a four-arm byte A/B on one card found the old and
801
- new pins identical on the atmosphere half of the per-step fingerprint at all
802
- 31 steps and on 0 of 138 history variables
803
- (`evidence/seam-258-ab-20260828/`) — one mesh, one case, one hour. The two
804
- earlier moves have no such arm, and none of the three magnitudes has been
805
- re-measured over 24 h since. Whether any of them moved is **NOT MEASURED**.
802
+ (2026-08-25), `659962929` (2026-08-28), `7e34a48` (2026-08-31, gpuwm
803
+ 2.6.0) and `df5f34c5c` (2026-09-01, gpuwm 2.6.1). The **2.5.8** move is measured to change nothing: a four-arm byte A/B
804
+ on one card found the old and new pins identical on the atmosphere half of
805
+ the per-step fingerprint at all 31 steps and on 0 of 138 history variables
806
+ (`evidence/seam-258-ab-20260828/`) — one mesh, one case, one hour. The
807
+ **2.6.0** move also crosses the executed seam (`gpuwm/core/rrtmg_legacy.py`
808
+ among its three moved files) and is measured the same way at the same
809
+ scope: the x4 proof re-run at that pin wrote an F001 history byte-identical
810
+ to the 2.5.8 proof's (`evidence/repin-260-20260831/x4-proof/`). The
811
+ **2.6.1** move crosses it a third time, at its centre — the seam's own batch
812
+ driver `gpuwm/core/mpas_column_batch.py` gains restart schema v2 and the P3
813
+ eight-species transport — and is measured the same way at the same scope:
814
+ the x4 proof re-run at that pin wrote all four snapshots (F000, F030, F001
815
+ and the restarted F001) byte-identical to the 2.6.0 proof's, so one F001
816
+ SHA-256 now spans three engines (`evidence/repin-261-20260901/x4-proof/`).
817
+ The two earliest moves have no such arm, and none of the three magnitudes
818
+ has been re-measured over 24 h since. Whether any of them moved is **NOT MEASURED**.
806
819
  Read them as the numbers from the pre-2026-08-20 engine, not as today's.
807
820
 
808
821
  1. **Upper-level warm drift.** Above level 45 the port warms relative to native
@@ -859,7 +872,8 @@ case-independent, which chaos cannot be, and each names a lane to fix.
859
872
  > `--cull-parent`, and `rw_mpas_lbc` was in no bundle and no published source
860
873
  > (measured 2026-08-27, `evidence/userwalk-20260827/RECEIPT.md` — that receipt
861
874
  > is a record of 2.5.7 and is not restated here as current fact). The engine
862
- > then published 2.5.8, which this distribution requires.
875
+ > then published 2.5.8, which this distribution required until it re-pinned
876
+ > onto 2.6.0 and then 2.6.1.
863
877
  >
864
878
  > Measured 2026-08-28 against the real published artefacts: `gpuwm
865
879
  > fetch-bridges` on a 2.5.8 install downloads
@@ -144,7 +144,7 @@ verdict for each divergence is in
144
144
  | Python | 3.11 or newer |
145
145
  | GPU | A CUDA device. Memory is set by mesh size *and* by the card, and not by a line through the two: the footprint is a per-card core, plus the Grell-Freitas and YSU column workspaces charged at `min(cells, tile)`, plus a per-cell term, all in `hexcore.device_admission`. Measured 2026-08-26 on an RTX 5090 at the merged tip: the published 40,962-cell global mesh (x1.40962, about 120 km) peaked at **8,874 MiB — inside a 12 GiB card's budget**; the 163,842-cell mesh (x4.163842, about 24 km) peaked at **20,446 MiB**, and every free-memory gate admits at the measured floor — the prediction plus that card's own margin, **about 21.7 GiB free at x4** — so x4 remains in practice a 32 GiB-card configuration. The core is a property of the card, not the mesh, and the door reads the card's multiprocessor count at the decision rather than assuming a 5090: the 16 GiB and 10 GiB parts each carry their own measured row, and a card nobody has measured gets a derived row that is labelled derived. A card with its own #264 ledger can still supply it with `--device-fixed-mib` / `--device-bytes-per-cell`. Receipts: `evidence/memory-row-refit-20260826/node2/`, `evidence/l6-capacity-20260825/` and `evidence/memory-shape-20260827/`. |
146
146
  | CUDA | CuPy matching your driver's CUDA major — there is no way for pip to detect it, so you choose (below). |
147
- | Engine | The `gpuwm` distribution, `>=2.5.8,<2.5.9` — a bounded range, and pip resolves it for you: the physics seam, and the bundle that carries the MPAS bridge binaries the doors drive. **Plus a `gpuwm` source checkout at `v2.5.8` for the forecast lane** — see *The engine pin*. |
147
+ | Engine | The `gpuwm` distribution, `>=2.6.1,<2.6.2` — a bounded range, and pip resolves it for you: the physics seam, and the bundle that carries the MPAS bridge binaries the doors drive. **Plus a `gpuwm` source checkout at `v2.6.1` for the forecast lane** — see *The engine pin*. |
148
148
  | Assets | A mesh grid file, a matching static file, and (for the init door) a vertical-grid declaration — normally a `--vertical-spec` JSON; a native-minted init file as a capsule is the compatibility mode. **gpuwm-hex ships none of these and has no fetch path for them.** See *Assets you must supply*. |
149
149
  | Rust binaries | `rw_mpas_init` for the init door; `rw_mpas_convert` and `rw_wrfbatch` for the render door. They are built from the `gpuwm` source tree — see *Building the Rust engines*. |
150
150
 
@@ -204,40 +204,43 @@ unchanged.
204
204
 
205
205
  ### The engine pin
206
206
 
207
- gpuwm-hex depends on `gpuwm>=2.5.8,<2.5.9` — a **bounded range**, and the
207
+ gpuwm-hex depends on `gpuwm>=2.6.1,<2.6.2` — a **bounded range**, and the
208
208
  bound is the point. The port pins the engine's physics seam by the SHA-256 of
209
209
  **sixteen individual gpuwm source files**, and the gap between a published
210
- stamp and the pinned bytes has recurred at every cut. Re-measured 2026-08-28
211
- against the real published bytes of every 2.5.x release, plus the `v2.5.5` tag
212
- that has no release at all — JSON at
213
- `evidence/repin-258-20260828/engine-verdicts.json`, instrument beside it:
210
+ stamp and the pinned bytes has recurred at every cut. Re-measured 2026-09-01
211
+ against the real published bytes of every 2.5.x and 2.6.x release, plus the
212
+ `v2.5.5` tag that has no release at all — JSON at
213
+ `evidence/repin-261-20260901/engine-verdicts.json`, instrument at
214
+ `evidence/standalone-20260827/measure_engine_verdicts.py`:
214
215
 
215
216
  | gpuwm | on PyPI | seam pin | `--offline` build road |
216
217
  | --- | --- | --- | --- |
217
- | 2.5.0 | yes | 10 of 16 moved | complete |
218
- | 2.5.1 | yes | 10 of 16 moved | complete |
219
- | 2.5.2 | yes | 9 of 16 moved | complete |
220
- | 2.5.3 | yes | 6 of 16 moved | complete |
221
- | 2.5.4 | yes | 6 of 16 moved | complete |
222
- | 2.5.5 | **no — a git tag with no release** | 4 of 16 moved | **broken** |
223
- | 2.5.6 | yes | 4 of 16 moved | complete |
224
- | 2.5.7 | yes | 3 of 16 moved | complete |
225
- | **2.5.8** | yes | **matches** | complete |
226
-
227
- **2.5.8 is the only published engine whose bytes match the pin**, so it is the
218
+ | 2.5.0 | yes | 11 of 16 moved | complete |
219
+ | 2.5.1 | yes | 11 of 16 moved | complete |
220
+ | 2.5.2 | yes | 10 of 16 moved | complete |
221
+ | 2.5.3 | yes | 7 of 16 moved | complete |
222
+ | 2.5.4 | yes | 7 of 16 moved | complete |
223
+ | 2.5.5 | **no — a git tag with no release** | 7 of 16 moved | **broken** |
224
+ | 2.5.6 | yes | 7 of 16 moved | complete |
225
+ | 2.5.7 | yes | 6 of 16 moved | complete |
226
+ | 2.5.8 | yes | 5 of 16 moved | complete |
227
+ | 2.6.0 | yes | 3 of 16 moved | complete |
228
+ | **2.6.1** | yes | **matches** | complete |
229
+
230
+ **2.6.1 is the only published engine whose bytes match the pin**, so it is the
228
231
  floor, and with the exclusive ceiling one patch above it, it is the whole
229
232
  range.
230
233
 
231
- That is a narrower claim than this page carried before 2026-08-28, and the
234
+ That is the same narrow claim this page has carried since 2026-08-28, and the
232
235
  reason is not that an engine regressed. The `moved` column is measured against
233
236
  **this port's** seam manifest, so re-pinning that manifest moves every row at
234
- once, including rows for engines cut long before it: 2.5.6 read `matches`
235
- under the previous manifest and reads `4 of 16 moved` under this one. A row
237
+ once, including rows for engines cut long before it: 2.6.0 read `matches`
238
+ under the previous manifest and reads `3 of 16 moved` under this one. A row
236
239
  from the old table is not comparable with a row from this one, and neither is
237
240
  a row anyone patches by hand.
238
241
 
239
242
  The consequence is worth stating rather than discovering: **this port has no
240
- fallback engine.** If 2.5.8 were withdrawn, the answer would be to publish a
243
+ fallback engine.** If 2.6.1 were withdrawn, the answer would be to publish a
241
244
  new engine and re-measure, not to widen the range.
242
245
 
243
246
  Two facts about 2.5.5 that this page used to give as floor reasons are still
@@ -258,7 +261,7 @@ stops there with `failed to open file .../cc/src/target/generated.rs`.
258
261
  > reported the estate healthy and exited 0. A green install and a dead run.
259
262
  >
260
263
  > The ceiling is exclusive and sits at the first engine that is not measured
261
- > usable, so a future 2.5.9 is excluded exactly as 2.5.7 is today. Admitting a
264
+ > usable, so a future 2.6.2 is excluded exactly as 2.6.0 is today. Admitting a
262
265
  > new engine is a deliberate act: re-run
263
266
  > `evidence/standalone-20260827/measure_engine_verdicts.py`, splice its JSON
264
267
  > into the table in `hexcore.engine_pin` with
@@ -278,22 +281,22 @@ rows landed the day after the 2.5.2 upload, so published 2.5.2 stages none of
278
281
  them through `gpuwm fetch-bridges`. Both front doors drive those binaries, so
279
282
  a user who resolved onto a 2.5.2 engine could open **neither door**. That is a
280
283
  stranded install rather than a degraded one, and a dependency floor is the
281
- only place pip can refuse it. Measured 2026-08-28 on the pinned engine:
284
+ only place pip can refuse it. Measured 2026-08-28 on the then-pinned engine:
282
285
  `gpuwm fetch-bridges` from a published 2.5.8 install downloads
283
286
  `gpuwm-bridges-v2.5.8-win-x86_64.zip` and stages **26 of 26 artifacts, each
284
287
  verified against the packaged pin** — the four above, plus `rw_wrfbatch` and
285
288
  the `rw_mpas_lbc` the limited-area lane needs.
286
289
 
287
290
  *(The gpuwm source tree publishes too: `github.com/FahrenheitResearch/arwen`
288
- carries tags `v2.5.0` through `v2.5.8` with the full tree, `docs/mpas-seam.md`
291
+ carries tags `v2.5.0` through `v2.6.1` with the full tree, `docs/mpas-seam.md`
289
292
  and `gpuwm/core/mpas_column_batch.py` included. The table above was taken by
290
- cloning all nine of those tags and hashing the pinned files, so the build road
291
- below is open to anyone, subject to the 2.5.5 vendor gap noted above.)*
293
+ hashing the pinned files at all eleven of those tags, so the build road below
294
+ is open to anyone, subject to the 2.5.5 vendor gap noted above.)*
292
295
 
293
296
  **Installing `gpuwm` is necessary but not sufficient for the forecast lane.**
294
297
  The `forecast` door refuses without `--gpuwm-checkout`: a gpuwm **git
295
298
  checkout** at the pinned commit (`--arwen-checkout` on the driver beneath it),
296
- in addition to the installed distribution. Clone `v2.5.8`. This is stated
299
+ in addition to the installed distribution. Clone `v2.6.1`. This is stated
297
300
  plainly because the alternative — discovering it as a `FileNotFoundError` deep
298
301
  in a launch — is the trap; the `forecast` door refuses by name instead, and so
299
302
  does `gpuwm-hex doctor`.
@@ -431,7 +434,7 @@ bundle carries `rw_wrfbatch` and **not** `rw_mpas_init` or `rw_mpas_convert`.
431
434
  On that engine `gpuwm fetch-bridges` gives you the renderer and nothing that
432
435
  opens either MPAS door. That measurement is why the dependency floor cleared
433
436
  2.5.3 and never fell back: 2.5.3 is where the four MPAS bridge binaries
434
- enter the bundle, and the current `gpuwm>=2.5.8,<2.5.9` range keeps that
437
+ enter the bundle, and the current `gpuwm>=2.6.1,<2.6.2` range keeps that
435
438
  guarantee, so pip cannot resolve you onto an engine that strands both doors. A
436
439
  conforming install therefore never sees the 2.5.2 shortfall; it is recorded
437
440
  here because it is the reason the floor first moved.
@@ -536,7 +539,7 @@ bytes can be named by commit, and an install has no commit — and a **gpuwm-hex
536
539
  source checkout** for the drivers under `tools/`, which verify their own
537
540
  executing modules by SHA-256 and therefore cannot live inside the wheel.
538
541
  `gpuwm-hex doctor` reports the same two gaps. The gpuwm one is no longer about
539
- a pinned file the wheel cannot reach: at 2.5.8 all sixteen resolve from an
542
+ a pinned file the wheel cannot reach: since 2.5.8 all sixteen resolve from an
540
543
  install (*The engine pin*).
541
544
 
542
545
  Its inputs are a mesh, a static file and an init. The registry makes the first
@@ -756,15 +759,25 @@ Measured over 24 h, two independent weather cases, two mixing regimes,
756
759
  They entered this repository already finished on 2026-08-20, and there is no
757
760
  receipt directory, no card and no run commit for them anywhere in the tree.
758
761
  What can be established is a ceiling: the commit that introduced them pinned
759
- engine `629ddb6f0`, so they were measured at or before that pin. Three engine
762
+ engine `629ddb6f0`, so they were measured at or before that pin. Five engine
760
763
  pin moves have landed since — `0d04db712` (2026-08-24), `26daaab7e`
761
- (2026-08-25) and `659962929` (2026-08-28). The **last** of the three is
762
- measured to change nothing: a four-arm byte A/B on one card found the old and
763
- new pins identical on the atmosphere half of the per-step fingerprint at all
764
- 31 steps and on 0 of 138 history variables
765
- (`evidence/seam-258-ab-20260828/`) — one mesh, one case, one hour. The two
766
- earlier moves have no such arm, and none of the three magnitudes has been
767
- re-measured over 24 h since. Whether any of them moved is **NOT MEASURED**.
764
+ (2026-08-25), `659962929` (2026-08-28), `7e34a48` (2026-08-31, gpuwm
765
+ 2.6.0) and `df5f34c5c` (2026-09-01, gpuwm 2.6.1). The **2.5.8** move is measured to change nothing: a four-arm byte A/B
766
+ on one card found the old and new pins identical on the atmosphere half of
767
+ the per-step fingerprint at all 31 steps and on 0 of 138 history variables
768
+ (`evidence/seam-258-ab-20260828/`) — one mesh, one case, one hour. The
769
+ **2.6.0** move also crosses the executed seam (`gpuwm/core/rrtmg_legacy.py`
770
+ among its three moved files) and is measured the same way at the same
771
+ scope: the x4 proof re-run at that pin wrote an F001 history byte-identical
772
+ to the 2.5.8 proof's (`evidence/repin-260-20260831/x4-proof/`). The
773
+ **2.6.1** move crosses it a third time, at its centre — the seam's own batch
774
+ driver `gpuwm/core/mpas_column_batch.py` gains restart schema v2 and the P3
775
+ eight-species transport — and is measured the same way at the same scope:
776
+ the x4 proof re-run at that pin wrote all four snapshots (F000, F030, F001
777
+ and the restarted F001) byte-identical to the 2.6.0 proof's, so one F001
778
+ SHA-256 now spans three engines (`evidence/repin-261-20260901/x4-proof/`).
779
+ The two earliest moves have no such arm, and none of the three magnitudes
780
+ has been re-measured over 24 h since. Whether any of them moved is **NOT MEASURED**.
768
781
  Read them as the numbers from the pre-2026-08-20 engine, not as today's.
769
782
 
770
783
  1. **Upper-level warm drift.** Above level 45 the port warms relative to native
@@ -821,7 +834,8 @@ case-independent, which chaos cannot be, and each names a lane to fix.
821
834
  > `--cull-parent`, and `rw_mpas_lbc` was in no bundle and no published source
822
835
  > (measured 2026-08-27, `evidence/userwalk-20260827/RECEIPT.md` — that receipt
823
836
  > is a record of 2.5.7 and is not restated here as current fact). The engine
824
- > then published 2.5.8, which this distribution requires.
837
+ > then published 2.5.8, which this distribution required until it re-pinned
838
+ > onto 2.6.0 and then 2.6.1.
825
839
  >
826
840
  > Measured 2026-08-28 against the real published artefacts: `gpuwm
827
841
  > fetch-bridges` on a 2.5.8 install downloads
@@ -56,11 +56,12 @@ is no receipt directory, no card and no run commit for them anywhere in the
56
56
  tree -- which is the opposite of how the obs-referee numbers below are
57
57
  recorded, and the gap is worth naming rather than papering over. What can be
58
58
  established is a ceiling: the commit that introduced them pinned engine
59
- `629ddb6f0`, so the run happened at or before that pin. Three engine pin moves
60
- have landed since -- `0d04db712` (2026-08-24), `26daaab7e` (2026-08-25) and
61
- `659962929` (2026-08-28, gpuwm 2.5.8).
59
+ `629ddb6f0`, so the run happened at or before that pin. Five engine pin moves
60
+ have landed since -- `0d04db712` (2026-08-24), `26daaab7e` (2026-08-25),
61
+ `659962929` (2026-08-28, gpuwm 2.5.8), `7e34a48` (2026-08-31, gpuwm
62
+ 2.6.0) and `df5f34c5c` (2026-09-01, gpuwm 2.6.1).
62
63
 
63
- The last of those crosses the executed seam and **has now been measured**, in
64
+ The 2.5.8 move crosses the executed seam and **has been measured**, in
64
65
  the strongest form available short of a re-run: a four-arm byte A/B on one
65
66
  RTX 5090, old pin against new pin, x4.163842, 30 composite steps, no tolerance
66
67
  anywhere. The atmosphere half of the per-step fingerprint is identical at all
@@ -71,10 +72,27 @@ digest rolled up over them
71
72
  That is one mesh, one case and one hour, and it is a byte comparison rather
72
73
  than a physics claim.
73
74
 
74
- The two EARLIER pin moves have no such arm, and no magnitude above has been
75
- re-measured over 24 h since the original run. **Whether any of the three moved
76
- across those pins is NOT MEASURED.** Read them as pre-2026-08-20 numbers until
77
- somebody re-runs them.
75
+ The 2026-08-31 move crosses the executed seam too
76
+ (`gpuwm/core/rrtmg_legacy.py` is one of its three moved files, and legacy
77
+ RRTMG is the prime suspect for the drift below), and it carries its own
78
+ one-hour byte arm: the x4 frozen-source proof re-run at that pin wrote an
79
+ F001 history byte-identical to the 2.5.8 proof's -- one SHA-256, two
80
+ engines (receipt `evidence/repin-260-20260831/x4-proof/`). One mesh, one
81
+ case, one hour, same caveat as above.
82
+
83
+ The 2026-09-01 move crosses the executed seam a third time, and at its
84
+ centre: `gpuwm/core/mpas_column_batch.py`, the seam's own batch driver,
85
+ gains restart schema v2 and the P3 eight-species transport (the engine's
86
+ default WSM6 path declared byte-unchanged), with `gpuwm/config.py` and
87
+ `docs/mpas-seam.md` moving beside it. Its arm is the same one-hour byte
88
+ arm: the x4 proof re-run at that pin wrote all four snapshots -- F000,
89
+ F030, F001 and the restarted F001 -- byte-identical to the 2.6.0 proof's,
90
+ so one F001 SHA-256 now spans three engines (receipt
91
+ `evidence/repin-261-20260901/x4-proof/`). Same scope, same caveat. The
92
+ two EARLIEST pin moves have no arm at all, and no magnitude above has been
93
+ re-measured over 24 h since the original run. **Whether any of the three moved across those pins is
94
+ NOT MEASURED.** Read them as pre-2026-08-20 numbers until somebody re-runs
95
+ them.
78
96
 
79
97
  ---
80
98
 
@@ -33,23 +33,24 @@ individual gpuwm source files by SHA-256. A bare install reached an engine the
33
33
  pin refused, and the forecast door refused at launch with a digest mismatch
34
34
  that named neither the version that works nor the fact that pip chose it.
35
35
 
36
- The declaration now carries a bounded range — `gpuwm>=2.5.8,<2.5.9` — so pip
36
+ The declaration now carries a bounded range — `gpuwm>=2.6.1,<2.6.2` — so pip
37
37
  resolves the engine that works and refuses the one that does not. Three things
38
38
  follow that are worth knowing rather than discovering:
39
39
 
40
- - **2.5.8 is the only published engine that matches**, re-measured 2026-08-28
41
- against every published 2.5.x release. So there is no fallback: the range is
42
- one version wide because only one version qualifies.
40
+ - **2.6.1 is the only published engine that matches**, re-measured 2026-09-01
41
+ against every published 2.5.x and 2.6.x release. So there is no fallback:
42
+ the range is one version wide because only one version qualifies.
43
43
  - **A newer gpuwm will not be resolved either.** The ceiling sits at the
44
44
  first engine this port has not measured against the manifest, so a future
45
- 2.5.9 is excluded exactly as 2.5.7 is. That is deliberate: an unmeasured
45
+ 2.6.2 is excluded exactly as 2.6.0 is. That is deliberate: an unmeasured
46
46
  engine is what produced the defect.
47
47
  - **If you already have a different gpuwm in the environment**, `gpuwm-hex
48
48
  doctor` compares the installed engine's bytes against the pin and names
49
49
  both the version it found and the version to install. It is a byte check,
50
50
  not a version check, and it runs by default. On a conforming install it
51
- reads `gpuwm 2.5.8: 16 of 16 pinned files are in this install and all 16
52
- match`.
51
+ reads `gpuwm 2.6.1: 16 of 16 pinned files are in this install and all 16
52
+ match` (measured 2026-09-01 against the published 2.6.1 wheel, in a fresh
53
+ virtualenv holding only the published wheels).
53
54
 
54
55
  Then add the CUDA lane:
55
56
 
@@ -150,7 +151,7 @@ gpuwm you have: the transcript above was taken against the published gpuwm
150
151
  2.5.2 wheel, whose bundle carries `rw_wrfbatch` and **not** `rw_mpas_init`
151
152
  or `rw_mpas_convert` — which is exactly the shortfall the doctor reports
152
153
  there. The four MPAS bridge binaries enter the bundle at gpuwm 2.5.3, and
153
- this distribution's declared range is `gpuwm>=2.5.8,<2.5.9` (the floor is
154
+ this distribution's declared range is `gpuwm>=2.6.1,<2.6.2` (the floor is
154
155
  far past 2.5.3, for the seam bytes the port pins): a conforming install cannot
155
156
  land on the engine that transcript was taken from. Doctor
156
157
  asks the gpuwm you actually have what its bundle declares, so it never sends
@@ -301,7 +302,7 @@ about a minute.
301
302
  The forecast lane is the one step whose answer depends on your hardware, so
302
303
  ask before you spend anything on it. **Both checkouts below are required and
303
304
  neither is optional**: `--repo` is your gpuwm-hex checkout (the drivers are
304
- not in the wheel) and `--gpuwm-checkout` is a gpuwm checkout at **`v2.5.8`**,
305
+ not in the wheel) and `--gpuwm-checkout` is a gpuwm checkout at **`v2.6.1`**,
305
306
  the tag whose bytes the seam pin matches (2.1). Leave `--repo` off and the
306
307
  door refuses before it reads anything else.
307
308
 
@@ -315,7 +316,7 @@ gpuwm-hex forecast --preflight \
315
316
  --hours 1.0 --history-every-minutes 30 \
316
317
  --out work/fc-01 \
317
318
  --repo <gpuwm-hex-checkout>/tree \
318
- --gpuwm-checkout <gpuwm-checkout-at-v2.5.8>
319
+ --gpuwm-checkout <gpuwm-checkout-at-v2.6.1>
319
320
  ```
320
321
 
321
322
  `--gpuwm-checkout` must be a **git clone**, not an unpacked release tarball
@@ -397,7 +398,7 @@ gpuwm-hex forecast \
397
398
  --hours 1.0 --history-every-minutes 30 \
398
399
  --out work/fc-01 \
399
400
  --repo <gpuwm-hex-checkout>/tree \
400
- --gpuwm-checkout <gpuwm-checkout-at-v2.5.8> \
401
+ --gpuwm-checkout <gpuwm-checkout-at-v2.6.1> \
401
402
  --case-label quickstart
402
403
  ```
403
404
 
@@ -113,7 +113,7 @@ icosahedral Goldberg grid at the resolution you ask for and builds the
113
113
  matching static in the same run, with no native toolchain anywhere in the
114
114
  loop. (This door was not present on the published gpuwm 2.5.2 wheel; it
115
115
  arrives with the 2.5.3 bundle, well below the floor this distribution's
116
- declared `gpuwm>=2.5.8,<2.5.9` range requires. The commands below were proven from a `gpuwm` checkout.)
116
+ declared `gpuwm>=2.6.1,<2.6.2` range requires. The commands below were proven from a `gpuwm` checkout.)
117
117
 
118
118
  **See what a card can hold:**
119
119
 
@@ -199,6 +199,41 @@ fifth of a second:
199
199
  gpuwm-hex mesh-plan --spec my-case.json --card rtx-5070-ti
200
200
  ```
201
201
 
202
+ #### Where that gradient is measured (changed 2026-08-29)
203
+
204
+ The transition-band gate is arithmetic on one number, and until 2026-08-29
205
+ the generator sampled that number on a lattice spread evenly over the whole
206
+ globe. At the 50,000 points it used, those sit about 101 km apart, so a
207
+ refinement transition narrower than that was stepped over entirely and the
208
+ receipt reported the flat background the lattice happened to land on. On an
209
+ eight-rung 51.2 km to 200 m ladder it printed 12.12 %/cell for a field that
210
+ reads 37.04, and the build admitted a design its own gate exists to refuse.
211
+ Nothing in the reading said so, because a maximum over points that missed the
212
+ ramp looks exactly like a gentle ramp.
213
+
214
+ The generator now probes where a spec says its regions are — a shell a few
215
+ transition widths wide around each region boundary, resolved across the ramp
216
+ rather than along it — and prints two more fields beside the number:
217
+ `gradient_probe_points`, what the reading cost, and
218
+ `gradient_probe_coverage`, which reads `complete` when every locus where the
219
+ field varies was covered. `gpuwm-hex` refuses to judge a spec on a receipt
220
+ that does not say `complete`, including a receipt from an older engine that
221
+ does not say anything, because a number that is not a measurement is not
222
+ something to gate on.
223
+
224
+ Two consequences worth stating plainly. Specs with ramps hundreds of
225
+ kilometres wide — every swath the threat metrics emit, and the two examples
226
+ above — do not move: the old lattice already resolved them, and their
227
+ readings shift in the fourth decimal. Specs with sub-kilometre cores and
228
+ short ramps do move, sharply, and some designs that used to build now refuse
229
+ before anything is seeded. That is the gate working, not a new restriction:
230
+ the band was always that narrow.
231
+
232
+ And what still is not measured this way: `predicted_cells` and
233
+ `region_attainment` on the same receipt are still integrals over the global
234
+ lattice, with the resolution limit that implies. Only the gradient follows
235
+ the regions.
236
+
202
237
  It prices the spec through the generator's own sizing integral, applies the
203
238
  transition-band gate here (so a spec the build would refuse is refused
204
239
  before the build, with the ramp widening that clears it quoted in the spec's
@@ -193,8 +193,8 @@ from an install. What is missing is the commit — the run writes the
193
193
  checkout's HEAD, tree and dirty paths into every receipt so the executed seam
194
194
  source can be named — so clone the tag instead of copying the files.
195
195
 
196
- **`--gpuwm-checkout ... is gpuwm 2.5.7, and this port's physics seam is
197
- pinned to gpuwm 2.5.8`** — the checkout is a real gpuwm tree at the wrong
196
+ **`--gpuwm-checkout ... is gpuwm 2.5.8, and this port's physics seam is
197
+ pinned to gpuwm 2.6.1`** — the checkout is a real gpuwm tree at the wrong
198
198
  version. The refusal names both versions, lists which of the sixteen pinned
199
199
  files moved, and prints the two commands that close it: the bounded `pip
200
200
  install` and the `git clone --depth 1 --branch v<version>` for the checkout
@@ -147,12 +147,12 @@ by omission.
147
147
  - Distribution and command: `gpuwm-hex`. Import namespace: `hexcore`,
148
148
  renamed from `mpas_port` at 0.2.0 and settled there (README, *The import
149
149
  namespace*). There is no alias shim.
150
- - Engine range: `gpuwm>=2.5.8,<2.5.9` is what pip enforces — a bounded
150
+ - Engine range: `gpuwm>=2.6.1,<2.6.2` is what pip enforces — a bounded
151
151
  range, derived from a measured table in `hexcore.engine_pin` rather than
152
152
  typed. The floor is where it is for one reason and it is the strictest
153
- one: 2.5.8 is the only published engine whose bytes match the sixteen-file
154
- Arwen seam manifest, re-measured 2026-08-28 against every published 2.5.x
155
- release. It clears, incidentally, the bundle rows that put the MPAS bridge
153
+ one: 2.6.1 is the only published engine whose bytes match the sixteen-file
154
+ Arwen seam manifest, re-measured 2026-09-01 against every published 2.5.x
155
+ and 2.6.x release. It clears, incidentally, the bundle rows that put the MPAS bridge
156
156
  binaries (`rw_mpas_init`, `rw_mpas_convert`, `rw_mpas_mesh`,
157
157
  `rw_mpas_static`, `rw_mpas_lbc`) within reach of `gpuwm fetch-bridges`;
158
158
  published 2.5.2 carries none of them and would strand every door that
@@ -162,7 +162,7 @@ by omission.
162
162
  forecast lane's real wall is stricter still: the sixteen-file seam
163
163
  manifest, plus a *git* checkout at the pinned commit for receipt
164
164
  provenance (chapter 6.1). `gpuwm-hex doctor` compares the installed
165
- engine's bytes against the manifest and names the version it found; at
165
+ engine's bytes against the manifest and names the version it found; since
166
166
  2.5.8 all sixteen pinned paths resolve from the install, so the checkout
167
167
  is owed for the commit rather than for a file.
168
168
  - Licence: Apache-2.0, with the MPAS-Atmosphere BSD-3-Clause notice
@@ -43,14 +43,14 @@ independent port and is not affiliated with or endorsed by them.)*
43
43
 
44
44
  **Every command was run before it was printed.** Each command block in this
45
45
  manual was executed against the real artifact it documents — the installed
46
- 0.2.0 wheel for the doors, the repository tools for the forecast lane, a CUDA
46
+ 0.2.1 wheel for the doors, the repository tools for the forecast lane, a CUDA
47
47
  node for anything that needs a card — before it was written down. Where a
48
48
  command's output is shown, it is the output that run produced, with machine
49
49
  home directories shortened to `~`.
50
50
 
51
51
  **What a walk of this manual actually reaches.** On 2026-08-27 the printed
52
52
  commands were executed in printed order, from an empty environment, against
53
- the built 0.2.0 wheel and the *published* engine, by somebody following the
53
+ the built 0.2.1 wheel and the *published* engine, by somebody following the
54
54
  page rather than remembering the code. Install, `doctor`, `mesh-check`, the
55
55
  init door, the forecast door and the render door all reach real output —
56
56
  16 min 46 s from an empty machine to the first rendered products. Three
@@ -60,7 +60,7 @@ re-measured 2026-08-28 against the published bundle: the **limited-area lane**
60
60
  of chapter 6.8 and the `cull` door of chapter 9 have the engine capabilities
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  they need, and the render door's **default window** is understood by the
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  published converter. The third stands, with a narrower reason than it had: the forecast lane needs
63
- a `gpuwm` **git** checkout at **v2.5.8**, not just whatever pip installs — not
63
+ a `gpuwm` **git** checkout at **v2.6.1**, not just whatever pip installs — not
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  because a pinned file is missing from the wheel (at 2.5.8 all sixteen resolve
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  from `site-packages`, measured 2026-08-28) but because the run records the
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  checkout's HEAD, tree and dirty paths into every receipt. Each is written
@@ -77,7 +77,7 @@ three measured, physics-shaped ways. They are stated in chapter 3, quantified
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  in [`docs/declared-divergences.md`](../declared-divergences.md), and never
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  hidden behind an option. Read them before trusting a number.
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80
- **Version.** This manual describes gpuwm-hex 0.2.0 with the gpuwm 2.5.x
80
+ **Version.** This manual describes gpuwm-hex 0.2.2 with the gpuwm 2.6.x
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  engine line. Where a measurement was taken on specific hardware, the card is
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  named beside the number.
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