gpuwm-hex 0.2.0__tar.gz → 0.2.2__tar.gz
This diff represents the content of publicly available package versions that have been released to one of the supported registries. The information contained in this diff is provided for informational purposes only and reflects changes between package versions as they appear in their respective public registries.
- {gpuwm_hex-0.2.0/src/gpuwm_hex.egg-info → gpuwm_hex-0.2.2}/PKG-INFO +54 -40
- {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/README.md +52 -38
- {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/docs/declared-divergences.md +26 -8
- {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/docs/manual/02-quickstart.md +12 -11
- {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/docs/manual/04-meshes-and-static.md +36 -1
- {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/docs/manual/08-troubleshooting.md +2 -2
- {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/docs/manual/09-reference.md +5 -5
- {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/docs/manual/index.md +4 -4
- {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/pyproject.toml +11 -9
- {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2/src/gpuwm_hex.egg-info}/PKG-INFO +54 -40
- {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/src/gpuwm_hex.egg-info/SOURCES.txt +3 -0
- {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/src/gpuwm_hex.egg-info/requires.txt +1 -1
- {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/src/hexcore/cuda_arwen_physics_v841.py +12 -12
- {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/src/hexcore/engine_pin.py +55 -18
- {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/src/hexcore/libm_identity.py +59 -0
- {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/src/hexcore/mesh.py +151 -0
- {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/src/hexcore/mesh_spec_gates.py +149 -16
- {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/src/hexcore/physics_seam.py +135 -11
- {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/src/hexcore/rkind_libm.py +1 -1
- {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/src/hexcore/swath/sizing.py +35 -1
- {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/src/hexcore/vertical.py +1 -1
- {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/tests/test_convection_admission.py +42 -18
- {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/tests/test_cuda_v841_full_physics_x4.py +2 -2
- {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/tests/test_engine_pin.py +35 -15
- {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/tests/test_libm_identity.py +2 -2
- {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/tests/test_mesh_spec_gates.py +180 -20
- {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/tests/test_mesh_validation.py +137 -0
- gpuwm_hex-0.2.2/tests/test_p3_seam_ab.py +309 -0
- {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/tests/test_packaging_declaration.py +6 -5
- {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/tests/test_proof_guard_pins.py +2 -2
- {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/tests/test_regional_physics_seam.py +113 -0
- {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/tests/test_swath_door.py +101 -5
- gpuwm_hex-0.2.2/tests/test_tier_membership.py +201 -0
- gpuwm_hex-0.2.2/tests/test_tracked_file_writers_keep_lf.py +185 -0
- {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/tests/test_vertical_vectorized_equivalence.py +42 -0
- gpuwm_hex-0.2.2/tools/battery/cpu_files.txt +213 -0
- {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/tools/battery/gpu_gates.txt +8 -0
- {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/tools/mpas_mesh_binding.py +96 -0
- {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/tools/probe_swath_spec_generable.py +35 -6
- {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/tools/run_cuda_v841_full_physics_x4.py +3 -3
- gpuwm_hex-0.2.0/tools/battery/cpu_files.txt +0 -92
- {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/LICENSE +0 -0
- {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/MANIFEST.in +0 -0
- {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/NOTICE +0 -0
- {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/docs/cycle-door.md +0 -0
- {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/docs/device-memory-ledger.md +0 -0
- {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/docs/init-door.md +0 -0
- {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/docs/manual/01-what-this-is.md +0 -0
- {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/docs/manual/03-concepts.md +0 -0
- {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/docs/manual/05-initial-conditions.md +0 -0
- {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/docs/manual/06-forecast.md +0 -0
- {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/docs/manual/07-render.md +0 -0
- {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/docs/native-free-init-admission.md +0 -0
- {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/docs/obs-referee.md +0 -0
- {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/docs/render-door.md +0 -0
- {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/docs/source-matrix.md +0 -0
- {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/evidence/EVIDENCE.md +0 -0
- {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/setup.cfg +0 -0
- {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/src/gpuwm_hex.egg-info/dependency_links.txt +0 -0
- {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/src/gpuwm_hex.egg-info/entry_points.txt +0 -0
- {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/src/gpuwm_hex.egg-info/top_level.txt +0 -0
- {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/src/hexcore/__init__.py +0 -0
- {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/src/hexcore/__main__.py +0 -0
- {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/src/hexcore/acoustic.py +0 -0
- {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/src/hexcore/acoustic_v841.py +0 -0
- {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/src/hexcore/cascade_row.py +0 -0
- {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/src/hexcore/cell_coordination_admission.py +0 -0
- {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/src/hexcore/cli.py +0 -0
- {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/src/hexcore/config.py +0 -0
- {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/src/hexcore/config_lts.py +0 -0
- {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/src/hexcore/config_v841.py +0 -0
- {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/src/hexcore/convection_admission.py +0 -0
- {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/src/hexcore/cuda_acoustic.py +0 -0
- {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/src/hexcore/cuda_acoustic_lts.py +0 -0
- {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/src/hexcore/cuda_acoustic_v841.py +0 -0
- {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/src/hexcore/cuda_backend/__init__.py +0 -0
- {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/src/hexcore/cuda_backend/arch_admission.py +0 -0
- {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/src/hexcore/cuda_backend/compile_contract.py +0 -0
- {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/src/hexcore/cuda_backend/containers.py +0 -0
- {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/src/hexcore/cuda_backend/recovery.py +0 -0
- {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/src/hexcore/cuda_backend/regional_admission.py +0 -0
- {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/src/hexcore/cuda_backend/runtime.py +0 -0
- {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/src/hexcore/cuda_driver.py +0 -0
- {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/src/hexcore/cuda_driver_lts.py +0 -0
- {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/src/hexcore/cuda_dualrun.py +0 -0
- {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/src/hexcore/cuda_dynamics_v841.py +0 -0
- {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/src/hexcore/cuda_fp32.py +0 -0
- {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/src/hexcore/cuda_ftz.py +0 -0
- {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/src/hexcore/cuda_ftz_v841.py +0 -0
- {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/src/hexcore/cuda_gwdo_v841.py +0 -0
- {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/src/hexcore/cuda_horizontal.py +0 -0
- {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/src/hexcore/cuda_horizontal_v841.py +0 -0
- {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/src/hexcore/cuda_physics_prep_v841.py +0 -0
- {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/src/hexcore/cuda_physics_tier_park_v841.py +0 -0
- {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/src/hexcore/cuda_physics_v841.py +0 -0
- {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/src/hexcore/cuda_regional_forecast_v841.py +0 -0
- {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/src/hexcore/cuda_regional_v841.py +0 -0
- {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/src/hexcore/cuda_transport.py +0 -0
- {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/src/hexcore/cuda_transport_v841.py +0 -0
- {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/src/hexcore/cuda_v841.py +0 -0
- {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/src/hexcore/cull_door.py +0 -0
- {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/src/hexcore/cycle/__init__.py +0 -0
- {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/src/hexcore/cycle/chain.py +0 -0
- {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/src/hexcore/cycle/delayed_start.py +0 -0
- {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/src/hexcore/cycle/door.py +0 -0
- {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/src/hexcore/cycle/errors.py +0 -0
- {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/src/hexcore/damping_v841.py +0 -0
- {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/src/hexcore/data/swath/placement-policy.v2.json +0 -0
- {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/src/hexcore/data/swath/threat-metrics.v3.json +0 -0
- {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/src/hexcore/device_admission.py +0 -0
- {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/src/hexcore/diagnostics.py +0 -0
- {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/src/hexcore/doctor.py +0 -0
- {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/src/hexcore/driver.py +0 -0
- {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/src/hexcore/dt_admission.py +0 -0
- {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/src/hexcore/dual_edge_admission.py +0 -0
- {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/src/hexcore/dynamics.py +0 -0
- {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/src/hexcore/dynamics_v841.py +0 -0
- {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/src/hexcore/engines.py +0 -0
- {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/src/hexcore/errors.py +0 -0
- {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/src/hexcore/forecast_door.py +0 -0
- {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/src/hexcore/horizontal.py +0 -0
- {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/src/hexcore/init_door.py +0 -0
- {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/src/hexcore/initialization.py +0 -0
- {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/src/hexcore/integration.py +0 -0
- {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/src/hexcore/integration_v841.py +0 -0
- {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/src/hexcore/lbc.py +0 -0
- {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/src/hexcore/lts_v841.py +0 -0
- {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/src/hexcore/mesh_plan_door.py +0 -0
- {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/src/hexcore/mesh_row_candidate.py +0 -0
- {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/src/hexcore/mixing.py +0 -0
- {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/src/hexcore/mixing_v841.py +0 -0
- {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/src/hexcore/nomix_oracle.py +0 -0
- {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/src/hexcore/obs_referee/__init__.py +0 -0
- {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/src/hexcore/obs_referee/__main__.py +0 -0
- {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/src/hexcore/obs_referee/acquire.py +0 -0
- {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/src/hexcore/obs_referee/align.py +0 -0
- {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/src/hexcore/obs_referee/bootstrap.py +0 -0
- {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/src/hexcore/obs_referee/bundle.py +0 -0
- {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/src/hexcore/obs_referee/canonical.py +0 -0
- {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/src/hexcore/obs_referee/cli.py +0 -0
- {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/src/hexcore/obs_referee/errors.py +0 -0
- {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/src/hexcore/obs_referee/manifest.py +0 -0
- {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/src/hexcore/obs_referee/metrics.py +0 -0
- {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/src/hexcore/obs_referee/report.py +0 -0
- {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/src/hexcore/obs_referee/runner.py +0 -0
- {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/src/hexcore/obs_referee/scorecard.py +0 -0
- {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/src/hexcore/obs_referee/treatment.py +0 -0
- {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/src/hexcore/offcentering_v841.py +0 -0
- {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/src/hexcore/oracle.py +0 -0
- {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/src/hexcore/output.py +0 -0
- {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/src/hexcore/partition_assets_v841.py +0 -0
- {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/src/hexcore/partition_device_scheduler_v841.py +0 -0
- {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/src/hexcore/partition_executor_v841.py +0 -0
- {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/src/hexcore/partition_local_mesh_v841.py +0 -0
- {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/src/hexcore/partition_net_v841.py +0 -0
- {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/src/hexcore/partition_state_v841.py +0 -0
- {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/src/hexcore/pbl_cadence.py +0 -0
- {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/src/hexcore/physics_backend_admission.py +0 -0
- {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/src/hexcore/physics_seam_v841.py +0 -0
- {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/src/hexcore/regional_v841.py +0 -0
- {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/src/hexcore/regrid.py +0 -0
- {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/src/hexcore/render_door.py +0 -0
- {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/src/hexcore/rust_renderer.py +0 -0
- {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/src/hexcore/shipped_sources.py +0 -0
- {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/src/hexcore/state.py +0 -0
- {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/src/hexcore/step_oracle.py +0 -0
- {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/src/hexcore/swath/__init__.py +0 -0
- {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/src/hexcore/swath/detect.py +0 -0
- {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/src/hexcore/swath/door.py +0 -0
- {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/src/hexcore/swath/errors.py +0 -0
- {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/src/hexcore/swath/geometry.py +0 -0
- {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/src/hexcore/swath/history.py +0 -0
- {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/src/hexcore/swath/hysteresis.py +0 -0
- {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/src/hexcore/swath/plan.py +0 -0
- {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/src/hexcore/swath/rank.py +0 -0
- {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/src/hexcore/swath/registry.py +0 -0
- {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/src/hexcore/swath/track.py +0 -0
- {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/src/hexcore/terrain.py +0 -0
- {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/src/hexcore/timestep_admission.py +0 -0
- {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/src/hexcore/tracer_oracle.py +0 -0
- {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/src/hexcore/transport.py +0 -0
- {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/src/hexcore/vector.py +0 -0
- {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/src/hexcore/vertical_spec.py +0 -0
- {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/src/hexcore/wps_intermediate.py +0 -0
- {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/tests/conftest.py +0 -0
- {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/tests/test_admission_strings.py +0 -0
- {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/tests/test_arch_admission.py +0 -0
- {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/tests/test_capacity_copy_elisions.py +0 -0
- {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/tests/test_cell_coordination_admission.py +0 -0
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- {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/verification/vertical-specs/native-comparison-policy.NOT-MEASURED.json +0 -0
- {gpuwm_hex-0.2.0 → gpuwm_hex-0.2.2}/verification/vertical-specs/tc55-v1.json +0 -0
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Name: gpuwm-hex
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Version: 0.2.
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Summary: GPU global atmospheric model on unstructured Voronoi meshes: a CUDA port of the MPAS-A v8.4.1 dycore with ArWen physics, arbitrary mesh generation, and single-card mesh streaming for 12-16 GB GPUs.
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| GPU | A CUDA device. Memory is set by mesh size *and* by the card, and not by a line through the two: the footprint is a per-card core, plus the Grell-Freitas and YSU column workspaces charged at `min(cells, tile)`, plus a per-cell term, all in `hexcore.device_admission`. Measured 2026-08-26 on an RTX 5090 at the merged tip: the published 40,962-cell global mesh (x1.40962, about 120 km) peaked at **8,874 MiB — inside a 12 GiB card's budget**; the 163,842-cell mesh (x4.163842, about 24 km) peaked at **20,446 MiB**, and every free-memory gate admits at the measured floor — the prediction plus that card's own margin, **about 21.7 GiB free at x4** — so x4 remains in practice a 32 GiB-card configuration. The core is a property of the card, not the mesh, and the door reads the card's multiprocessor count at the decision rather than assuming a 5090: the 16 GiB and 10 GiB parts each carry their own measured row, and a card nobody has measured gets a derived row that is labelled derived. A card with its own #264 ledger can still supply it with `--device-fixed-mib` / `--device-bytes-per-cell`. Receipts: `evidence/memory-row-refit-20260826/node2/`, `evidence/l6-capacity-20260825/` and `evidence/memory-shape-20260827/`. |
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| CUDA | CuPy matching your driver's CUDA major — there is no way for pip to detect it, so you choose (below). |
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| Engine | The `gpuwm` distribution, `>=2.
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| Engine | The `gpuwm` distribution, `>=2.6.1,<2.6.2` — a bounded range, and pip resolves it for you: the physics seam, and the bundle that carries the MPAS bridge binaries the doors drive. **Plus a `gpuwm` source checkout at `v2.6.1` for the forecast lane** — see *The engine pin*. |
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| Assets | A mesh grid file, a matching static file, and (for the init door) a vertical-grid declaration — normally a `--vertical-spec` JSON; a native-minted init file as a capsule is the compatibility mode. **gpuwm-hex ships none of these and has no fetch path for them.** See *Assets you must supply*. |
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| Rust binaries | `rw_mpas_init` for the init door; `rw_mpas_convert` and `rw_wrfbatch` for the render door. They are built from the `gpuwm` source tree — see *Building the Rust engines*. |
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### The engine pin
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gpuwm-hex depends on `gpuwm>=2.6.1,<2.6.2` — a **bounded range**, and the
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bound is the point. The port pins the engine's physics seam by the SHA-256 of
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**sixteen individual gpuwm source files**, and the gap between a published
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`evidence/repin-
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stamp and the pinned bytes has recurred at every cut. Re-measured 2026-09-01
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against the real published bytes of every 2.5.x and 2.6.x release, plus the
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`evidence/repin-261-20260901/engine-verdicts.json`, instrument at
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`evidence/standalone-20260827/measure_engine_verdicts.py`:
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| gpuwm | on PyPI | seam pin | `--offline` build road |
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| 2.5.0 | yes |
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| 2.5.1 | yes |
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| 2.5.0 | yes | 11 of 16 moved | complete |
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| 2.5.1 | yes | 11 of 16 moved | complete |
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| 2.5.2 | yes | 10 of 16 moved | complete |
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| 2.5.5 | **no — a git tag with no release** | 7 of 16 moved | **broken** |
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| 2.5.6 | yes | 7 of 16 moved | complete |
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| 2.5.7 | yes | 6 of 16 moved | complete |
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| 2.5.8 | yes | 5 of 16 moved | complete |
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| 2.6.0 | yes | 3 of 16 moved | complete |
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| **2.6.1** | yes | **matches** | complete |
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floor, and with the exclusive ceiling one patch above it, it is the whole
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under the previous manifest and reads `3 of 16 moved` under this one. A row
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The consequence is worth stating rather than discovering: **this port has no
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fallback engine.** If 2.
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fallback engine.** If 2.6.1 were withdrawn, the answer would be to publish a
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> into the table in `hexcore.engine_pin` with
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them through `gpuwm fetch-bridges`. Both front doors drive those binaries, so
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verified against the packaged pin** — the four above, plus `rw_wrfbatch` and
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the `rw_mpas_lbc` the limited-area lane needs.
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*(The gpuwm source tree publishes too: `github.com/FahrenheitResearch/arwen`
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carries tags `v2.5.0` through `v2.
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carries tags `v2.5.0` through `v2.6.1` with the full tree, `docs/mpas-seam.md`
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and `gpuwm/core/mpas_column_batch.py` included. The table above was taken by
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hashing the pinned files at all eleven of those tags, so the build road below
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is open to anyone, subject to the 2.5.5 vendor gap noted above.)*
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**Installing `gpuwm` is necessary but not sufficient for the forecast lane.**
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The `forecast` door refuses without `--gpuwm-checkout`: a gpuwm **git
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checkout** at the pinned commit (`--arwen-checkout` on the driver beneath it),
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in addition to the installed distribution. Clone `v2.
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in addition to the installed distribution. Clone `v2.6.1`. This is stated
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plainly because the alternative — discovering it as a `FileNotFoundError` deep
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in a launch — is the trap; the `forecast` door refuses by name instead, and so
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does `gpuwm-hex doctor`.
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On that engine `gpuwm fetch-bridges` gives you the renderer and nothing that
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opens either MPAS door. That measurement is why the dependency floor cleared
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2.5.3 and never fell back: 2.5.3 is where the four MPAS bridge binaries
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enter the bundle, and the current `gpuwm>=2.
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enter the bundle, and the current `gpuwm>=2.6.1,<2.6.2` range keeps that
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guarantee, so pip cannot resolve you onto an engine that strands both doors. A
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conforming install therefore never sees the 2.5.2 shortfall; it is recorded
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here because it is the reason the floor first moved.
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source checkout** for the drivers under `tools/`, which verify their own
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executing modules by SHA-256 and therefore cannot live inside the wheel.
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`gpuwm-hex doctor` reports the same two gaps. The gpuwm one is no longer about
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a pinned file the wheel cannot reach:
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a pinned file the wheel cannot reach: since 2.5.8 all sixteen resolve from an
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install (*The engine pin*).
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Its inputs are a mesh, a static file and an init. The registry makes the first
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@@ -794,15 +797,25 @@ Measured over 24 h, two independent weather cases, two mixing regimes,
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They entered this repository already finished on 2026-08-20, and there is no
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receipt directory, no card and no run commit for them anywhere in the tree.
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What can be established is a ceiling: the commit that introduced them pinned
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engine `629ddb6f0`, so they were measured at or before that pin.
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engine `629ddb6f0`, so they were measured at or before that pin. Five engine
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pin moves have landed since — `0d04db712` (2026-08-24), `26daaab7e`
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(2026-08-25)
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measured to change nothing: a four-arm byte A/B
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new pins identical on the atmosphere half of
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31 steps and on 0 of 138 history variables
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(`evidence/seam-258-ab-20260828/`) — one mesh, one case, one hour. The
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(2026-08-25), `659962929` (2026-08-28), `7e34a48` (2026-08-31, gpuwm
|
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803
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2.6.0) and `df5f34c5c` (2026-09-01, gpuwm 2.6.1). The **2.5.8** move is measured to change nothing: a four-arm byte A/B
|
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on one card found the old and new pins identical on the atmosphere half of
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the per-step fingerprint at all 31 steps and on 0 of 138 history variables
|
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(`evidence/seam-258-ab-20260828/`) — one mesh, one case, one hour. The
|
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807
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**2.6.0** move also crosses the executed seam (`gpuwm/core/rrtmg_legacy.py`
|
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among its three moved files) and is measured the same way at the same
|
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809
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scope: the x4 proof re-run at that pin wrote an F001 history byte-identical
|
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to the 2.5.8 proof's (`evidence/repin-260-20260831/x4-proof/`). The
|
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811
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**2.6.1** move crosses it a third time, at its centre — the seam's own batch
|
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812
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+
driver `gpuwm/core/mpas_column_batch.py` gains restart schema v2 and the P3
|
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813
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eight-species transport — and is measured the same way at the same scope:
|
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the x4 proof re-run at that pin wrote all four snapshots (F000, F030, F001
|
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815
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and the restarted F001) byte-identical to the 2.6.0 proof's, so one F001
|
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816
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SHA-256 now spans three engines (`evidence/repin-261-20260901/x4-proof/`).
|
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817
|
+
The two earliest moves have no such arm, and none of the three magnitudes
|
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+
has been re-measured over 24 h since. Whether any of them moved is **NOT MEASURED**.
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Read them as the numbers from the pre-2026-08-20 engine, not as today's.
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1. **Upper-level warm drift.** Above level 45 the port warms relative to native
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@@ -859,7 +872,8 @@ case-independent, which chaos cannot be, and each names a lane to fix.
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> `--cull-parent`, and `rw_mpas_lbc` was in no bundle and no published source
|
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860
873
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> (measured 2026-08-27, `evidence/userwalk-20260827/RECEIPT.md` — that receipt
|
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> is a record of 2.5.7 and is not restated here as current fact). The engine
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862
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-
> then published 2.5.8, which this distribution
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+
> then published 2.5.8, which this distribution required until it re-pinned
|
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> onto 2.6.0 and then 2.6.1.
|
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877
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>
|
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878
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> Measured 2026-08-28 against the real published artefacts: `gpuwm
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> fetch-bridges` on a 2.5.8 install downloads
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@@ -144,7 +144,7 @@ verdict for each divergence is in
|
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144
144
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| Python | 3.11 or newer |
|
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145
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| GPU | A CUDA device. Memory is set by mesh size *and* by the card, and not by a line through the two: the footprint is a per-card core, plus the Grell-Freitas and YSU column workspaces charged at `min(cells, tile)`, plus a per-cell term, all in `hexcore.device_admission`. Measured 2026-08-26 on an RTX 5090 at the merged tip: the published 40,962-cell global mesh (x1.40962, about 120 km) peaked at **8,874 MiB — inside a 12 GiB card's budget**; the 163,842-cell mesh (x4.163842, about 24 km) peaked at **20,446 MiB**, and every free-memory gate admits at the measured floor — the prediction plus that card's own margin, **about 21.7 GiB free at x4** — so x4 remains in practice a 32 GiB-card configuration. The core is a property of the card, not the mesh, and the door reads the card's multiprocessor count at the decision rather than assuming a 5090: the 16 GiB and 10 GiB parts each carry their own measured row, and a card nobody has measured gets a derived row that is labelled derived. A card with its own #264 ledger can still supply it with `--device-fixed-mib` / `--device-bytes-per-cell`. Receipts: `evidence/memory-row-refit-20260826/node2/`, `evidence/l6-capacity-20260825/` and `evidence/memory-shape-20260827/`. |
|
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146
|
| CUDA | CuPy matching your driver's CUDA major — there is no way for pip to detect it, so you choose (below). |
|
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147
|
-
| Engine | The `gpuwm` distribution, `>=2.
|
|
147
|
+
| Engine | The `gpuwm` distribution, `>=2.6.1,<2.6.2` — a bounded range, and pip resolves it for you: the physics seam, and the bundle that carries the MPAS bridge binaries the doors drive. **Plus a `gpuwm` source checkout at `v2.6.1` for the forecast lane** — see *The engine pin*. |
|
|
148
148
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| Assets | A mesh grid file, a matching static file, and (for the init door) a vertical-grid declaration — normally a `--vertical-spec` JSON; a native-minted init file as a capsule is the compatibility mode. **gpuwm-hex ships none of these and has no fetch path for them.** See *Assets you must supply*. |
|
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| Rust binaries | `rw_mpas_init` for the init door; `rw_mpas_convert` and `rw_wrfbatch` for the render door. They are built from the `gpuwm` source tree — see *Building the Rust engines*. |
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### The engine pin
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gpuwm-hex depends on `gpuwm>=2.
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gpuwm-hex depends on `gpuwm>=2.6.1,<2.6.2` — a **bounded range**, and the
|
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bound is the point. The port pins the engine's physics seam by the SHA-256 of
|
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209
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**sixteen individual gpuwm source files**, and the gap between a published
|
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210
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stamp and the pinned bytes has recurred at every cut. Re-measured 2026-
|
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against the real published bytes of every 2.5.x release, plus the
|
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212
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that has no release at all — JSON at
|
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`evidence/repin-
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stamp and the pinned bytes has recurred at every cut. Re-measured 2026-09-01
|
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against the real published bytes of every 2.5.x and 2.6.x release, plus the
|
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`v2.5.5` tag that has no release at all — JSON at
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`evidence/repin-261-20260901/engine-verdicts.json`, instrument at
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`evidence/standalone-20260827/measure_engine_verdicts.py`:
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| gpuwm | on PyPI | seam pin | `--offline` build road |
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217
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| --- | --- | --- | --- |
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217
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-
| 2.5.0 | yes |
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218
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-
| 2.5.1 | yes |
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219
|
-
| 2.5.2 | yes |
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220
|
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| 2.5.3 | yes |
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| 2.5.4 | yes |
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|
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| 2.5.5 | **no — a git tag with no release** |
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-
| 2.5.6 | yes |
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-
| 2.5.7 | yes |
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-
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-
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-
**2.
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| 2.5.0 | yes | 11 of 16 moved | complete |
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+
| 2.5.1 | yes | 11 of 16 moved | complete |
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220
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+
| 2.5.2 | yes | 10 of 16 moved | complete |
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221
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+
| 2.5.3 | yes | 7 of 16 moved | complete |
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+
| 2.5.4 | yes | 7 of 16 moved | complete |
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| 2.5.5 | **no — a git tag with no release** | 7 of 16 moved | **broken** |
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+
| 2.5.6 | yes | 7 of 16 moved | complete |
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225
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+
| 2.5.7 | yes | 6 of 16 moved | complete |
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226
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+
| 2.5.8 | yes | 5 of 16 moved | complete |
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| 2.6.0 | yes | 3 of 16 moved | complete |
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| **2.6.1** | yes | **matches** | complete |
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+
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+
**2.6.1 is the only published engine whose bytes match the pin**, so it is the
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floor, and with the exclusive ceiling one patch above it, it is the whole
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range.
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-
That is
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+
That is the same narrow claim this page has carried since 2026-08-28, and the
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reason is not that an engine regressed. The `moved` column is measured against
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**this port's** seam manifest, so re-pinning that manifest moves every row at
|
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once, including rows for engines cut long before it: 2.
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-
under the previous manifest and reads `
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+
once, including rows for engines cut long before it: 2.6.0 read `matches`
|
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under the previous manifest and reads `3 of 16 moved` under this one. A row
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from the old table is not comparable with a row from this one, and neither is
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a row anyone patches by hand.
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241
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The consequence is worth stating rather than discovering: **this port has no
|
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-
fallback engine.** If 2.
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+
fallback engine.** If 2.6.1 were withdrawn, the answer would be to publish a
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new engine and re-measure, not to widen the range.
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Two facts about 2.5.5 that this page used to give as floor reasons are still
|
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@@ -258,7 +261,7 @@ stops there with `failed to open file .../cc/src/target/generated.rs`.
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> reported the estate healthy and exited 0. A green install and a dead run.
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>
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> The ceiling is exclusive and sits at the first engine that is not measured
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> usable, so a future 2.
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+
> usable, so a future 2.6.2 is excluded exactly as 2.6.0 is today. Admitting a
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> new engine is a deliberate act: re-run
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> `evidence/standalone-20260827/measure_engine_verdicts.py`, splice its JSON
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> into the table in `hexcore.engine_pin` with
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@@ -278,22 +281,22 @@ rows landed the day after the 2.5.2 upload, so published 2.5.2 stages none of
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them through `gpuwm fetch-bridges`. Both front doors drive those binaries, so
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a user who resolved onto a 2.5.2 engine could open **neither door**. That is a
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stranded install rather than a degraded one, and a dependency floor is the
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-
only place pip can refuse it. Measured 2026-08-28 on the pinned engine:
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+
only place pip can refuse it. Measured 2026-08-28 on the then-pinned engine:
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`gpuwm fetch-bridges` from a published 2.5.8 install downloads
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`gpuwm-bridges-v2.5.8-win-x86_64.zip` and stages **26 of 26 artifacts, each
|
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verified against the packaged pin** — the four above, plus `rw_wrfbatch` and
|
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the `rw_mpas_lbc` the limited-area lane needs.
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*(The gpuwm source tree publishes too: `github.com/FahrenheitResearch/arwen`
|
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|
-
carries tags `v2.5.0` through `v2.
|
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+
carries tags `v2.5.0` through `v2.6.1` with the full tree, `docs/mpas-seam.md`
|
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and `gpuwm/core/mpas_column_batch.py` included. The table above was taken by
|
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-
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-
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+
hashing the pinned files at all eleven of those tags, so the build road below
|
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+
is open to anyone, subject to the 2.5.5 vendor gap noted above.)*
|
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|
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**Installing `gpuwm` is necessary but not sufficient for the forecast lane.**
|
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The `forecast` door refuses without `--gpuwm-checkout`: a gpuwm **git
|
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checkout** at the pinned commit (`--arwen-checkout` on the driver beneath it),
|
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|
-
in addition to the installed distribution. Clone `v2.
|
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|
+
in addition to the installed distribution. Clone `v2.6.1`. This is stated
|
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plainly because the alternative — discovering it as a `FileNotFoundError` deep
|
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in a launch — is the trap; the `forecast` door refuses by name instead, and so
|
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does `gpuwm-hex doctor`.
|
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@@ -431,7 +434,7 @@ bundle carries `rw_wrfbatch` and **not** `rw_mpas_init` or `rw_mpas_convert`.
|
|
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434
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On that engine `gpuwm fetch-bridges` gives you the renderer and nothing that
|
|
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435
|
opens either MPAS door. That measurement is why the dependency floor cleared
|
|
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436
|
2.5.3 and never fell back: 2.5.3 is where the four MPAS bridge binaries
|
|
434
|
-
enter the bundle, and the current `gpuwm>=2.
|
|
437
|
+
enter the bundle, and the current `gpuwm>=2.6.1,<2.6.2` range keeps that
|
|
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438
|
guarantee, so pip cannot resolve you onto an engine that strands both doors. A
|
|
436
439
|
conforming install therefore never sees the 2.5.2 shortfall; it is recorded
|
|
437
440
|
here because it is the reason the floor first moved.
|
|
@@ -536,7 +539,7 @@ bytes can be named by commit, and an install has no commit — and a **gpuwm-hex
|
|
|
536
539
|
source checkout** for the drivers under `tools/`, which verify their own
|
|
537
540
|
executing modules by SHA-256 and therefore cannot live inside the wheel.
|
|
538
541
|
`gpuwm-hex doctor` reports the same two gaps. The gpuwm one is no longer about
|
|
539
|
-
a pinned file the wheel cannot reach:
|
|
542
|
+
a pinned file the wheel cannot reach: since 2.5.8 all sixteen resolve from an
|
|
540
543
|
install (*The engine pin*).
|
|
541
544
|
|
|
542
545
|
Its inputs are a mesh, a static file and an init. The registry makes the first
|
|
@@ -756,15 +759,25 @@ Measured over 24 h, two independent weather cases, two mixing regimes,
|
|
|
756
759
|
They entered this repository already finished on 2026-08-20, and there is no
|
|
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760
|
receipt directory, no card and no run commit for them anywhere in the tree.
|
|
758
761
|
What can be established is a ceiling: the commit that introduced them pinned
|
|
759
|
-
engine `629ddb6f0`, so they were measured at or before that pin.
|
|
762
|
+
engine `629ddb6f0`, so they were measured at or before that pin. Five engine
|
|
760
763
|
pin moves have landed since — `0d04db712` (2026-08-24), `26daaab7e`
|
|
761
|
-
(2026-08-25)
|
|
762
|
-
measured to change nothing: a four-arm byte A/B
|
|
763
|
-
new pins identical on the atmosphere half of
|
|
764
|
-
31 steps and on 0 of 138 history variables
|
|
765
|
-
(`evidence/seam-258-ab-20260828/`) — one mesh, one case, one hour. The
|
|
766
|
-
|
|
767
|
-
|
|
764
|
+
(2026-08-25), `659962929` (2026-08-28), `7e34a48` (2026-08-31, gpuwm
|
|
765
|
+
2.6.0) and `df5f34c5c` (2026-09-01, gpuwm 2.6.1). The **2.5.8** move is measured to change nothing: a four-arm byte A/B
|
|
766
|
+
on one card found the old and new pins identical on the atmosphere half of
|
|
767
|
+
the per-step fingerprint at all 31 steps and on 0 of 138 history variables
|
|
768
|
+
(`evidence/seam-258-ab-20260828/`) — one mesh, one case, one hour. The
|
|
769
|
+
**2.6.0** move also crosses the executed seam (`gpuwm/core/rrtmg_legacy.py`
|
|
770
|
+
among its three moved files) and is measured the same way at the same
|
|
771
|
+
scope: the x4 proof re-run at that pin wrote an F001 history byte-identical
|
|
772
|
+
to the 2.5.8 proof's (`evidence/repin-260-20260831/x4-proof/`). The
|
|
773
|
+
**2.6.1** move crosses it a third time, at its centre — the seam's own batch
|
|
774
|
+
driver `gpuwm/core/mpas_column_batch.py` gains restart schema v2 and the P3
|
|
775
|
+
eight-species transport — and is measured the same way at the same scope:
|
|
776
|
+
the x4 proof re-run at that pin wrote all four snapshots (F000, F030, F001
|
|
777
|
+
and the restarted F001) byte-identical to the 2.6.0 proof's, so one F001
|
|
778
|
+
SHA-256 now spans three engines (`evidence/repin-261-20260901/x4-proof/`).
|
|
779
|
+
The two earliest moves have no such arm, and none of the three magnitudes
|
|
780
|
+
has been re-measured over 24 h since. Whether any of them moved is **NOT MEASURED**.
|
|
768
781
|
Read them as the numbers from the pre-2026-08-20 engine, not as today's.
|
|
769
782
|
|
|
770
783
|
1. **Upper-level warm drift.** Above level 45 the port warms relative to native
|
|
@@ -821,7 +834,8 @@ case-independent, which chaos cannot be, and each names a lane to fix.
|
|
|
821
834
|
> `--cull-parent`, and `rw_mpas_lbc` was in no bundle and no published source
|
|
822
835
|
> (measured 2026-08-27, `evidence/userwalk-20260827/RECEIPT.md` — that receipt
|
|
823
836
|
> is a record of 2.5.7 and is not restated here as current fact). The engine
|
|
824
|
-
> then published 2.5.8, which this distribution
|
|
837
|
+
> then published 2.5.8, which this distribution required until it re-pinned
|
|
838
|
+
> onto 2.6.0 and then 2.6.1.
|
|
825
839
|
>
|
|
826
840
|
> Measured 2026-08-28 against the real published artefacts: `gpuwm
|
|
827
841
|
> fetch-bridges` on a 2.5.8 install downloads
|
|
@@ -56,11 +56,12 @@ is no receipt directory, no card and no run commit for them anywhere in the
|
|
|
56
56
|
tree -- which is the opposite of how the obs-referee numbers below are
|
|
57
57
|
recorded, and the gap is worth naming rather than papering over. What can be
|
|
58
58
|
established is a ceiling: the commit that introduced them pinned engine
|
|
59
|
-
`629ddb6f0`, so the run happened at or before that pin.
|
|
60
|
-
have landed since -- `0d04db712` (2026-08-24), `26daaab7e` (2026-08-25)
|
|
61
|
-
`659962929` (2026-08-28, gpuwm 2.5.8)
|
|
59
|
+
`629ddb6f0`, so the run happened at or before that pin. Five engine pin moves
|
|
60
|
+
have landed since -- `0d04db712` (2026-08-24), `26daaab7e` (2026-08-25),
|
|
61
|
+
`659962929` (2026-08-28, gpuwm 2.5.8), `7e34a48` (2026-08-31, gpuwm
|
|
62
|
+
2.6.0) and `df5f34c5c` (2026-09-01, gpuwm 2.6.1).
|
|
62
63
|
|
|
63
|
-
The
|
|
64
|
+
The 2.5.8 move crosses the executed seam and **has been measured**, in
|
|
64
65
|
the strongest form available short of a re-run: a four-arm byte A/B on one
|
|
65
66
|
RTX 5090, old pin against new pin, x4.163842, 30 composite steps, no tolerance
|
|
66
67
|
anywhere. The atmosphere half of the per-step fingerprint is identical at all
|
|
@@ -71,10 +72,27 @@ digest rolled up over them
|
|
|
71
72
|
That is one mesh, one case and one hour, and it is a byte comparison rather
|
|
72
73
|
than a physics claim.
|
|
73
74
|
|
|
74
|
-
The
|
|
75
|
-
|
|
76
|
-
|
|
77
|
-
|
|
75
|
+
The 2026-08-31 move crosses the executed seam too
|
|
76
|
+
(`gpuwm/core/rrtmg_legacy.py` is one of its three moved files, and legacy
|
|
77
|
+
RRTMG is the prime suspect for the drift below), and it carries its own
|
|
78
|
+
one-hour byte arm: the x4 frozen-source proof re-run at that pin wrote an
|
|
79
|
+
F001 history byte-identical to the 2.5.8 proof's -- one SHA-256, two
|
|
80
|
+
engines (receipt `evidence/repin-260-20260831/x4-proof/`). One mesh, one
|
|
81
|
+
case, one hour, same caveat as above.
|
|
82
|
+
|
|
83
|
+
The 2026-09-01 move crosses the executed seam a third time, and at its
|
|
84
|
+
centre: `gpuwm/core/mpas_column_batch.py`, the seam's own batch driver,
|
|
85
|
+
gains restart schema v2 and the P3 eight-species transport (the engine's
|
|
86
|
+
default WSM6 path declared byte-unchanged), with `gpuwm/config.py` and
|
|
87
|
+
`docs/mpas-seam.md` moving beside it. Its arm is the same one-hour byte
|
|
88
|
+
arm: the x4 proof re-run at that pin wrote all four snapshots -- F000,
|
|
89
|
+
F030, F001 and the restarted F001 -- byte-identical to the 2.6.0 proof's,
|
|
90
|
+
so one F001 SHA-256 now spans three engines (receipt
|
|
91
|
+
`evidence/repin-261-20260901/x4-proof/`). Same scope, same caveat. The
|
|
92
|
+
two EARLIEST pin moves have no arm at all, and no magnitude above has been
|
|
93
|
+
re-measured over 24 h since the original run. **Whether any of the three moved across those pins is
|
|
94
|
+
NOT MEASURED.** Read them as pre-2026-08-20 numbers until somebody re-runs
|
|
95
|
+
them.
|
|
78
96
|
|
|
79
97
|
---
|
|
80
98
|
|
|
@@ -33,23 +33,24 @@ individual gpuwm source files by SHA-256. A bare install reached an engine the
|
|
|
33
33
|
pin refused, and the forecast door refused at launch with a digest mismatch
|
|
34
34
|
that named neither the version that works nor the fact that pip chose it.
|
|
35
35
|
|
|
36
|
-
The declaration now carries a bounded range — `gpuwm>=2.
|
|
36
|
+
The declaration now carries a bounded range — `gpuwm>=2.6.1,<2.6.2` — so pip
|
|
37
37
|
resolves the engine that works and refuses the one that does not. Three things
|
|
38
38
|
follow that are worth knowing rather than discovering:
|
|
39
39
|
|
|
40
|
-
- **2.
|
|
41
|
-
against every published 2.5.x release. So there is no fallback:
|
|
42
|
-
one version wide because only one version qualifies.
|
|
40
|
+
- **2.6.1 is the only published engine that matches**, re-measured 2026-09-01
|
|
41
|
+
against every published 2.5.x and 2.6.x release. So there is no fallback:
|
|
42
|
+
the range is one version wide because only one version qualifies.
|
|
43
43
|
- **A newer gpuwm will not be resolved either.** The ceiling sits at the
|
|
44
44
|
first engine this port has not measured against the manifest, so a future
|
|
45
|
-
2.
|
|
45
|
+
2.6.2 is excluded exactly as 2.6.0 is. That is deliberate: an unmeasured
|
|
46
46
|
engine is what produced the defect.
|
|
47
47
|
- **If you already have a different gpuwm in the environment**, `gpuwm-hex
|
|
48
48
|
doctor` compares the installed engine's bytes against the pin and names
|
|
49
49
|
both the version it found and the version to install. It is a byte check,
|
|
50
50
|
not a version check, and it runs by default. On a conforming install it
|
|
51
|
-
reads `gpuwm 2.
|
|
52
|
-
match
|
|
51
|
+
reads `gpuwm 2.6.1: 16 of 16 pinned files are in this install and all 16
|
|
52
|
+
match` (measured 2026-09-01 against the published 2.6.1 wheel, in a fresh
|
|
53
|
+
virtualenv holding only the published wheels).
|
|
53
54
|
|
|
54
55
|
Then add the CUDA lane:
|
|
55
56
|
|
|
@@ -150,7 +151,7 @@ gpuwm you have: the transcript above was taken against the published gpuwm
|
|
|
150
151
|
2.5.2 wheel, whose bundle carries `rw_wrfbatch` and **not** `rw_mpas_init`
|
|
151
152
|
or `rw_mpas_convert` — which is exactly the shortfall the doctor reports
|
|
152
153
|
there. The four MPAS bridge binaries enter the bundle at gpuwm 2.5.3, and
|
|
153
|
-
this distribution's declared range is `gpuwm>=2.
|
|
154
|
+
this distribution's declared range is `gpuwm>=2.6.1,<2.6.2` (the floor is
|
|
154
155
|
far past 2.5.3, for the seam bytes the port pins): a conforming install cannot
|
|
155
156
|
land on the engine that transcript was taken from. Doctor
|
|
156
157
|
asks the gpuwm you actually have what its bundle declares, so it never sends
|
|
@@ -301,7 +302,7 @@ about a minute.
|
|
|
301
302
|
The forecast lane is the one step whose answer depends on your hardware, so
|
|
302
303
|
ask before you spend anything on it. **Both checkouts below are required and
|
|
303
304
|
neither is optional**: `--repo` is your gpuwm-hex checkout (the drivers are
|
|
304
|
-
not in the wheel) and `--gpuwm-checkout` is a gpuwm checkout at **`v2.
|
|
305
|
+
not in the wheel) and `--gpuwm-checkout` is a gpuwm checkout at **`v2.6.1`**,
|
|
305
306
|
the tag whose bytes the seam pin matches (2.1). Leave `--repo` off and the
|
|
306
307
|
door refuses before it reads anything else.
|
|
307
308
|
|
|
@@ -315,7 +316,7 @@ gpuwm-hex forecast --preflight \
|
|
|
315
316
|
--hours 1.0 --history-every-minutes 30 \
|
|
316
317
|
--out work/fc-01 \
|
|
317
318
|
--repo <gpuwm-hex-checkout>/tree \
|
|
318
|
-
--gpuwm-checkout <gpuwm-checkout-at-v2.
|
|
319
|
+
--gpuwm-checkout <gpuwm-checkout-at-v2.6.1>
|
|
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```
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`--gpuwm-checkout` must be a **git clone**, not an unpacked release tarball
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--hours 1.0 --history-every-minutes 30 \
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--out work/fc-01 \
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--repo <gpuwm-hex-checkout>/tree \
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-
--gpuwm-checkout <gpuwm-checkout-at-v2.
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+
--gpuwm-checkout <gpuwm-checkout-at-v2.6.1> \
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--case-label quickstart
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```
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matching static in the same run, with no native toolchain anywhere in the
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loop. (This door was not present on the published gpuwm 2.5.2 wheel; it
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arrives with the 2.5.3 bundle, well below the floor this distribution's
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declared `gpuwm>=2.
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declared `gpuwm>=2.6.1,<2.6.2` range requires. The commands below were proven from a `gpuwm` checkout.)
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**See what a card can hold:**
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gpuwm-hex mesh-plan --spec my-case.json --card rtx-5070-ti
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```
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#### Where that gradient is measured (changed 2026-08-29)
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The transition-band gate is arithmetic on one number, and until 2026-08-29
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the generator sampled that number on a lattice spread evenly over the whole
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globe. At the 50,000 points it used, those sit about 101 km apart, so a
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refinement transition narrower than that was stepped over entirely and the
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receipt reported the flat background the lattice happened to land on. On an
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eight-rung 51.2 km to 200 m ladder it printed 12.12 %/cell for a field that
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reads 37.04, and the build admitted a design its own gate exists to refuse.
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Nothing in the reading said so, because a maximum over points that missed the
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ramp looks exactly like a gentle ramp.
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The generator now probes where a spec says its regions are — a shell a few
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transition widths wide around each region boundary, resolved across the ramp
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rather than along it — and prints two more fields beside the number:
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`gradient_probe_points`, what the reading cost, and
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`gradient_probe_coverage`, which reads `complete` when every locus where the
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field varies was covered. `gpuwm-hex` refuses to judge a spec on a receipt
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that does not say `complete`, including a receipt from an older engine that
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does not say anything, because a number that is not a measurement is not
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something to gate on.
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+
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Two consequences worth stating plainly. Specs with ramps hundreds of
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kilometres wide — every swath the threat metrics emit, and the two examples
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above — do not move: the old lattice already resolved them, and their
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readings shift in the fourth decimal. Specs with sub-kilometre cores and
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short ramps do move, sharply, and some designs that used to build now refuse
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before anything is seeded. That is the gate working, not a new restriction:
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the band was always that narrow.
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And what still is not measured this way: `predicted_cells` and
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`region_attainment` on the same receipt are still integrals over the global
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lattice, with the resolution limit that implies. Only the gradient follows
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the regions.
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It prices the spec through the generator's own sizing integral, applies the
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transition-band gate here (so a spec the build would refuse is refused
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before the build, with the ramp widening that clears it quoted in the spec's
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checkout's HEAD, tree and dirty paths into every receipt so the executed seam
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source can be named — so clone the tag instead of copying the files.
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-
**`--gpuwm-checkout ... is gpuwm 2.5.
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pinned to gpuwm 2.
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+
**`--gpuwm-checkout ... is gpuwm 2.5.8, and this port's physics seam is
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+
pinned to gpuwm 2.6.1`** — the checkout is a real gpuwm tree at the wrong
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version. The refusal names both versions, lists which of the sixteen pinned
|
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files moved, and prints the two commands that close it: the bounded `pip
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install` and the `git clone --depth 1 --branch v<version>` for the checkout
|
|
@@ -147,12 +147,12 @@ by omission.
|
|
|
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- Distribution and command: `gpuwm-hex`. Import namespace: `hexcore`,
|
|
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renamed from `mpas_port` at 0.2.0 and settled there (README, *The import
|
|
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namespace*). There is no alias shim.
|
|
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|
-
- Engine range: `gpuwm>=2.
|
|
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|
+
- Engine range: `gpuwm>=2.6.1,<2.6.2` is what pip enforces — a bounded
|
|
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range, derived from a measured table in `hexcore.engine_pin` rather than
|
|
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typed. The floor is where it is for one reason and it is the strictest
|
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|
-
one: 2.
|
|
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|
-
Arwen seam manifest, re-measured 2026-
|
|
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|
-
release. It clears, incidentally, the bundle rows that put the MPAS bridge
|
|
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|
+
one: 2.6.1 is the only published engine whose bytes match the sixteen-file
|
|
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|
+
Arwen seam manifest, re-measured 2026-09-01 against every published 2.5.x
|
|
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|
+
and 2.6.x release. It clears, incidentally, the bundle rows that put the MPAS bridge
|
|
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|
binaries (`rw_mpas_init`, `rw_mpas_convert`, `rw_mpas_mesh`,
|
|
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|
`rw_mpas_static`, `rw_mpas_lbc`) within reach of `gpuwm fetch-bridges`;
|
|
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|
published 2.5.2 carries none of them and would strand every door that
|
|
@@ -162,7 +162,7 @@ by omission.
|
|
|
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|
forecast lane's real wall is stricter still: the sixteen-file seam
|
|
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|
manifest, plus a *git* checkout at the pinned commit for receipt
|
|
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|
provenance (chapter 6.1). `gpuwm-hex doctor` compares the installed
|
|
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|
-
engine's bytes against the manifest and names the version it found;
|
|
165
|
+
engine's bytes against the manifest and names the version it found; since
|
|
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166
|
2.5.8 all sixteen pinned paths resolve from the install, so the checkout
|
|
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|
is owed for the commit rather than for a file.
|
|
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168
|
- Licence: Apache-2.0, with the MPAS-Atmosphere BSD-3-Clause notice
|
|
@@ -43,14 +43,14 @@ independent port and is not affiliated with or endorsed by them.)*
|
|
|
43
43
|
|
|
44
44
|
**Every command was run before it was printed.** Each command block in this
|
|
45
45
|
manual was executed against the real artifact it documents — the installed
|
|
46
|
-
0.2.
|
|
46
|
+
0.2.1 wheel for the doors, the repository tools for the forecast lane, a CUDA
|
|
47
47
|
node for anything that needs a card — before it was written down. Where a
|
|
48
48
|
command's output is shown, it is the output that run produced, with machine
|
|
49
49
|
home directories shortened to `~`.
|
|
50
50
|
|
|
51
51
|
**What a walk of this manual actually reaches.** On 2026-08-27 the printed
|
|
52
52
|
commands were executed in printed order, from an empty environment, against
|
|
53
|
-
the built 0.2.
|
|
53
|
+
the built 0.2.1 wheel and the *published* engine, by somebody following the
|
|
54
54
|
page rather than remembering the code. Install, `doctor`, `mesh-check`, the
|
|
55
55
|
init door, the forecast door and the render door all reach real output —
|
|
56
56
|
16 min 46 s from an empty machine to the first rendered products. Three
|
|
@@ -60,7 +60,7 @@ re-measured 2026-08-28 against the published bundle: the **limited-area lane**
|
|
|
60
60
|
of chapter 6.8 and the `cull` door of chapter 9 have the engine capabilities
|
|
61
61
|
they need, and the render door's **default window** is understood by the
|
|
62
62
|
published converter. The third stands, with a narrower reason than it had: the forecast lane needs
|
|
63
|
-
a `gpuwm` **git** checkout at **v2.
|
|
63
|
+
a `gpuwm` **git** checkout at **v2.6.1**, not just whatever pip installs — not
|
|
64
64
|
because a pinned file is missing from the wheel (at 2.5.8 all sixteen resolve
|
|
65
65
|
from `site-packages`, measured 2026-08-28) but because the run records the
|
|
66
66
|
checkout's HEAD, tree and dirty paths into every receipt. Each is written
|
|
@@ -77,7 +77,7 @@ three measured, physics-shaped ways. They are stated in chapter 3, quantified
|
|
|
77
77
|
in [`docs/declared-divergences.md`](../declared-divergences.md), and never
|
|
78
78
|
hidden behind an option. Read them before trusting a number.
|
|
79
79
|
|
|
80
|
-
**Version.** This manual describes gpuwm-hex 0.2.
|
|
80
|
+
**Version.** This manual describes gpuwm-hex 0.2.2 with the gpuwm 2.6.x
|
|
81
81
|
engine line. Where a measurement was taken on specific hardware, the card is
|
|
82
82
|
named beside the number.
|
|
83
83
|
|