flashinfer-python 0.3.0__tar.gz → 0.3.1__tar.gz

{flashinfer_python-0.3.0/flashinfer_python.egg-info → flashinfer_python-0.3.1}/PKG-INFO

@@ -1,6 +1,6 @@
 Metadata-Version: 2.4
 Name: flashinfer-python
-Version: 0.3.0
+Version: 0.3.1
 Summary: FlashInfer: Kernel Library for LLM Serving
 Author: FlashInfer team
 License-Expression: Apache-2.0
@@ -18,6 +18,9 @@ Requires-Dist: ninja
 Requires-Dist: requests
 Requires-Dist: pynvml
 Requires-Dist: einops
+Requires-Dist: click
+Requires-Dist: tqdm
+Requires-Dist: tabulate
 Requires-Dist: packaging>=24.2
 Requires-Dist: nvidia-cudnn-frontend>=1.13.0
 Dynamic: license-file
@@ -93,7 +96,7 @@ To pre-compile essential kernels ahead-of-time (AOT), run the following command:
 
 ```bash
 # Set target CUDA architectures
-export TORCH_CUDA_ARCH_LIST="7.5 8.0 8.9 9.0a 10.0a"
+export FLASHINFER_CUDA_ARCH_LIST="7.5 8.0 8.9 9.0a 10.0a"
 # Build AOT kernels. Will produce AOT kernels in aot-ops/
 python -m flashinfer.aot
 # Build AOT wheel
@@ -149,6 +152,10 @@ Starting from FlashInfer v0.2, users can customize their own attention variants
 
 FlashInfer also provides C++ API and TVM bindings, please refer to [documentation](https://docs.flashinfer.ai/) for more details.
 
+## GPU Support
+
+FlashInfer currently provides support for NVIDIA SM architectures 80 and higher and beta support for 103, 110, 120, and 121.
+
 ## Adoption
 
 We are thrilled to share that FlashInfer is being adopted by many cutting-edge projects, including but not limited to:

{flashinfer_python-0.3.0 → flashinfer_python-0.3.1}/README.md

@@ -68,7 +68,7 @@ To pre-compile essential kernels ahead-of-time (AOT), run the following command:
 
 ```bash
 # Set target CUDA architectures
-export TORCH_CUDA_ARCH_LIST="7.5 8.0 8.9 9.0a 10.0a"
+export FLASHINFER_CUDA_ARCH_LIST="7.5 8.0 8.9 9.0a 10.0a"
 # Build AOT kernels. Will produce AOT kernels in aot-ops/
 python -m flashinfer.aot
 # Build AOT wheel
@@ -124,6 +124,10 @@ Starting from FlashInfer v0.2, users can customize their own attention variants
 
 FlashInfer also provides C++ API and TVM bindings, please refer to [documentation](https://docs.flashinfer.ai/) for more details.
 
+## GPU Support
+
+FlashInfer currently provides support for NVIDIA SM architectures 80 and higher and beta support for 103, 110, 120, and 121.
+
 ## Adoption
 
 We are thrilled to share that FlashInfer is being adopted by many cutting-edge projects, including but not limited to:

flashinfer_python-0.3.1/csrc/fp4_gemm_cutlass_sm120.cu

@@ -0,0 +1,191 @@
+/*
+ * Copyright (c) 2020-2023, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include <ATen/cuda/EmptyTensor.h>
+#include <cuda_fp16.h>
+
+#include <cstddef>
+#include <cstdint>
+#include <functional>
+#include <type_traits>
+#include <vector>
+
+#include "flashinfer/gemm/cutlass_gemm_configs.h"
+// Use SM120-specific dispatch template (includes fp4_gemm_cutlass.h)
+#include "flashinfer/gemm/fp4_gemm_cutlass_template_sm120.h"
+#include "pytorch_extension_utils.h"
+
+using flashinfer::gemm::ClusterShape;
+using flashinfer::gemm::CutlassFp4GemmRunner;
+using flashinfer::gemm::CutlassGemmConfig;
+using flashinfer::gemm::CutlassTileConfigSM120;
+using flashinfer::gemm::EpilogueScheduleType;
+using flashinfer::gemm::FP4GemmType;
+using flashinfer::gemm::MainloopScheduleType;
+
+namespace torch_ext {
+
+namespace {
+
+CutlassGemmConfig getFp4GemmConfig(int64_t m, int64_t n, int64_t k, int64_t tactic) {
+  auto getCutlassFp4GemmConfigs = []() {
+    CutlassFp4GemmRunner<__nv_bfloat16, FP4GemmType::W4A4_NVFP4_NVFP4> gemmRunner;
+    return gemmRunner.getConfigs();
+  };
+  static std::vector<CutlassGemmConfig> globalConfigs = getCutlassFp4GemmConfigs();
+  TORCH_CHECK(tactic >= 0 && tactic < globalConfigs.size(), "tactic must be between 0 and ",
+              globalConfigs.size());
+  return globalConfigs[tactic];
+}
+
+template <typename T>
+void runGemm(at::Tensor& out, at::Tensor const& mat1, at::Tensor const& mat2,
+             at::Tensor const& mat1Scale, at::Tensor const& mat2Scale,
+             at::Tensor const& globalScale, int64_t m, int64_t n, int64_t k, int64_t batch_count,
+             CutlassGemmConfig const& gemmConfig, at::Tensor workspace_buffer) {
+  CutlassFp4GemmRunner<T, FP4GemmType::W4A4_NVFP4_NVFP4> gemmRunner;
+
+  int64_t const required_workspace_size = gemmRunner.getWorkspaceSize(m, n, k, batch_count);
+  int64_t const provided_workspace_size =
+      workspace_buffer.numel() * workspace_buffer.element_size();
+
+  auto runKernel = [&](void* workspace) {
+    gemmRunner.gemm(out.data_ptr(), mat1.const_data_ptr(), mat2.const_data_ptr(),
+                    mat1Scale.const_data_ptr(), mat2Scale.const_data_ptr(),
+                    globalScale.data_ptr<float>(), m, n, k, batch_count, gemmConfig,
+                    reinterpret_cast<char*>(workspace), required_workspace_size,
+                    at::cuda::getCurrentCUDAStream(mat1.get_device()));
+  };
+
+  if (provided_workspace_size < required_workspace_size) {
+    at::Tensor new_workspace = at::detail::empty_cuda(
+        {required_workspace_size}, at::ScalarType::Char, mat1.device(), std::nullopt);
+
+    runKernel(new_workspace.data_ptr());
+  } else {
+    runKernel(workspace_buffer.data_ptr());
+  }
+}
+
+constexpr auto FLOAT4_E2M1X2 = at::ScalarType::Byte;  // uint8_t
+constexpr auto SF_DTYPE = at::ScalarType::Byte;       // uint8_t
+
+at::Tensor fp4_bmm_impl(at::Tensor const& mat1, at::Tensor const& mat2, at::Tensor const& mat1Scale,
+                        at::Tensor const& mat2Scale, at::Tensor const& globalScale, at::Tensor out,
+                        at::Tensor workspace_buffer, int64_t tactic) {
+  // Validate inputs
+  TORCH_CHECK(mat1.dtype() == FLOAT4_E2M1X2, "mat1 must be FLOAT4_E2M1X2 (uint8)");
+  TORCH_CHECK(mat2.dtype() == FLOAT4_E2M1X2, "mat2 must be FLOAT4_E2M1X2 (uint8)");
+  TORCH_CHECK(mat1Scale.dtype() == SF_DTYPE, "mat1Scale must be SF_DTYPE (uint8)");
+  TORCH_CHECK(mat2Scale.dtype() == SF_DTYPE, "mat2Scale must be SF_DTYPE (uint8)");
+  TORCH_CHECK(globalScale.dtype() == at::ScalarType::Float, "globalScale must be float");
+  TORCH_CHECK(mat1.is_cuda(), "mat1 must be on CUDA device");
+  TORCH_CHECK(mat2.is_cuda(), "mat2 must be on CUDA device");
+  TORCH_CHECK(mat1Scale.is_cuda(), "mat1Scale must be on CUDA device");
+  TORCH_CHECK(mat2Scale.is_cuda(), "mat2Scale must be on CUDA device");
+  TORCH_CHECK(globalScale.is_cuda(), "globalScale must be on CUDA device");
+  TORCH_CHECK(out.is_cuda(), "out must be on CUDA device");
+  TORCH_CHECK(workspace_buffer.is_cuda(), "workspace_buffer must be on CUDA device");
+
+  // Check device consistency
+  TORCH_CHECK(mat1.device() == mat2.device() && mat1.device() == mat1Scale.device() &&
+                  mat1.device() == mat2Scale.device() && mat1.device() == globalScale.device() &&
+                  mat1.device() == out.device() && mat1.device() == workspace_buffer.device(),
+              "All tensors must be on the same device");
+
+  // Get dimensions
+  int64_t b = 1;
+  int64_t m, k_packed, n;
+
+  if (mat1.dim() == 2) {
+    m = mat1.size(0);
+    k_packed = mat1.size(1);
+  } else if (mat1.dim() == 3) {
+    b = mat1.size(0);
+    m = mat1.size(1);
+    k_packed = mat1.size(2);
+  } else {
+    TORCH_CHECK(false, "mat1 must be 2D or 3D tensor");
+  }
+
+  if (mat2.dim() == 2) {
+    n = mat2.size(0);
+    TORCH_CHECK(mat2.size(1) == k_packed, "mat2.size(1) must match mat1.size(-1)");
+  } else if (mat2.dim() == 3) {
+    TORCH_CHECK(mat2.size(0) == b, "Batch dimensions must match");
+    n = mat2.size(1);
+    TORCH_CHECK(mat2.size(2) == k_packed, "mat2.size(2) must match mat1.size(-1)");
+  } else {
+    TORCH_CHECK(false, "mat2 must be 2D or 3D tensor");
+  }
+
+  // k_packed stores 2 FP4 values per byte
+  int64_t k = k_packed * 2;
+
+  TORCH_CHECK(globalScale.numel() == 1, "globalScale must be a scalar tensor");
+
+  // Configure the kernel
+  CutlassGemmConfig config =
+      (tactic >= 0) ? getFp4GemmConfig(m, n, k, tactic)
+                    : CutlassGemmConfig(CutlassTileConfigSM120::CtaShape128x128x128B,
+                                        MainloopScheduleType::AUTO, EpilogueScheduleType::AUTO,
+                                        ClusterShape::ClusterShape_1x1x1);
+
+  // Validate output dimensions
+  std::vector<int64_t> out_shape =
+      (b > 1) ? std::vector<int64_t>{b, m, n} : std::vector<int64_t>{m, n};
+  TORCH_CHECK(out.dim() == out_shape.size(), "out must have ", out_shape.size(), " dimensions");
+  for (size_t i = 0; i < out_shape.size(); ++i) {
+    TORCH_CHECK(out.sizes()[i] == out_shape[i], "out.size(", i, "): expected ", out_shape[i],
+                ", got ", out.sizes()[i]);
+  }
+
+  c10::ScalarType out_dtype = out.scalar_type();
+
+  switch (out_dtype) {
+    case at::ScalarType::Half:
+      runGemm<half>(out, mat1, mat2, mat1Scale, mat2Scale, globalScale, m, n, k, b, config,
+                    workspace_buffer);
+      break;
+    case at::ScalarType::BFloat16:
+      runGemm<__nv_bfloat16>(out, mat1, mat2, mat1Scale, mat2Scale, globalScale, m, n, k, b, config,
+                             workspace_buffer);
+      break;
+    default:
+      TORCH_CHECK(false, "out_dtype must be one of fp16/bf16.");
+  }
+  return out;
+}
+
+}  // namespace
+
+at::Tensor fp4_gemm(at::Tensor const& mat1, at::Tensor const& mat2, at::Tensor const& mat1Scale,
+                    at::Tensor const& mat2Scale, at::Tensor const& globalScale, at::Tensor out,
+                    at::Tensor workspace_buffer, int64_t tactic) {
+  return fp4_bmm_impl(mat1, mat2, mat1Scale, mat2Scale, globalScale, out, workspace_buffer, tactic);
+}
+
+int64_t fp4_gemm_tactic_num() {
+  static const int64_t totalTactics =
+      CutlassFp4GemmRunner<__nv_bfloat16, FP4GemmType::W4A4_NVFP4_NVFP4>{}.getConfigs().size();
+  return totalTactics;
+}
+
+}  // namespace torch_ext
+
+TORCH_LIBRARY_FRAGMENT(TORCH_EXTENSION_NAME, m) {
+  m.def("fp4_gemm", &torch_ext::fp4_gemm);
+  m.def("fp4_gemm_tactic_num", &torch_ext::fp4_gemm_tactic_num);
+}

flashinfer_python-0.3.1/csrc/fp4_gemm_cutlass_sm120.jinja

@@ -0,0 +1,26 @@
+/*
+ * Copyright (c) 2020-2023, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+// Use SM120-specific dispatch template
+#include "flashinfer/gemm/fp4_gemm_cutlass_template_sm120.h"
+
+namespace flashinfer {
+namespace gemm {
+// SM120/121 only supports 1x1x1 cluster shape
+INSTANTIATE_FP4_GEMM_KERNEL_LAUNCHER({{ type }}, {{ cta_m }}, {{ cta_n }}, {{ cta_k }}, 1, 1, 1, _1SM)
+
+}  // namespace gemm
+}  // namespace flashinfer

flashinfer_python-0.3.1/csrc/gemm_groupwise_sm120.cu

@@ -0,0 +1,138 @@
+/*
+ * Copyright (c) 2025 by FlashInfer team.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include <flashinfer/cutlass_utils.cuh>
+
+#include "pytorch_extension_utils.h"
+
+using namespace flashinfer;
+
+#define DISPATCH_PYTORCH_INPUT_OUTPUT_DTYPE(input_dtype, output_dtype, c_type_in, c_type_out, ...) \
+  [&]() -> bool {                                                                                  \
+    return DISPATCH_PYTORCH_DTYPE_TO_CTYPE_FP16(output_dtype, c_type_out, [&] {                    \
+      return DISPATCH_PYTORCH_DTYPE_TO_CTYPE_FP8(input_dtype, c_type_in,                           \
+                                                 [&] { return __VA_ARGS__(); });                   \
+    });                                                                                            \
+  }()
+
+#define DISPATCH_SCALE_GRANULARITY(scale_granularity_m, scale_granularity_n, scale_granularity_k,  \
+                                   SCALE_GRANULARITY_M, SCALE_GRANULARITY_N, SCALE_GRANULARITY_K,  \
+                                   ...)                                                            \
+  [&]() -> bool {                                                                                  \
+    /* SM120 Cooperative schedule uses 128x128x128 tile shape */                                   \
+    /* TODO (yongwww): PingPong schedule (64x128x128) will need additional dispatch logic */       \
+    constexpr int SCALE_GRANULARITY_K = 128;                                                       \
+    if (scale_granularity_k != 128) {                                                              \
+      TORCH_CHECK(                                                                                 \
+          false,                                                                                   \
+          "SM120 requires scale_granularity_k=128. CUTLASS enforces ScaleGranularityK must equal " \
+          "tile shape K dimension (128 for both Cooperative and PingPong schedules).");            \
+      return false;                                                                                \
+    }                                                                                              \
+    /* Support (1,128,128) and (128,128,128) as per SM100's approach */                            \
+    if (scale_granularity_m == 1 && scale_granularity_n == 128) {                                  \
+      constexpr int SCALE_GRANULARITY_M = 1;                                                       \
+      constexpr int SCALE_GRANULARITY_N = 128;                                                     \
+      return __VA_ARGS__();                                                                        \
+    } else if (scale_granularity_m == 128 && scale_granularity_n == 128) {                         \
+      constexpr int SCALE_GRANULARITY_M = 128;                                                     \
+      constexpr int SCALE_GRANULARITY_N = 128;                                                     \
+      return __VA_ARGS__();                                                                        \
+    }                                                                                              \
+    TORCH_CHECK(false, "SM120: Unsupported scale granularity combination (", scale_granularity_m,  \
+                ",", scale_granularity_n, ",", scale_granularity_k, ")");                          \
+    return false;                                                                                  \
+  }()
+
+#define DISPATCH_SCALE_MAJOR_K(scale_major_mode, SCALE_MAJOR_K, ...) \
+  [&]() -> bool {                                                    \
+    if (scale_major_mode == "K") {                                   \
+      constexpr bool SCALE_MAJOR_K = true;                           \
+      return __VA_ARGS__();                                          \
+    } else if (scale_major_mode == "MN") {                           \
+      constexpr bool SCALE_MAJOR_K = false;                          \
+      return __VA_ARGS__();                                          \
+    }                                                                \
+    TORCH_CHECK(false, "Unsupported Scale Major Mode");              \
+    return false;                                                    \
+  }()
+
+namespace flashinfer {
+namespace gemm {
+
+template <int ScaleGranularityM, int ScaleGranularityN, int ScaleGranularityK, bool ScaleMajorK,
+          typename DTypeIn, typename DTypeOut>
+cudaError_t CutlassGroupwiseScaledGEMMSM120(void* float_buffer, size_t float_buffer_size_in_bytes,
+                                            DTypeIn* A_ptr, DTypeIn* B_ptr, float* SFA_ptr,
+                                            float* SFB_ptr, DTypeOut* C_ptr, int m, int n, int k,
+                                            int l, cudaStream_t stream);
+
+}  // namespace gemm
+}  // namespace flashinfer
+
+void CutlassGemmGroupwiseScaledSM120(at::Tensor float_workspace_buffer, at::Tensor A, at::Tensor B,
+                                     at::Tensor SFA, at::Tensor SFB, at::Tensor C,
+                                     int64_t scale_granularity_m, int64_t scale_granularity_n,
+                                     int64_t scale_granularity_k, std::string scale_major_mode) {
+  const c10::cuda::OptionalCUDAGuard device_guard(float_workspace_buffer.device());
+  auto stream = at::cuda::getCurrentCUDAStream();
+
+  // Ensure scales are contiguous
+  // Note: We keep the original shape and let the kernel's layout handle interpretation
+  at::Tensor SFA_contig = SFA.is_contiguous() ? SFA : SFA.contiguous();
+  at::Tensor SFB_contig = SFB.is_contiguous() ? SFB : SFB.contiguous();
+
+  DISPATCH_SCALE_MAJOR_K(scale_major_mode, SCALE_MAJOR_K, [&] {
+    return DISPATCH_PYTORCH_INPUT_OUTPUT_DTYPE(
+        A.scalar_type(), C.scalar_type(), c_type_in, c_type_out, [&] {
+          return DISPATCH_SCALE_GRANULARITY(
+              scale_granularity_m, scale_granularity_n, scale_granularity_k, SCALE_GRANULARITY_M,
+              SCALE_GRANULARITY_N, SCALE_GRANULARITY_K, [&] {
+                using cutlass_t_in = cutlass_dtype_t<c_type_in>;
+                using cutlass_t_out = cutlass_dtype_t<c_type_out>;
+
+                // Handle both 2D and 3D tensors (BMM)
+                int m, n, k, l;
+                if (A.dim() == 2) {
+                  // 2D case: simple matrix multiplication
+                  m = A.size(0);
+                  k = A.size(1);
+                  n = B.size(0);
+                  l = 1;  // no batch dimension
+                } else if (A.dim() == 3) {
+                  // 3D case: batch matrix multiplication
+                  l = A.size(0);  // batch size
+                  m = A.size(1);  // per-batch m dimension
+                  k = A.size(2);  // per-batch k dimension
+                  n = B.size(2);  // per-batch n dimension (B is [batch, k, n] column-major)
+                } else {
+                  return false;  // Unsupported tensor dimension
+                }
+
+                auto status = flashinfer::gemm::CutlassGroupwiseScaledGEMMSM120<
+                    SCALE_GRANULARITY_M, SCALE_GRANULARITY_N, SCALE_GRANULARITY_K, SCALE_MAJOR_K>(
+                    static_cast<void*>(float_workspace_buffer.data_ptr()),
+                    float_workspace_buffer.element_size() * float_workspace_buffer.numel(),
+                    static_cast<cutlass_t_in*>(A.data_ptr()),
+                    static_cast<cutlass_t_in*>(B.data_ptr()),
+                    static_cast<float*>(SFA_contig.data_ptr()),
+                    static_cast<float*>(SFB_contig.data_ptr()),
+                    static_cast<cutlass_t_out*>(C.data_ptr()), m, n, k, l,
+                    stream);  // C is the output (D)
+                return status == cudaSuccess;
+              });
+        });
+  });
+}

flashinfer_python-0.3.1/csrc/gemm_groupwise_sm120_kernel_inst.jinja

@@ -0,0 +1,42 @@
+/*
+ * Copyright (c) 2025 by FlashInfer team.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include <flashinfer/gemm/gemm_groupwise_sm120.cuh>
+
+using namespace flashinfer;
+using namespace flashinfer::gemm;
+
+namespace flashinfer {
+namespace gemm {
+
+// Following SM100's approach: support (1,128,128) and (128,128,128)
+{% for scale_granularity_m in [1, 128] %}
+{% for scale_granularity_n in [128] %}
+{% for scale_granularity_k in [128] %}
+template cudaError_t
+CutlassGroupwiseScaledGEMMSM120<
+    {{ scale_granularity_m }}, {{ scale_granularity_n }}, {{ scale_granularity_k }},
+    {{ scale_major_k }},
+    {{ dtype_in }},
+    {{ dtype_out }}>(
+        void* float_buffer, size_t float_buffer_size_in_bytes,
+        {{ dtype_in }}* A_ptr, {{ dtype_in }}* B_ptr, float* SFA_ptr, float* SFB_ptr,
+        {{ dtype_out }}* D_ptr, int m, int n, int k, int l, cudaStream_t stream);
+{% endfor %}
+{% endfor %}
+{% endfor %}
+
+};  // namespace gemm
+};  // namespace flashinfer

flashinfer_python-0.3.1/csrc/gemm_sm120_pybind.cu

@@ -0,0 +1,25 @@
+/*
+ * Copyright (c) 2025 by FlashInfer team.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "pytorch_extension_utils.h"
+
+void CutlassGemmGroupwiseScaledSM120(at::Tensor float_workspace_buffer, at::Tensor A, at::Tensor B,
+                                     at::Tensor SFA, at::Tensor SFB, at::Tensor C,
+                                     int64_t scale_granularity_m, int64_t scale_granularity_n,
+                                     int64_t scale_granularity_k, std::string scale_major_mode);
+
+TORCH_LIBRARY_FRAGMENT(TORCH_EXTENSION_NAME, m) {
+  m.def("gemm_fp8_nt_groupwise", CutlassGemmGroupwiseScaledSM120);
+}

flashinfer_python-0.3.1/csrc/group_gemm_fp8_groupwise_sm120.cu

@@ -0,0 +1,123 @@
+/*
+ * Copyright (c) 2025 by FlashInfer team.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include <flashinfer/cutlass_utils.cuh>
+
+#include "pytorch_extension_utils.h"
+
+using namespace flashinfer;
+
+#define DISPATCH_PYTORCH_INPUT_OUTPUT_DTYPE(input_dtype, output_dtype, c_type_in, c_type_out, ...) \
+  [&]() -> bool {                                                                                  \
+    return DISPATCH_PYTORCH_DTYPE_TO_CTYPE_FP16(output_dtype, c_type_out, [&] {                    \
+      return DISPATCH_PYTORCH_DTYPE_TO_CTYPE_FP8(input_dtype, c_type_in,                           \
+                                                 [&] { return __VA_ARGS__(); });                   \
+    });                                                                                            \
+  }()
+
+#define DISPATCH_SCALE_GRANULARITY(scale_granularity_m, scale_granularity_n, scale_granularity_k,  \
+                                   SCALE_GRANULARITY_M, SCALE_GRANULARITY_N, SCALE_GRANULARITY_K,  \
+                                   ...)                                                            \
+  [&]() -> bool {                                                                                  \
+    constexpr int SCALE_GRANULARITY_K = 128;                                                       \
+    if (scale_granularity_k != 128) {                                                              \
+      TORCH_CHECK(                                                                                 \
+          false,                                                                                   \
+          "SM120 requires scale_granularity_k=128. CUTLASS enforces ScaleGranularityK must equal " \
+          "tile shape K dimension (128 for both Cooperative and PingPong schedules).");            \
+      return false;                                                                                \
+    }                                                                                              \
+    /* Match SM100's approach: support only (1,128,128) and (128,128,128) */                       \
+    if (scale_granularity_m == 1 && scale_granularity_n == 128) {                                  \
+      constexpr int SCALE_GRANULARITY_M = 1;                                                       \
+      constexpr int SCALE_GRANULARITY_N = 128;                                                     \
+      return __VA_ARGS__();                                                                        \
+    } else if (scale_granularity_m == 128 && scale_granularity_n == 128) {                         \
+      constexpr int SCALE_GRANULARITY_M = 128;                                                     \
+      constexpr int SCALE_GRANULARITY_N = 128;                                                     \
+      return __VA_ARGS__();                                                                        \
+    }                                                                                              \
+    TORCH_CHECK(false, "SM120: Unsupported scale granularity combination (", scale_granularity_m,  \
+                ",", scale_granularity_n, ",", scale_granularity_k, ")");                          \
+    return false;                                                                                  \
+  }()
+
+#define DISPATCH_SCALE_MAJOR_K(scale_major_mode, SCALE_MAJOR_K, ...) \
+  [&]() -> bool {                                                    \
+    if (scale_major_mode == "K") {                                   \
+      constexpr bool SCALE_MAJOR_K = true;                           \
+      return __VA_ARGS__();                                          \
+    } else if (scale_major_mode == "MN") {                           \
+      constexpr bool SCALE_MAJOR_K = false;                          \
+      return __VA_ARGS__();                                          \
+    }                                                                \
+    TORCH_CHECK(false, "Unsupported Scale Major Mode");              \
+    return false;                                                    \
+  }()
+
+namespace flashinfer {
+namespace group_gemm {
+
+template <int ScaleGranularityM, int ScaleGranularityN, int ScaleGranularityK, bool ScaleMajorK,
+          typename DTypeIn, typename DTypeOut>
+cudaError_t CutlassFP8GroupwiseScaledGroupGEMMSM120(
+    void* int_buffer, size_t int_buffer_size_in_bytes, void* float_buffer,
+    size_t float_buffer_size_in_bytes, DTypeIn* A, DTypeIn* B, float* SFA, float* SFB, DTypeOut* D,
+    int* m_indptr, int max_m, int n, int k, int num_groups, cudaStream_t stream);
+
+}  // namespace group_gemm
+}  // namespace flashinfer
+
+void CutlassGroupGemmFP8GroupwiseScaledSM120(
+    at::Tensor int_workspace_buffer, at::Tensor float_workspace_buffer, at::Tensor A, at::Tensor B,
+    at::Tensor SFA, at::Tensor SFB, at::Tensor D, at::Tensor m_indptr, int64_t n, int64_t k,
+    int64_t scale_granularity_m, int64_t scale_granularity_n, int64_t scale_granularity_k,
+    std::string scale_major_mode) {
+  const c10::cuda::OptionalCUDAGuard device_guard(float_workspace_buffer.device());
+  auto stream = at::cuda::getCurrentCUDAStream();
+  int num_groups = m_indptr.size(0) - 1;
+
+  // Ensure scales are contiguous
+  // Note: We keep the original shape and let the kernel's layout handle interpretation
+  at::Tensor SFA_contig = SFA.is_contiguous() ? SFA : SFA.contiguous();
+  at::Tensor SFB_contig = SFB.is_contiguous() ? SFB : SFB.contiguous();
+
+  // Get max_m from SFA shape
+  int max_m = SFA.size(SFA.dim() > 1 ? 1 : 0);
+
+  DISPATCH_PYTORCH_INPUT_OUTPUT_DTYPE(A.scalar_type(), D.scalar_type(), c_type_in, c_type_out, [&] {
+    return DISPATCH_SCALE_MAJOR_K(scale_major_mode, SCALE_MAJOR_K, [&] {
+      return DISPATCH_SCALE_GRANULARITY(
+          scale_granularity_m, scale_granularity_n, scale_granularity_k, SCALE_GRANULARITY_M,
+          SCALE_GRANULARITY_N, SCALE_GRANULARITY_K, [&] {
+            using cutlass_t_in = cutlass_dtype_t<c_type_in>;
+            using cutlass_t_out = cutlass_dtype_t<c_type_out>;
+            auto status = flashinfer::group_gemm::CutlassFP8GroupwiseScaledGroupGEMMSM120<
+                SCALE_GRANULARITY_M, SCALE_GRANULARITY_N, SCALE_GRANULARITY_K, SCALE_MAJOR_K,
+                cutlass_t_in, cutlass_t_out>(
+                static_cast<int*>(int_workspace_buffer.data_ptr()),
+                int_workspace_buffer.element_size() * int_workspace_buffer.size(0),
+                static_cast<float*>(float_workspace_buffer.data_ptr()),
+                float_workspace_buffer.element_size() * float_workspace_buffer.size(0),
+                static_cast<cutlass_t_in*>(A.data_ptr()), static_cast<cutlass_t_in*>(B.data_ptr()),
+                static_cast<float*>(SFA_contig.data_ptr()),
+                static_cast<float*>(SFB_contig.data_ptr()),
+                static_cast<cutlass_t_out*>(D.data_ptr()), static_cast<int*>(m_indptr.data_ptr()),
+                max_m, n, k, num_groups, stream);
+            return status == cudaSuccess;
+          });
+    });
+  });
+}

flashinfer_python-0.3.1/csrc/group_gemm_fp8_groupwise_sm120_kernel_inst.jinja

@@ -0,0 +1,43 @@
+/*
+ * Copyright (c) 2025 by FlashInfer team.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include <flashinfer/gemm/group_gemm_fp8_groupwise_sm120.cuh>
+
+using namespace flashinfer;
+using namespace flashinfer::group_gemm;
+
+namespace flashinfer {
+namespace group_gemm {
+
+// SM120 uses Cooperative schedule with fixed 128x128x128 tiles
+{% for scale_granularity_m in [1, 128] %}
+{% for scale_granularity_n in [128] %}
+{% for scale_granularity_k in [128] %}
+template cudaError_t
+CutlassFP8GroupwiseScaledGroupGEMMSM120<
+    {{ scale_granularity_m }}, {{ scale_granularity_n }}, {{ scale_granularity_k }},
+    {{ scale_major_k }},
+    {{ dtype_in }},
+    {{ dtype_out }}>(
+        void* int_buffer, size_t int_buffer_size_in_bytes,
+        void* float_buffer, size_t float_buffer_size_in_bytes,
+        {{ dtype_in }}* A, {{ dtype_in }}* B, float* SFA, float* SFB, {{ dtype_out }}* D,
+        int* m_indptr, int max_m, int n, int k, int num_groups, cudaStream_t stream);
+{% endfor %}
+{% endfor %}
+{% endfor %}
+
+};  // namespace group_gemm
+};  // namespace flashinfer

{flashinfer_python-0.3.0 → flashinfer_python-0.3.1}/csrc/group_gemm_mxfp4_groupwise_sm100.cu

@@ -134,7 +134,7 @@ void CutlassGroupGemmMXFP4GroupwiseScaledSM100(at::Tensor int_workspace_buffer,
                                                int64_t k, int64_t mma_sm, int64_t tile_m,
                                                int64_t tile_n, int64_t tile_k, bool swap_ab) {
   const c10::cuda::OptionalCUDAGuard device_guard(float_workspace_buffer.device());
-  auto stream = at::cuda::getCurrentCUDAStream();
+  auto stream = at::cuda::getCurrentCUDAStream(A.device().index());
   int num_groups = m_indptr.size(0) - 1;
   DISPATCH_PYTORCH_INPUT_OUTPUT_DTYPE(
       A.scalar_type(), B.scalar_type(), SFA.scalar_type(), SFB.scalar_type(), D.scalar_type(),