PyPI - esptool - Versions diffs - 5.3.dev1__tar.gz → 5.3.dev2__tar.gz - Mend

esptool 5.3.dev1tar.gz → 5.3.dev2tar.gz

This diff represents the content of publicly available package versions that have been released to one of the supported registries. The information contained in this diff is provided for informational purposes only and reflects changes between package versions as they appear in their respective public registries.

Files changed (176) hide show

{esptool-5.3.dev1/esptool.egg-info → esptool-5.3.dev2}/PKG-INFO RENAMED Viewed

@@ -1,6 +1,6 @@
 Metadata-Version: 2.4
 Name: esptool
-Version: 5.3.dev1
+Version: 5.3.dev2
 Summary: A serial utility for flashing, provisioning, and interacting with Espressif SoCs.
 Author: Fredrik Ahlberg (themadinventor), Angus Gratton (projectgus), Espressif Systems
 License: GPLv2+

{esptool-5.3.dev1 → esptool-5.3.dev2}/espefuse/efuse/esp32h4/fields.py RENAMED Viewed

@@ -212,8 +212,6 @@ class EspEfuses(base_fields.EspEfusesBase):
                 f"The eFuse supports only xtal=32M (xtal was {apb_freq}"
             )
-        # TODO: [ESP32H4] IDF-12268
     def get_coding_scheme_warnings(self, silent=False):
         """Check if the coding scheme has detected any errors."""
         old_addr_reg = 0
@@ -281,9 +279,7 @@ class EfuseMacField(base_fields.EfuseMacFieldBase, EfuseField):
 class EfuseWafer(base_fields.EfuseWaferBase, EfuseField):
-    def get(self, from_read=True):
-        # TODO: [ESP32H4] IDF-12268
-        return 0
+    pass
 class EfuseKeyPurposeField(base_fields.EfuseKeyPurposeFieldBase, EfuseField):
@@ -293,6 +289,8 @@ class EfuseKeyPurposeField(base_fields.EfuseKeyPurposeFieldBase, EfuseField):
         ("USER",                         0,  None,       None,      "no_need_rd_protect"),   # User purposes (software-only use)
         ("ECDSA_KEY_P256",               1,  None,       "Reverse", "need_rd_protect"),      # ECDSA key P256 (NIST P-256)
         ("ECDSA_KEY",                    1,  None,       "Reverse", "need_rd_protect"),      # ECDSA key (alias for P256)
+        ("XTS_AES_256_KEY_1",            2,  None,       "Reverse", "need_rd_protect"),      # Flash encryption key (XTS-AES-256 low/first half)
+        ("XTS_AES_256_KEY_2",            3,  None,       "Reverse", "need_rd_protect"),      # Flash encryption key (XTS-AES-256 high/second half)
         ("XTS_AES_128_KEY",              4,  None,       "Reverse", "need_rd_protect"),      # XTS_AES_128_KEY (flash/PSRAM encryption)
         ("HMAC_DOWN_ALL",                5,  None,       None,      "need_rd_protect"),      # HMAC Downstream mode
         ("HMAC_DOWN_JTAG",               6,  None,       None,      "need_rd_protect"),      # JTAG soft enable key (uses HMAC Downstream mode)
@@ -302,9 +300,14 @@ class EfuseKeyPurposeField(base_fields.EfuseKeyPurposeFieldBase, EfuseField):
         ("SECURE_BOOT_DIGEST1",          10, "DIGEST",   None,      "no_need_rd_protect"),   # SECURE_BOOT_DIGEST1 (Secure Boot key digest)
         ("SECURE_BOOT_DIGEST2",          11, "DIGEST",   None,      "no_need_rd_protect"),   # SECURE_BOOT_DIGEST2 (Secure Boot key digest)
         ("KM_INIT_KEY",                  12, None,       None,      "need_rd_protect"),      # init key that is used for the generation of AES/ECDSA key
+        ("XTS_AES_256_PSRAM_KEY_1",      13, None,       "Reverse", "need_rd_protect"),      # PSRAM encryption key (XTS-AES-256 low/first half)
+        ("XTS_AES_256_PSRAM_KEY_2",      14, None,       "Reverse", "need_rd_protect"),      # PSRAM encryption key (XTS-AES-256 high/second half)
+        ("XTS_AES_128_PSRAM_KEY",        15, None,       "Reverse", "need_rd_protect"),      # PSRAM encryption key (XTS-AES-128)
         ("ECDSA_KEY_P192",               16, None,       "Reverse", "need_rd_protect"),      # ECDSA key P192 (NIST P-192)
         ("ECDSA_KEY_P384_L",             17, None,       "Reverse", "need_rd_protect"),      # ECDSA key P384 low half
         ("ECDSA_KEY_P384_H",             18, None,       "Reverse", "need_rd_protect"),      # ECDSA key P384 high half
+        ("XTS_AES_256_KEY",              -1, "VIRTUAL",  None,      "no_need_rd_protect"),   # Virtual purpose splits to XTS_AES_256_KEY_1 and XTS_AES_256_KEY_2
+        ("XTS_AES_256_PSRAM_KEY",        -2, "VIRTUAL",  None,      "no_need_rd_protect"),   # Virtual purpose splits to XTS_AES_256_PSRAM_KEY_1 and XTS_AES_256_PSRAM_KEY_2
         ("ECDSA_KEY_P384",               -3, "VIRTUAL",  None,      "need_rd_protect"),      # Virtual: one key file -> ECDSA_KEY_P384_L + ECDSA_KEY_P384_H
     ]
     # fmt: on

{esptool-5.3.dev1 → esptool-5.3.dev2}/espefuse/efuse_defs/esp32h4.yaml RENAMED Viewed

@@ -1,9 +1,9 @@
-VER_NO: 7bc342bad0952907e1db21112d258c6b
+VER_NO: 6c3ca4b9e6c9ee71a1a0627fa77a905a
 EFUSES:
   WR_DIS                           : {show: y, blk : 0, word: 0, pos : 0, len : 32, start  : 0, type : 'uint:32', wr_dis: null, rd_dis: null, alt                            : '', dict             : '', desc: Disable programming of individual eFuses, rloc: EFUSE_RD_WR_DIS0_REG, bloc: 'B0,B1,B2,B3'}
   RD_DIS                           : {show: y, blk : 0, word: 1, pos : 0, len  : 7, start : 32, type  : 'uint:7', wr_dis   : 0, rd_dis: null, alt                            : '', dict             : '', desc: Disable reading from BlOCK4-10, rloc: 'EFUSE_RD_REPEAT_DATA0_REG[6:0]', bloc: 'B4[6:0]'}
   DIS_USB_JTAG                     : {show: y, blk : 0, word: 1, pos : 7, len  : 1, start : 39, type      : bool, wr_dis   : 2, rd_dis: null, alt                            : '', dict             : '', desc: 'Represents whether the function of usb switch to jtag is disabled or enabled. 1: disabled 0: enabled', rloc: 'EFUSE_RD_REPEAT_DATA0_REG[7]', bloc: 'B4[7]'}
-  RESERVE_0_40                     : {show: n, blk : 0, word: 1, pos : 8, len  : 1, start : 40, type      : bool, wr_dis: null, rd_dis: null, alt                            : '', dict             : '', desc: Reserved; it was created by set_missed_fields_in_regs func, rloc: 'EFUSE_RD_REPEAT_DATA0_REG[8]', bloc: 'B5[0]'}
+  DIS_USB_SERIAL_JTAG              : {show: n, blk : 0, word: 1, pos : 8, len  : 1, start : 40, type      : bool, wr_dis   : 2, rd_dis: null, alt                            : '', dict             : '', desc: 'Represents whether USB-Serial-JTAG is disabled or enabled. 1: disabled 0: enabled', rloc: 'EFUSE_RD_REPEAT_DATA0_REG[8]', bloc: 'B5[0]'}
   DIS_FORCE_DOWNLOAD               : {show: y, blk : 0, word: 1, pos : 9, len  : 1, start : 41, type      : bool, wr_dis   : 2, rd_dis: null, alt                            : '', dict             : '', desc: 'Represents whether the function that forces chip into download mode is disabled or enabled. 1: disabled 0: enabled', rloc: 'EFUSE_RD_REPEAT_DATA0_REG[9]', bloc: 'B5[1]'}
   SPI_DOWNLOAD_MSPI_DIS            : {show: y, blk : 0, word: 1, pos: 10, len  : 1, start : 42, type      : bool, wr_dis   : 2, rd_dis: null, alt                            : '', dict             : '', desc: 'Represents whether SPI0 controller during boot_mode_download is disabled or enabled. 1: disabled 0: enabled', rloc: 'EFUSE_RD_REPEAT_DATA0_REG[10]', bloc: 'B5[2]'}
   DIS_TWAI                         : {show: y, blk : 0, word: 1, pos: 11, len  : 1, start : 43, type      : bool, wr_dis   : 2, rd_dis: null, alt                            : '', dict             : '', desc: 'Represents whether TWAI function is disabled or enabled. 1: disabled 0: enabled', rloc: 'EFUSE_RD_REPEAT_DATA0_REG[11]', bloc: 'B5[3]'}
@@ -11,9 +11,9 @@ EFUSES:
   DIS_PAD_JTAG                     : {show: y, blk : 0, word: 1, pos: 13, len  : 1, start : 45, type      : bool, wr_dis   : 2, rd_dis: null, alt                            : '', dict             : '', desc: 'Represents whether JTAG is disabled in the hard way(permanently). 1: disabled 0: enabled', rloc: 'EFUSE_RD_REPEAT_DATA0_REG[13]', bloc: 'B5[5]'}
   DIS_DOWNLOAD_MANUAL_ENCRYPT      : {show: y, blk : 0, word: 1, pos: 14, len  : 1, start : 46, type      : bool, wr_dis   : 2, rd_dis: null, alt                            : '', dict             : '', desc: 'Represents whether flash encrypt function is disabled or enabled(except in SPI boot mode). 1: disabled 0: enabled', rloc: 'EFUSE_RD_REPEAT_DATA0_REG[14]', bloc: 'B5[6]'}
   RESERVE_0_47                     : {show: n, blk : 0, word: 1, pos: 15, len  : 3, start : 47, type  : 'uint:3', wr_dis: null, rd_dis: null, alt                            : '', dict             : '', desc: Reserved; it was created by set_missed_fields_in_regs func, rloc: 'EFUSE_RD_REPEAT_DATA0_REG[17:15]', bloc: 'B5[7],B6[1:0]'}
-  PVT_GLITCH_EN                    : {show: y, blk : 0, word: 1, pos: 18, len  : 1, start : 50, type      : bool, wr_dis: null, rd_dis: null, alt                            : '', dict             : '', desc: 'Represents whether to enable PVT power glitch monitor function.1:Enable. 0:Disable', rloc: 'EFUSE_RD_REPEAT_DATA0_REG[18]', bloc: 'B6[2]'}
+  PVT_GLITCH_EN                    : {show: y, blk : 0, word: 1, pos: 18, len  : 1, start : 50, type      : bool, wr_dis   : 2, rd_dis: null, alt                            : '', dict             : '', desc: 'Represents whether to enable PVT power glitch monitor function.1:Enable. 0:Disable', rloc: 'EFUSE_RD_REPEAT_DATA0_REG[18]', bloc: 'B6[2]'}
   RESERVE_0_51                     : {show: n, blk : 0, word: 1, pos: 19, len  : 1, start : 51, type      : bool, wr_dis: null, rd_dis: null, alt                            : '', dict             : '', desc: Reserved; it was created by set_missed_fields_in_regs func, rloc: 'EFUSE_RD_REPEAT_DATA0_REG[19]', bloc: 'B6[3]'}
-  PVT_GLITCH_MODE                  : {show: y, blk : 0, word: 1, pos: 20, len  : 2, start : 52, type  : 'uint:2', wr_dis: null, rd_dis: null, alt                            : '', dict             : '', desc: Use to configure glitch mode, rloc: 'EFUSE_RD_REPEAT_DATA0_REG[21:20]', bloc: 'B6[5:4]'}
+  PVT_GLITCH_MODE                  : {show: y, blk : 0, word: 1, pos: 20, len  : 2, start : 52, type  : 'uint:2', wr_dis   : 2, rd_dis: null, alt                            : '', dict             : '', desc: Use to configure glitch mode, rloc: 'EFUSE_RD_REPEAT_DATA0_REG[21:20]', bloc: 'B6[5:4]'}
   DIS_CORE1                        : {show: y, blk : 0, word: 1, pos: 22, len  : 1, start : 54, type      : bool, wr_dis: null, rd_dis: null, alt                            : '', dict             : '', desc: 'Represents whether the CPU-Core1 is disabled.  1: Disabled.  0: Not disable', rloc: 'EFUSE_RD_REPEAT_DATA0_REG[22]', bloc: 'B6[6]'}
   SPI_BOOT_CRYPT_CNT               : {show: y, blk : 0, word: 1, pos: 23, len  : 3, start : 55, type  : 'uint:3', wr_dis   : 4, rd_dis: null, alt                            : '', dict: '{0: "Disable", 1: "Enable", 3: "Disable", 7: "Enable"}', desc: Enables flash encryption when 1 or 3 bits are set and disables otherwise, rloc: 'EFUSE_RD_REPEAT_DATA0_REG[25:23]', bloc: 'B6[7],B7[1:0]'}
   SECURE_BOOT_KEY_REVOKE0          : {show: y, blk : 0, word: 1, pos: 26, len  : 1, start : 58, type      : bool, wr_dis   : 5, rd_dis: null, alt                            : '', dict             : '', desc: Revoke 1st secure boot key, rloc: 'EFUSE_RD_REPEAT_DATA0_REG[26]', bloc: 'B7[2]'}
@@ -30,7 +30,7 @@ EFUSES:
   XTS_DPA_PSEUDO_LEVEL             : {show: y, blk : 0, word: 3, pos : 0, len  : 2, start : 96, type  : 'uint:2', wr_dis  : 14, rd_dis: null, alt                            : '', dict             : '', desc: 'Represents the pseudo round level of xts-aes anti-dpa attack. 3: High. 2: Moderate 1. Low 0: Disabled', rloc: 'EFUSE_RD_REPEAT_DATA2_REG[1:0]', bloc: 'B12[1:0]'}
   XTS_DPA_CLK_ENABLE               : {show: y, blk : 0, word: 3, pos : 2, len  : 1, start : 98, type      : bool, wr_dis  : 14, rd_dis: null, alt                            : '', dict             : '', desc: 'Represents whether xts-aes anti-dpa attack clock is enabled. 1. Enable. 0: Disable.', rloc: 'EFUSE_RD_REPEAT_DATA2_REG[2]', bloc: 'B12[2]'}
   ECC_FORCE_CONST_TIME             : {show: y, blk : 0, word: 3, pos : 3, len  : 1, start : 99, type      : bool, wr_dis  : 14, rd_dis: null, alt                            : '', dict             : '', desc: 'Represents whether to force ecc to use const-time calculation mode.  1: Enable.  0: Disable', rloc: 'EFUSE_RD_REPEAT_DATA2_REG[3]', bloc: 'B12[3]'}
-  ECDSA_P384_ENABLE                : {show: y, blk : 0, word: 3, pos : 4, len  : 1, start: 100, type      : bool, wr_dis: null, rd_dis: null, alt                            : '', dict             : '', desc: Represents if the chip supports ECDSA P384, rloc: 'EFUSE_RD_REPEAT_DATA2_REG[4]', bloc: 'B12[4]'}
+  SECURE_BOOT_SHA384_EN            : {show: y, blk : 0, word: 3, pos : 4, len  : 1, start: 100, type      : bool, wr_dis  : 14, rd_dis: null, alt                            : '', dict             : '', desc: Represents if the chip supports Secure Boot using SHA-384, rloc: 'EFUSE_RD_REPEAT_DATA2_REG[4]', bloc: 'B12[4]'}
   SECURE_BOOT_EN                   : {show: y, blk : 0, word: 3, pos : 5, len  : 1, start: 101, type      : bool, wr_dis  : 15, rd_dis: null, alt                            : '', dict             : '', desc: 'Represents whether secure boot is enabled or disabled. 1: enabled 0: disabled', rloc: 'EFUSE_RD_REPEAT_DATA2_REG[5]', bloc: 'B12[5]'}
   SECURE_BOOT_AGGRESSIVE_REVOKE    : {show: y, blk : 0, word: 3, pos : 6, len  : 1, start: 102, type      : bool, wr_dis  : 16, rd_dis: null, alt                            : '', dict             : '', desc: 'Represents whether revoking aggressive secure boot is enabled or disabled. 1: enabled. 0: disabled', rloc: 'EFUSE_RD_REPEAT_DATA2_REG[6]', bloc: 'B12[6]'}
   KM_DISABLE_DEPLOY_MODE           : {show: y, blk : 0, word: 3, pos : 7, len  : 5, start: 103, type  : 'uint:5', wr_dis   : 1, rd_dis: null, alt                            : '', dict             : '', desc: 'Represents whether the new key deployment of key manager is disabled. Bit0: Represents whether the new ECDSA key deployment is disabled0: Enabled1: DisabledBit1: Represents whether the new XTS-AES (flash and PSRAM) key deployment is disabled0: Enabled1: DisabledBit2: Represents whether the new HMAC key deployment is disabled0: Enabled1: DisabledBit3: Represents whether the new DS key deployment is disabled0: Enabled1: Disabled', rloc: 'EFUSE_RD_REPEAT_DATA2_REG[11:7]', bloc: 'B12[7],B13[3:0]'}
@@ -53,10 +53,13 @@ EFUSES:
   HUK_GEN_STATE                    : {show: y, blk : 0, word: 4, pos: 23, len  : 5, start: 151, type  : 'uint:5', wr_dis  : 19, rd_dis: null, alt                            : '', dict             : '', desc: 'Represents whether the HUK generate mode is valid.Odd count of bits with a value of 1: InvalidEven count of bits with a value of 1: Valid', rloc: 'EFUSE_RD_REPEAT_DATA3_REG[27:23]', bloc: 'B18[7],B19[3:0]'}
   FLASH_LDO_EFUSE_SEL              : {show: y, blk : 0, word: 4, pos: 28, len  : 1, start: 156, type      : bool, wr_dis: null, rd_dis: null, alt                            : '', dict             : '', desc: 'Represents whether to select efuse control flash ldo default voltage.  1 : efuse 0 : strapping', rloc: 'EFUSE_RD_REPEAT_DATA3_REG[28]', bloc: 'B19[4]'}
   RESERVE_0_157                    : {show: n, blk : 0, word: 4, pos: 29, len  : 3, start: 157, type  : 'uint:3', wr_dis: null, rd_dis: null, alt                            : '', dict             : '', desc: Reserved; it was created by set_missed_fields_in_regs func, rloc: 'EFUSE_RD_REPEAT_DATA3_REG[31:29]', bloc: 'B19[7:5]'}
-  RESERVE_0_160                    : {show: n, blk : 0, word: 5, pos : 0, len  : 8, start: 160, type  : 'uint:8', wr_dis: null, rd_dis: null, alt                            : '', dict             : '', desc: Reserved; it was created by set_missed_fields_in_regs func, rloc: 'EFUSE_RD_REPEAT_DATA4_REG[7:0]', bloc: B20}
+  USB_DREFH                        : {show: n, blk : 0, word: 5, pos : 0, len  : 2, start: 160, type  : 'uint:2', wr_dis  : 30, rd_dis: null, alt                            : '', dict             : '', desc: Represents the single-end input threshold vrefh of USB_SERIAL_JTAG PHY; 1.76 V to 2 V with step of 80 mV, rloc: 'EFUSE_RD_REPEAT_DATA4_REG[1:0]', bloc: 'B20[1:0]'}
+  USB_DREFL                        : {show: n, blk : 0, word: 5, pos : 2, len  : 2, start: 162, type  : 'uint:2', wr_dis  : 30, rd_dis: null, alt                            : '', dict             : '', desc: Represents the single-end input threshold vrefl of USB_SERIAL_JTAG PHY; 1.76 V to 2 V with step of 80 mV, rloc: 'EFUSE_RD_REPEAT_DATA4_REG[3:2]', bloc: 'B20[3:2]'}
+  USB_OTG_FS_DREFH                 : {show: n, blk : 0, word: 5, pos : 4, len  : 2, start: 164, type  : 'uint:2', wr_dis  : 30, rd_dis: null, alt                            : '', dict             : '', desc: Represents the single-end input threshold vrefh of USB_OTG_FS PHY; 1.76 V to 2 V with step of 80 mV, rloc: 'EFUSE_RD_REPEAT_DATA4_REG[5:4]', bloc: 'B20[5:4]'}
+  USB_OTG_FS_DREFL                 : {show: n, blk : 0, word: 5, pos : 6, len  : 2, start: 166, type  : 'uint:2', wr_dis  : 30, rd_dis: null, alt                            : '', dict             : '', desc: Represents the single-end input threshold vrefl of USB_OTG_FS PHY; 1.76 V to 2 V with step of 80 mV, rloc: 'EFUSE_RD_REPEAT_DATA4_REG[7:6]', bloc: 'B20[7:6]'}
   USB_EXCHG_PINS                   : {show: y, blk : 0, word: 5, pos : 8, len  : 1, start: 168, type      : bool, wr_dis  : 30, rd_dis: null, alt                            : '', dict             : '', desc: 'Represents whether the D+ and D- pins of USB_SERIAL_JTAG PHY is exchanged. 1: exchanged 0: not exchanged', rloc: 'EFUSE_RD_REPEAT_DATA4_REG[8]', bloc: 'B21[0]'}
-  USB_OTG_FS_EXCHG_PINS            : {show: y, blk : 0, word: 5, pos : 9, len  : 1, start: 169, type      : bool, wr_dis: null, rd_dis: null, alt                            : '', dict             : '', desc: 'Represents whether the D+ and D- pins of USB_OTG_FS PHY is exchanged. 1: exchanged 0: not exchanged', rloc: 'EFUSE_RD_REPEAT_DATA4_REG[9]', bloc: 'B21[1]'}
-  USB_PHY_SEL                      : {show: y, blk : 0, word: 5, pos: 10, len  : 1, start: 170, type      : bool, wr_dis: null, rd_dis: null, alt                            : '', dict             : '', desc: 'Represents whether to exchange the USB_SERIAL_JTAG PHY with USB_OTG_FS PHY.  1: exchanged.  0: not exchanged', rloc: 'EFUSE_RD_REPEAT_DATA4_REG[10]', bloc: 'B21[2]'}
+  USB_OTG_FS_EXCHG_PINS            : {show: y, blk : 0, word: 5, pos : 9, len  : 1, start: 169, type      : bool, wr_dis  : 30, rd_dis: null, alt                            : '', dict             : '', desc: 'Represents whether the D+ and D- pins of USB_OTG_FS PHY is exchanged. 1: exchanged 0: not exchanged', rloc: 'EFUSE_RD_REPEAT_DATA4_REG[9]', bloc: 'B21[1]'}
+  USB_PHY_SEL                      : {show: y, blk : 0, word: 5, pos: 10, len  : 1, start: 170, type      : bool, wr_dis  : 30, rd_dis: null, alt                            : '', dict             : '', desc: 'Represents whether to exchange the USB_SERIAL_JTAG PHY with USB_OTG_FS PHY.  1: exchanged.  0: not exchanged', rloc: 'EFUSE_RD_REPEAT_DATA4_REG[10]', bloc: 'B21[2]'}
   SOFT_DIS_JTAG                    : {show: y, blk : 0, word: 5, pos: 11, len  : 3, start: 171, type  : 'uint:3', wr_dis  : 31, rd_dis: null, alt                            : '', dict             : '', desc: 'Represents whether JTAG is disabled in soft way. Odd number: disabled Even number: enabled', rloc: 'EFUSE_RD_REPEAT_DATA4_REG[13:11]', bloc: 'B21[5:3]'}
   IO_LDO_ADJUST                    : {show: y, blk : 0, word: 5, pos: 14, len  : 8, start: 174, type  : 'uint:8', wr_dis: null, rd_dis: null, alt                            : '', dict             : '', desc: Represents configuration of IO LDO mode and voltage., rloc: 'EFUSE_RD_REPEAT_DATA4_REG[21:14]', bloc: 'B21[7:6],B22[5:0]'}
   IO_LDO_1P8                       : {show: y, blk : 0, word: 5, pos: 22, len  : 1, start: 182, type      : bool, wr_dis: null, rd_dis: null, alt                            : '', dict             : '', desc: 'Represents select IO LDO voltage to 1.8V or 3.3V. 1: 1.8V 0: 3.3V', rloc: 'EFUSE_RD_REPEAT_DATA4_REG[22]', bloc: 'B22[6]'}
@@ -75,10 +78,48 @@ EFUSES:
   RESERVE_1_104                    : {show: n, blk : 1, word: 3, pos : 8, len  : 1, start: 104, type      : bool, wr_dis  : 20, rd_dis: null, alt                            : '', dict             : '', desc: Reserved; it was created by set_missed_fields_in_regs func, rloc: 'EFUSE_RD_MAC_SYS3_REG[8]', bloc: 'B13[0]'}
   VDD_SPI_LDO_ADJUST               : {show: y, blk : 1, word: 3, pos : 9, len  : 8, start: 105, type  : 'uint:8', wr_dis  : 20, rd_dis: null, alt                            : '', dict             : '', desc: Represents configuration of FLASH LDO mode and voltage., rloc: 'EFUSE_RD_MAC_SYS3_REG[16:9]', bloc: 'B13[7:1],B14[0]'}
   FLASH_LDO_POWER_SEL              : {show: y, blk : 1, word: 3, pos: 17, len  : 1, start: 113, type      : bool, wr_dis  : 20, rd_dis: null, alt                            : '', dict             : '', desc: 'Represents which flash ldo be select: 1: FLASH LDO 1P2 0 : FLASH LDO 1P8', rloc: 'EFUSE_RD_MAC_SYS3_REG[17]', bloc: 'B14[1]'}
-  SYS_DATA_PART0_0                 : {show: n, blk : 1, word: 3, pos: 18, len : 14, start: 114, type : 'uint:14', wr_dis  : 20, rd_dis: null, alt                            : '', dict             : '', desc: Represents the first 14-bit of zeroth part of system data, rloc: 'EFUSE_RD_MAC_SYS3_REG[31:18]', bloc: 'B14[7:2],B15'}
-  SYS_DATA_PART0_1                 : {show: n, blk : 1, word: 4, pos : 0, len : 32, start: 128, type : 'uint:32', wr_dis  : 20, rd_dis: null, alt                            : '', dict             : '', desc: Represents the first 14-bit of zeroth part of system data, rloc: EFUSE_RD_MAC_SYS4_REG, bloc: 'B16,B17,B18,B19'}
-  SYS_DATA_PART0_2                 : {show: n, blk : 1, word: 5, pos : 0, len : 32, start: 160, type : 'uint:32', wr_dis  : 20, rd_dis: null, alt                            : '', dict             : '', desc: Represents the second 32-bit of zeroth part of system data, rloc: EFUSE_RD_MAC_SYS5_REG, bloc: 'B20,B21,B22,B23'}
-  SYS_DATA_PART1_0                 : {show: n, blk : 2, word: 0, pos : 0, len: 256, start  : 0, type: 'bytes:32', wr_dis  : 21, rd_dis: null, alt                            : '', dict             : '', desc: Represents the zeroth 32-bit of first part of system data, rloc: EFUSE_RD_SYS_PART1_DATA0_REG, bloc: 'B0,B1,B2,B3,B4,B5,B6,B7,B8,B9,B10,B11,B12,B13,B14,B15,B16,B17,B18,B19,B20,B21,B22,B23,B24,B25,B26,B27,B28,B29,B30,B31'}
+  WAFER_VERSION_MINOR              : {show: y, blk : 1, word: 3, pos: 18, len  : 4, start: 114, type  : 'uint:4', wr_dis  : 20, rd_dis: null, alt                            : '', dict             : '', desc: Minor chip version, rloc: 'EFUSE_RD_MAC_SYS3_REG[21:18]', bloc: 'B14[5:2]'}
+  WAFER_VERSION_MAJOR              : {show: y, blk : 1, word: 3, pos: 22, len  : 2, start: 118, type  : 'uint:2', wr_dis  : 20, rd_dis: null, alt                            : '', dict             : '', desc: Major chip version, rloc: 'EFUSE_RD_MAC_SYS3_REG[23:22]', bloc: 'B14[7:6]'}
+  DISABLE_WAFER_VERSION_MAJOR      : {show: y, blk : 1, word: 3, pos: 24, len  : 1, start: 120, type      : bool, wr_dis  : 20, rd_dis: null, alt                            : '', dict             : '', desc: Disables check of wafer version major, rloc: 'EFUSE_RD_MAC_SYS3_REG[24]', bloc: 'B15[0]'}
+  DISABLE_BLK_VERSION_MAJOR        : {show: y, blk : 1, word: 3, pos: 25, len  : 1, start: 121, type      : bool, wr_dis  : 20, rd_dis: null, alt                            : '', dict             : '', desc: Disables check of blk version major, rloc: 'EFUSE_RD_MAC_SYS3_REG[25]', bloc: 'B15[1]'}
+  BLK_VERSION_MINOR                : {show: y, blk : 1, word: 3, pos: 26, len  : 3, start: 122, type  : 'uint:3', wr_dis  : 20, rd_dis: null, alt                            : '', dict             : '', desc: BLK_VERSION_MINOR of BLOCK2, rloc: 'EFUSE_RD_MAC_SYS3_REG[28:26]', bloc: 'B15[4:2]'}
+  BLK_VERSION_MAJOR                : {show: y, blk : 1, word: 3, pos: 29, len  : 2, start: 125, type  : 'uint:2', wr_dis  : 20, rd_dis: null, alt                            : '', dict             : '', desc: BLK_VERSION_MAJOR of BLOCK2, rloc: 'EFUSE_RD_MAC_SYS3_REG[30:29]', bloc: 'B15[6:5]'}
+  FLASH_CAP                        : {show: y, blk : 1, word: 3, pos: 31, len  : 3, start: 127, type  : 'uint:3', wr_dis  : 20, rd_dis: null, alt                            : '', dict             : '', desc: Flash capacity, rloc: 'EFUSE_RD_MAC_SYS3_REG[31]', bloc: 'B15[7],B16[1:0]'}
+  FLASH_VENDOR                     : {show: y, blk : 1, word: 4, pos : 2, len  : 3, start: 130, type  : 'uint:3', wr_dis  : 20, rd_dis: null, alt                            : '', dict             : '', desc: Flash vendor, rloc: 'EFUSE_RD_MAC_SYS4_REG[4:2]', bloc: 'B16[4:2]'}
+  PSRAM_CAP                        : {show: y, blk : 1, word: 4, pos : 5, len  : 3, start: 133, type  : 'uint:3', wr_dis  : 20, rd_dis: null, alt                            : '', dict             : '', desc: Psram capacity, rloc: 'EFUSE_RD_MAC_SYS4_REG[7:5]', bloc: 'B16[7:5]'}
+  PSRAM_VENDOR                     : {show: y, blk : 1, word: 4, pos : 8, len  : 2, start: 136, type  : 'uint:2', wr_dis  : 20, rd_dis: null, alt                            : '', dict             : '', desc: Psram vendor, rloc: 'EFUSE_RD_MAC_SYS4_REG[9:8]', bloc: 'B17[1:0]'}
+  TEMP                             : {show: y, blk : 1, word: 4, pos: 10, len  : 2, start: 138, type  : 'uint:2', wr_dis  : 20, rd_dis: null, alt                            : '', dict             : '', desc: Temp (die embedded inside), rloc: 'EFUSE_RD_MAC_SYS4_REG[11:10]', bloc: 'B17[3:2]'}
+  PKG_VERSION                      : {show: y, blk : 1, word: 4, pos: 12, len  : 3, start: 140, type  : 'uint:3', wr_dis  : 20, rd_dis: null, alt                            : '', dict             : '', desc: Package version, rloc: 'EFUSE_RD_MAC_SYS4_REG[14:12]', bloc: 'B17[6:4]'}
+  PVT_DBIAS                        : {show: y, blk : 1, word: 4, pos: 15, len  : 5, start: 143, type  : 'uint:5', wr_dis  : 20, rd_dis: null, alt                            : '', dict             : '', desc: PVT DBIAS, rloc: 'EFUSE_RD_MAC_SYS4_REG[19:15]', bloc: 'B17[7],B18[3:0]'}
+  ADJUST_1V2                       : {show: y, blk : 1, word: 4, pos: 20, len  : 4, start: 148, type  : 'uint:4', wr_dis  : 20, rd_dis: null, alt                            : '', dict             : '', desc: SPI LDO adjust of 1.2v, rloc: 'EFUSE_RD_MAC_SYS4_REG[23:20]', bloc: 'B18[7:4]'}
+  ADJUST_1V8                       : {show: y, blk : 1, word: 4, pos: 24, len  : 4, start: 152, type  : 'uint:4', wr_dis  : 20, rd_dis: null, alt                            : '', dict             : '', desc: SPI LDO adjust of 1.8v, rloc: 'EFUSE_RD_MAC_SYS4_REG[27:24]', bloc: 'B19[3:0]'}
+  ACTIVE_DCDC_1V25                 : {show: y, blk : 1, word: 4, pos: 28, len  : 4, start: 156, type  : 'uint:4', wr_dis  : 20, rd_dis: null, alt                            : '', dict             : '', desc: DCDC-DCDC DBIAS of 1.25v, rloc: 'EFUSE_RD_MAC_SYS4_REG[31:28]', bloc: 'B19[7:4]'}
+  ACTIVE_DCDC_1V35                 : {show: y, blk : 1, word: 5, pos : 0, len  : 4, start: 160, type  : 'uint:4', wr_dis  : 20, rd_dis: null, alt                            : '', dict             : '', desc: DCDC-DCDC DBIAS of 1.35v, rloc: 'EFUSE_RD_MAC_SYS5_REG[3:0]', bloc: 'B20[3:0]'}
+  SLP_DCDC                         : {show: y, blk : 1, word: 5, pos : 4, len  : 5, start: 164, type  : 'uint:5', wr_dis  : 20, rd_dis: null, alt                            : '', dict             : '', desc: DCDC DBIAS in sleep, rloc: 'EFUSE_RD_MAC_SYS5_REG[8:4]', bloc: 'B20[7:4],B21[0]'}
+  LSLP_HP_DRVB                     : {show: y, blk : 1, word: 5, pos : 9, len  : 5, start: 169, type  : 'uint:5', wr_dis  : 20, rd_dis: null, alt                            : '', dict             : '', desc: HP DRVB in light sleep, rloc: 'EFUSE_RD_MAC_SYS5_REG[13:9]', bloc: 'B21[5:1]'}
+  DSLP_LP_DBIAS                    : {show: y, blk : 1, word: 5, pos: 14, len  : 2, start: 174, type  : 'uint:2', wr_dis  : 20, rd_dis: null, alt                            : '', dict             : '', desc: LP DBIAS in deep sleep, rloc: 'EFUSE_RD_MAC_SYS5_REG[15:14]', bloc: 'B21[7:6]'}
+  TEMP_CALIB                       : {show: y, blk : 1, word: 5, pos: 16, len : 10, start: 176, type : 'uint:10', wr_dis  : 20, rd_dis: null, alt                            : '', dict             : '', desc: Temperature calibration data, rloc: 'EFUSE_RD_MAC_SYS5_REG[25:16]', bloc: 'B22,B23[1:0]'}
+  RESERVED_1_186                   : {show: n, blk : 1, word: 5, pos: 26, len  : 6, start: 186, type  : 'uint:6', wr_dis  : 20, rd_dis: null, alt                            : '', dict             : '', desc: reserved, rloc: 'EFUSE_RD_MAC_SYS5_REG[31:26]', bloc: 'B23[7:2]'}
+  OPTIONAL_UNIQUE_ID               : {show: y, blk : 2, word: 0, pos : 0, len: 128, start  : 0, type: 'bytes:16', wr_dis  : 21, rd_dis: null, alt                            : '', dict             : '', desc: Optional unique 128-bit ID, rloc: EFUSE_RD_SYS_PART1_DATA0_REG, bloc: 'B0,B1,B2,B3,B4,B5,B6,B7,B8,B9,B10,B11,B12,B13,B14,B15'}
+  OCODE                            : {show: y, blk : 2, word: 4, pos : 0, len  : 8, start: 128, type  : 'uint:8', wr_dis  : 21, rd_dis: null, alt                            : '', dict             : '', desc: ADC OCode, rloc: 'EFUSE_RD_SYS_PART1_DATA4_REG[7:0]', bloc: B16}
+  DCDC_OCODE                       : {show: y, blk : 2, word: 4, pos : 8, len  : 8, start: 136, type  : 'uint:8', wr_dis  : 21, rd_dis: null, alt                            : '', dict             : '', desc: DCDC OCode, rloc: 'EFUSE_RD_SYS_PART1_DATA4_REG[15:8]', bloc: B17}
+  VDD_3V4_DOUT                     : {show: y, blk : 2, word: 4, pos: 16, len : 10, start: 144, type : 'uint:10', wr_dis  : 21, rd_dis: null, alt                            : '', dict             : '', desc: ADC dout of vdd 3.4v, rloc: 'EFUSE_RD_SYS_PART1_DATA4_REG[25:16]', bloc: 'B18,B19[1:0]'}
+  ADC1_AVE_INITCODE_ATTEN0         : {show: y, blk : 2, word: 4, pos: 26, len  : 9, start: 154, type  : 'uint:9', wr_dis  : 21, rd_dis: null, alt                            : '', dict             : '', desc: Average initcode of ADC1 atten0, rloc: 'EFUSE_RD_SYS_PART1_DATA4_REG[31:26]', bloc: 'B19[7:2],B20[2:0]'}
+  ADC1_AVE_INITCODE_ATTEN1         : {show: y, blk : 2, word: 5, pos : 3, len  : 9, start: 163, type  : 'uint:9', wr_dis  : 21, rd_dis: null, alt                            : '', dict             : '', desc: Average initcode of ADC1 atten1, rloc: 'EFUSE_RD_SYS_PART1_DATA5_REG[11:3]', bloc: 'B20[7:3],B21[3:0]'}
+  ADC1_AVE_INITCODE_ATTEN2         : {show: y, blk : 2, word: 5, pos: 12, len  : 9, start: 172, type  : 'uint:9', wr_dis  : 21, rd_dis: null, alt                            : '', dict             : '', desc: Average initcode of ADC1 atten2, rloc: 'EFUSE_RD_SYS_PART1_DATA5_REG[20:12]', bloc: 'B21[7:4],B22[4:0]'}
+  ADC1_AVE_INITCODE_ATTEN3         : {show: y, blk : 2, word: 5, pos: 21, len  : 9, start: 181, type  : 'uint:9', wr_dis  : 21, rd_dis: null, alt                            : '', dict             : '', desc: Average initcode of ADC1 atten3, rloc: 'EFUSE_RD_SYS_PART1_DATA5_REG[29:21]', bloc: 'B22[7:5],B23[5:0]'}
+  ADC1_HI_DOUT_ATTEN0              : {show: y, blk : 2, word: 5, pos: 30, len  : 9, start: 190, type  : 'uint:9', wr_dis  : 21, rd_dis: null, alt                            : '', dict             : '', desc: HI dout of ADC1 atten0, rloc: 'EFUSE_RD_SYS_PART1_DATA5_REG[31:30]', bloc: 'B23[7:6],B24[6:0]'}
+  ADC1_HI_DOUT_ATTEN1              : {show: y, blk : 2, word: 6, pos : 7, len  : 9, start: 199, type  : 'uint:9', wr_dis  : 21, rd_dis: null, alt                            : '', dict             : '', desc: HI dout of ADC1 atten1, rloc: 'EFUSE_RD_SYS_PART1_DATA6_REG[15:7]', bloc: 'B24[7],B25'}
+  ADC1_HI_DOUT_ATTEN2              : {show: y, blk : 2, word: 6, pos: 16, len  : 9, start: 208, type  : 'uint:9', wr_dis  : 21, rd_dis: null, alt                            : '', dict             : '', desc: HI dout of ADC1 atten2, rloc: 'EFUSE_RD_SYS_PART1_DATA6_REG[24:16]', bloc: 'B26,B27[0]'}
+  ADC1_HI_DOUT_ATTEN3              : {show: y, blk : 2, word: 6, pos: 25, len  : 9, start: 217, type  : 'uint:9', wr_dis  : 21, rd_dis: null, alt                            : '', dict             : '', desc: HI dout of ADC1 atten3, rloc: 'EFUSE_RD_SYS_PART1_DATA6_REG[31:25]', bloc: 'B27[7:1],B28[1:0]'}
+  ADC1_CH0_ATTEN0_INITCODE_DIFF    : {show: y, blk : 2, word: 7, pos : 2, len  : 3, start: 226, type  : 'uint:3', wr_dis  : 21, rd_dis: null, alt                            : '', dict             : '', desc: Gap between ADC1 CH0 and average initcode, rloc: 'EFUSE_RD_SYS_PART1_DATA7_REG[4:2]', bloc: 'B28[4:2]'}
+  ADC1_CH1_ATTEN0_INITCODE_DIFF    : {show: y, blk : 2, word: 7, pos : 5, len  : 3, start: 229, type  : 'uint:3', wr_dis  : 21, rd_dis: null, alt                            : '', dict             : '', desc: Gap between ADC1 CH1 and average initcode, rloc: 'EFUSE_RD_SYS_PART1_DATA7_REG[7:5]', bloc: 'B28[7:5]'}
+  ADC1_CH2_ATTEN0_INITCODE_DIFF    : {show: y, blk : 2, word: 7, pos : 8, len  : 3, start: 232, type  : 'uint:3', wr_dis  : 21, rd_dis: null, alt                            : '', dict             : '', desc: Gap between ADC1 CH2 and average initcode, rloc: 'EFUSE_RD_SYS_PART1_DATA7_REG[10:8]', bloc: 'B29[2:0]'}
+  ADC1_CH3_ATTEN0_INITCODE_DIFF    : {show: y, blk : 2, word: 7, pos: 11, len  : 3, start: 235, type  : 'uint:3', wr_dis  : 21, rd_dis: null, alt                            : '', dict             : '', desc: Gap between ADC1 CH3 and average initcode, rloc: 'EFUSE_RD_SYS_PART1_DATA7_REG[13:11]', bloc: 'B29[5:3]'}
+  ADC1_CH4_ATTEN0_INITCODE_DIFF    : {show: y, blk : 2, word: 7, pos: 14, len  : 3, start: 238, type  : 'uint:3', wr_dis  : 21, rd_dis: null, alt                            : '', dict             : '', desc: Gap between ADC1 CH4 and average initcode, rloc: 'EFUSE_RD_SYS_PART1_DATA7_REG[16:14]', bloc: 'B29[7:6],B30[0]'}
+  INITCODE_DIFF_1P8_3P3            : {show: y, blk : 2, word: 7, pos: 17, len  : 5, start: 241, type  : 'uint:5', wr_dis  : 21, rd_dis: null, alt                            : '', dict             : '', desc: Initcode diff between IO LDO 1.8v and 3.3v, rloc: 'EFUSE_RD_SYS_PART1_DATA7_REG[21:17]', bloc: 'B30[5:1]'}
+  HI_DOUT_DIFF_1P8_3P3             : {show: y, blk : 2, word: 7, pos: 22, len  : 5, start: 246, type  : 'uint:5', wr_dis  : 21, rd_dis: null, alt                            : '', dict             : '', desc: HI dout diff between IO LDO 1.8v and 3.3v, rloc: 'EFUSE_RD_SYS_PART1_DATA7_REG[26:22]', bloc: 'B30[7:6],B31[2:0]'}
+  RESERVED_2_251                   : {show: n, blk : 2, word: 7, pos: 27, len  : 5, start: 251, type  : 'uint:5', wr_dis  : 21, rd_dis: null, alt                            : '', dict             : '', desc: reserved, rloc: 'EFUSE_RD_SYS_PART1_DATA7_REG[31:27]', bloc: 'B31[7:3]'}
   BLOCK_USR_DATA                   : {show: y, blk : 3, word: 0, pos : 0, len: 192, start  : 0, type: 'bytes:24', wr_dis  : 22, rd_dis: null, alt                     : USER_DATA, dict             : '', desc: User data, rloc: EFUSE_RD_USR_DATA0_REG, bloc: 'B0,B1,B2,B3,B4,B5,B6,B7,B8,B9,B10,B11,B12,B13,B14,B15,B16,B17,B18,B19,B20,B21,B22,B23'}
   RESERVED_3_192                   : {show: n, blk : 3, word: 6, pos : 0, len  : 8, start: 192, type  : 'uint:8', wr_dis  : 22, rd_dis: null, alt                            : '', dict             : '', desc: reserved, rloc: 'EFUSE_RD_USR_DATA6_REG[7:0]', bloc: B24}
   CUSTOM_MAC                       : {show: y, blk : 3, word: 6, pos : 8, len : 48, start: 200, type : 'bytes:6', wr_dis  : 22, rd_dis: null, alt: MAC_CUSTOM USER_DATA_MAC_CUSTOM, dict             : '', desc: Custom MAC, rloc: 'EFUSE_RD_USR_DATA6_REG[31:8]', bloc: 'B25,B26,B27,B28,B29,B30'}

{esptool-5.3.dev1 → esptool-5.3.dev2}/esptool/__init__.py RENAMED Viewed

@@ -31,7 +31,7 @@ __all__ = [
     "write_mem",
 ]
-__version__ = "5.3.dev1"
+__version__ = "5.3.dev2"
 import os
 import shlex

{esptool-5.3.dev1 → esptool-5.3.dev2}/esptool/bin_image.py RENAMED Viewed

@@ -1276,6 +1276,7 @@ class ESP32S31FirmwareImage(ESP32C5FirmwareImage):
     """ESP32S31 Firmware Image almost exactly the same as ESP32C5FirmwareImage"""
     ROM_LOADER = ESP32S31ROM
+    MMU_PAGE_SIZE_CONF = (32768, 65536, 131072, 262144)
 ESP32S31ROM.BOOTLOADER_IMAGE = ESP32S31FirmwareImage

{esptool-5.3.dev1 → esptool-5.3.dev2}/esptool/targets/esp32h4.py RENAMED Viewed

@@ -67,6 +67,8 @@ class ESP32H4ROM(ESP32C3ROM):
     EFUSE_FORCE_USE_KEY_MANAGER_KEY_SHIFT = 19
     FORCE_USE_KEY_MANAGER_VAL_XTS_AES_KEY = 2
+    PURPOSE_VAL_XTS_AES256_KEY_1 = 2
+    PURPOSE_VAL_XTS_AES256_KEY_2 = 3
     PURPOSE_VAL_XTS_AES128_KEY = 4
     FLASH_ENCRYPTED_WRITE_ALIGN = 16
@@ -115,6 +117,8 @@ class ESP32H4ROM(ESP32C3ROM):
     KEY_PURPOSES: dict[int, str] = {
         0: "USER/EMPTY",
         1: "ECDSA_KEY",  # ECDSA_KEY_P256 (NIST P-256)
+        2: "XTS_AES_256_KEY_FLASH_1",
+        3: "XTS_AES_256_KEY_FLASH_2",
         4: "XTS_AES_128_KEY",
         5: "HMAC_DOWN_ALL",
         6: "HMAC_DOWN_JTAG",
@@ -124,20 +128,25 @@ class ESP32H4ROM(ESP32C3ROM):
         10: "SECURE_BOOT_DIGEST1",
         11: "SECURE_BOOT_DIGEST2",
         12: "KM_INIT_KEY",
+        13: "XTS_AES_256_KEY_PSRAM_1",
+        14: "XTS_AES_256_KEY_PSRAM_2",
+        15: "XTS_AES_128_KEY_PSRAM",
         16: "ECDSA_KEY_P192",
         17: "ECDSA_KEY_P384_L",
         18: "ECDSA_KEY_P384_H",
     }
-    # not alloc yet, return 0
     def get_pkg_version(self):
-        return 0
+        num_word = 4
+        return (self.read_reg(self.EFUSE_BLOCK1_ADDR + (4 * num_word)) >> 12) & 0x07
     def get_minor_chip_version(self):
-        return 0
+        num_word = 3
+        return (self.read_reg(self.EFUSE_BLOCK1_ADDR + (4 * num_word)) >> 18) & 0x0F
     def get_major_chip_version(self):
-        return 0
+        num_word = 3
+        return (self.read_reg(self.EFUSE_BLOCK1_ADDR + (4 * num_word)) >> 22) & 0x03
     def get_chip_description(self):
         chip_name = {
@@ -184,8 +193,10 @@ class ESP32H4ROM(ESP32C3ROM):
         )
     def get_key_block_purpose(self, key_block):
-        if key_block < 0 or key_block > 5:
-            raise FatalError("Valid key block numbers must be in range 0-5")
+        if key_block < 0 or key_block > self.EFUSE_MAX_KEY:
+            raise FatalError(
+                f"Valid key block numbers must be in range 0-{self.EFUSE_MAX_KEY}"
+            )
         reg, shift = [
             (self.EFUSE_PURPOSE_KEY0_REG, self.EFUSE_PURPOSE_KEY0_SHIFT),
@@ -207,12 +218,19 @@ class ESP32H4ROM(ESP32C3ROM):
         )
     def is_flash_encryption_key_valid(self):
-        # Need to see an AES-128 key
-        purposes = [self.get_key_block_purpose(b) for b in range(6)]
+        # Need to see an AES-128 key or both AES-256 flash key halves.
+        purposes = [
+            self.get_key_block_purpose(b) for b in range(self.EFUSE_MAX_KEY + 1)
+        ]
         if any(p == self.PURPOSE_VAL_XTS_AES128_KEY for p in purposes):
             return True
+        if any(p == self.PURPOSE_VAL_XTS_AES256_KEY_1 for p in purposes) and any(
+            p == self.PURPOSE_VAL_XTS_AES256_KEY_2 for p in purposes
+        ):
+            return True
         return self.uses_key_manager_for_flash_encryption()
     def check_spi_connection(self, spi_connection):

{esptool-5.3.dev1 → esptool-5.3.dev2}/esptool/targets/stub_flasher/2/README.md RENAMED Viewed

@@ -1,3 +1,3 @@
 # Licensing
-The binaries in JSON format distributed in this directory are dual licensed under the Apache License Version 2.0 or the MIT license. They were released at https://github.com/espressif/esp-flasher-stub/releases/tag/v0.5.0 from where the sources can be obtained.
+The binaries in JSON format distributed in this directory are dual licensed under the Apache License Version 2.0 or the MIT license. They were released at https://github.com/espressif/esp-flasher-stub/releases/tag/v0.5.1 from where the sources can be obtained.

{esptool-5.3.dev1 → esptool-5.3.dev2}/esptool/targets/stub_flasher/2/esp32.json RENAMED Viewed

@@ -1,6 +1,6 @@
 {
     "entry": 1074429964,
-    "text": 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Cp1OQZsKgiBGAZoIMBQYIAMKgALLHbKLHcOUxAKKgAeU7AAwYDApgioMLlgtVbQlaWIInG4xIUIYgVjj9YKYgULUgpSsAFtoAsZ3+uQMioNGtCwYXAACpAyKg0UYQAJLCK5CQdByqlzoswqBIDAtwpyCCZyCB4v3gCACRoP6irKygoqCqmZgJsicg3QfNBq0C4AkARob/sYv+uQNG7P/cCs0HDAsgoiCldf/GBQChif4McqC6IMKgACCiIGV0/4GH/gwJmQhhhf4MBYgGWQOMiKLHYOAIAKkDWQYd8AAANkEApbQABgIAAAAA5bQApRz/JbQAVjr/kAAAADZBAKKgAOWsAIKhAYcKHKKgACU4AKBqIAwHxgIAoqAApa0ApRn/cscBd5bwHfAAADZBAGWyACKgAVZaACWuAKAqgB3wXIEKQAibCkAQmwpAhI8KQOiaCkDwmgpAoI8KQFyTCkA2QQAmEgYmIheGCwAAsfT/HBqlrgCh8/+lB/+h8/8GDwClNQCx8v/CoAQcGmWpAKHw/yUG/6Hv/4YIABwKoton5SMADAqlJgDB7P/SoQEMW6KgAOUoAKHp/6UD/wwKZQT/HfAABgAAEDZBACCCICH9/xYYAfIoBehI2DjIKLgYqAhlNgAtCh3wNkEAJTMAMDB0MLMgIKIgZTcAHfABAAAQWO39PzZBACCiIOV+AOV3AC0KpagAoLogcqAAVnoApaoAcfb/vQoMGICIAbe4B4H0/wwZkkgA8q//0qABwqAB8PD14qEAQN0RAMwRrQKlLwCgepMtBx3wADZBAGVyAIIqAIJiAIIqAYkSiCqJIog6iTKISolCiFqJUh3wAAIAABA2QQBAgiCAgBQgoiAwsyAh+/9A1CDc2IHa/4IIAIy4vQrNAwwa5V0ABgIAAM0EEBEgpTEALQod8AMAABA2QQBAgiCAgBStAr0DIfv/zQRQ0HTcyIHL/4IIAIz47Q29Ct0EzQMMGiVHAMYAAADlKgAtCh3wADZBAGUvAC0KHfAAADZBAG0CfQMioAAMA6UvABYaAqKgAaUMABuTDBg3OQEMCCooPQl3MuMnlwJnOd0hofxGAAAMAh3wNmEADAkMGAwbIImTMJuDkIggfQKtBIxIIZ3/RiAAsqAAgmEAJfr/IZX8VioHUiMAiAHMNQwChhkAfPmQkPVIB1e5BECQ9IzJQJC0Vpn8DBZAZhEGAgBioAGCoAEAZhGRmv+SCQAWWQG9BAwajEilVQCGAAAlVAAtCpwaRggArQSMSGUrAEYBABARIOUnAEpGSQcMCGc1AmCFwIkDBuX/AB3wAAA0hQBANkEAIKIggf3/4AgAHfAAADZBAKWOAC0KHfAAADZBACCiIDCzIGVuAKAqIB3wAAAANkEAIKB0JVAAHfAANkEAvQMgoHRlaQAd8AAAADZBACCgdKVPAB3wAOxnAEAIaABANkEAfEiC2ECKgr0EAIgRDAm2IgQMeTCZEZoofPjAIACJQgwMMKMggfT/4AgAjLXAIACIMlCIIMAgAIkyDBoAE0AAqqGB7v/gCAAd8BwA9D82QQAMCLYiBAx4MIgRkfv/ACIRmiKKIsAgACgCICB0HfAAAAAAkgBANkEAIKB0gf3/4AgALQod8DZBACVkAKKgiKLaE6Xw/x3wAAAANkEA5WgAHfA2QQCtAmVFAB3wAAA2QQCtAr0DzQSlRQAd8AAANkEAIKIgMLMgJUYAkAAAADZBACF4/R3w3J8AQDZBAKKgBoH9/+AIAAx6gfv/4AgADIqB+f/gCAAMuoH3/+AIAB3wAAA4MgZANkEA/QetAr0DzQTdBe0Ggfv/4AgADBKgKoNAIgEd8ABsKgZANkEArQIwsHSB/f/gCAAd8CAjBkA2QQDlPwCB/f/gCAAd8AAACAAAEHguBkBQLQZANkEAUFB0rQK9A80EjIWB+v/gCACGAQAAgfn/4AgALQqMGiH0/x3wAAQAABDYLgZANkEArQIwsyBAxCCB/P/gCAAtCowaIfj/HfAAABQsBkA2QQCB/v/gCAAMEqAqg0AiAR3wABAg9D8AIPQ/NkEAZTsAgfz/kqAAwCAAkmgAoqABkfn/UKoBwCAAqQnAIACoCVZ6/8AgACgIICAEHfAAAAQg9D82QQDl8/+lNwCB/P+AIhEgKEHAIAApCAwZger/gJkBwCAAmQjAIACYCFZ5/x3wAAA2QQDl8P+lNACB8P+AIhEgKEHAIAApCAwZgd7/kJkBwCAAmQjAIACYCFZ5/x3wAAD0LQZANkEAgf7/4AgAHfAAYC4GQDZBAIH+/+AIAB3wALAoBkA2QQCB/v/gCAAMEqAqg0AiAR3wADbBAIKgBIJhAYKgEokhDIiJMSwIiVEMCIlhiZGJoa0BDBgpATlBSXFZgYmxgkEw5VwAHfA2wQCioBCi2ieyoABlvv99Ai0K7Nrl5f8MWIkRDIiJMSwIiVGtAQwYeQFJITlBKWEpcSmBKZEpoYmxgkEwpVgAxgAAACGZ+x3wAAAANmEAsqP/YJB0KRG6ZQwKt7YBDBoASkBgaoE8CqLadaCGgqBmookBFtkKMKUgoKA0Icz+VhoPZfH/JU8ADBLl8v9AIgFWegiiIQBgtiCltf8tChZqByGB+8YcAAAwsFQwoHTcO7KvP7q6PPy3vBJMB1c8HoYCAAAAADCwRBwHVgsBgq8fiqoc+6e7BCwHVzsBHAe9BK0DzQelSQDl2P+oAb0GZdH/Vsr6qBHQ1xG9AwvdDAzl7P9lSACoAWC2IKWu/1YK+XpEcDOAcFXAVsX45ej/hhQAAAAAoiEAYLYgpaz/oCogLA4WugMhXPsGDgAAADBwdHLX/+ClY3BwYKB3Y2XS/6gRcND0vQPQ3RHNBCXn/6gBvQYlqf9Wyvx6RHozcFXALA5Whfwd8AAANsEAoqAQotonsqAA5ab/IHIgLQpWygRGEAAAAACwZWOCoASSoCCCYQGZUQzIYJD0iSHQmREMiIkxiWGZoQwIDBmtATlBSZF5AYlxiYGZsYJBMGBVwKU/AGpEajMcC1a1+4YAACEz+x3wAAAANkEArQK9AywcJeH/LQod8DZBACCiIDCzIMKg3OXf/6AqIB3weJIAQDZBACCgdIH9/+AIAB3wAABYkgBANkEAIKB0gf3/4AgAHfAAAHzaBUA2QQAgoiCB/f/gCAAd8AAAnNoFQDZBAK0CvQNAxCCB/P/gCAAd8AAAHNsFQDZBAL0CrQOB/f/gCAAd8ABw4vo/NkEAIf7/HfCAIPQ/NkEAgf7/DAnAIACZCKKgAZEa/0CqAcAgAKJpAMAgAKgJVnr/wCAAKAggIHUd8AAA+CD0PzZBAJH+/8AgAIgJgIAkVkj/HfAAHCD0P1zt/T82QQCM0oH8/8AgAJgIgfv/mQiJAh3wAABYhgBANkEAgf7/4AgAfQqMMq0CZf3/cKcgsqAApbX/kfD/oq//wCAAiAkQqgGgiCDAIACJCR3wAIC6jAEAWmICALTEBHCA9D+fZNEBtID0P4iFAEA2QQCB+/+SoAHAIACCKABQmQGAixVQiAEh9f+XGE6B9//gCACB9P8h8P+nOAIh7f+h8v8MC8AgAIgKDByAkPWAgPSQiMCAy5MMGJCLg4cMD3z4gID1hxkHQCkRhgMAAAAgnEEAiRGaiMAgAIkKHfAAzJAAQDZBAHKgiHLXE60HpZH/5ff/ICB0wKoRMDrCrQLl4/+tAr0Dgfb/4AgArQelj/8d8DZBACEB/B3wfID0P////+dg7f0/AGiJCRgw9D9QhQBANkEAkfn/DHrAIACICVCqEaCIIMAgAIkJkcX/ofT/wCAAiAmgiBAMGlCqAaCIIMAgAIkJge//ke//oqCgmQiB7//gCACB7f8MCcAgAJkIHfBIgPQ/pID0P6E62FCMgPQ/NkEAkfv/DIrAIACICaCIIMAgAIkJgff/kfj/ofj/wCAAmQgMCcAgAJkKwCAAmQgd8AAAADZBAJICAYICAICZEYCZIIICAiICAwCIEZCIIIAiAYAiIB3wADZBACKg/4AiER3wADZBAHxIgthAioIAiBEMCbYiBZKgBzCZEZqIwCAAKCjAIAApSB3wAAA2QQB8SILYQIqCAIgRDAm2IgWSoAcwmRGaiMAgACgIICB0HfA2QQAMAh3wADZBAB3wAAAANkEADAId8AA2QQAMAh3wADZBAAwCHfAANkEADBId8AA2QQAd8AAAADZBAAwCHfAANkEAHfAAAAA2QQAMAh3wADZBAB3wAAAANkEADAId8AA2QQAd8AAAADZBAB3wAAAANkEAHfAAAAA2QQAd8AAAADZBACCAdBzJhzkRDBIcGQAYQAAioYc5EAwCxgIAgsjHgPhAgIVBcCgBHfAANkEADBKAIgEd8AAANkEAHfAAAAA2QQAMAh3wAA==",
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Cp1OQZsKgiBGAZoIMBQYIAMKgALLHbKLHcOUxAKKgAeU7AAwYDApgioMLlgtVbQlaWIInG4xIUIYgVjj9YKYgULUgpSsAFtoAsZ3+uQMioNGtCwYXAACpAyKg0UYQAJLCK5CQdByqlzoswqBIDAtwpyCCZyCB4v3gCACRoP6irKygoqCqmZgJsicg3QfNBq0C4AkARob/sYv+uQNG7P/cCs0HDAsgoiCldf/GBQChif4McqC6IMKgACCiIGV0/4GH/gwJmQhhhf4MBYgGWQOMiKLHYOAIAKkDWQYd8AAANkEApbQABgIAAAAA5bQApRz/JbQAVjr/kAAAADZBAKKgAOWsAIKhAYcKHKKgACU4AKBqIAwHxgIAoqAApa0ApRn/cscBd5bwHfAAADZBAGWyACKgAVZaACWuAKAqgB3wXIEKQAibCkAQmwpAhI8KQOiaCkDwmgpAoI8KQFyTCkA2QQAmEgYmIheGCwAAsfT/HBqlrgCh8/+lB/+h8/8GDwClNQCx8v/CoAQcGmWpAKHw/yUG/6Hv/4YIABwKoton5SMADAqlJgDB7P/SoQEMW6KgAOUoAKHp/6UD/wwKZQT/HfAABgAAEDZBACCCICH9/xYYAfIoBehI2DjIKLgYqAhlNgAtCh3wNkEAJTMAMDB0MLMgIKIgZTcAHfABAAAQWO39PzZBACCiIOV+AOV3AC0KpagAoLogcqAAVnoApaoAcfb/vQoMGICIAbe4B4H0/wwZkkgA8q//0qABwqAB8PD14qEAQN0RAMwRrQKlLwCgepMtBx3wADZBAGVyAIIqAIJiAIIqAYkSiCqJIog6iTKISolCiFqJUh3wAAIAABA2QQBAgiCAgBQgoiAwsyAh+/9A1CDc2IHa/4IIAIy4vQrNAwwa5V0ABgIAAM0EEBEgpTEALQod8AMAABA2QQBAgiCAgBStAr0DIfv/zQRQ0HTcyIHL/4IIAIz47Q29Ct0EzQMMGiVHAMYAAADlKgAtCh3wADZBAGUvAC0KHfAAADZBAG0CfQMioAAMA6UvABYaAqKgAaUMABuTDBg3OQEMCCooPQl3MuMnlwJnOd0hofxGAAAMAh3wNmEADAkMGAwbIImTMJuDkIggfQKtBIxIIZ3/RiAAsqAAgmEAJfr/IZX8VioHUiMAiAHMNQwChhkAfPmQkPVIB1e5BECQ9IzJQJC0Vpn8DBZAZhEGAgBioAGCoAEAZhGRmv+SCQAWWQG9BAwajEilVQCGAAAlVAAtCpwaRggArQSMSGUrAEYBABARIOUnAEpGSQcMCGc1AmCFwIkDBuX/AB3wAAA0hQBANkEAIKIggf3/4AgAHfAAADZBAKWOAC0KHfAAADZBACCiIDCzIGVuAKAqIB3wAAAANkEAIKB0JVAAHfAANkEAvQMgoHRlaQAd8AAAADZBACCgdKVPAB3wAOxnAEAIaABANkEAfEiC2ECKgr0EAIgRDAm2IgQMeTCZEZoofPjAIACJQgwMMKMggfT/4AgAjLXAIACIMlCIIMAgAIkyDBoAE0AAqqGB7v/gCAAd8BwA9D82QQAMCLYiBAx4MIgRkfv/ACIRmiKKIsAgACgCICB0HfAAAAAAkgBANkEAIKB0gf3/4AgALQod8DZBACVkAKKgEKLaJ6Xw/5AAAAAANkEA5WgAHfA2QQCtAmVFAB3wAAA2QQCtAr0DzQSlRQAd8AAANkEAIKIgMLMgJUYAkAAAADZBACF4/R3w3J8AQDZBAKKgBoH9/+AIAAx6gfv/4AgADIqB+f/gCAAMuoH3/+AIAB3wAAA4MgZANkEA/QetAr0DzQTdBe0Ggfv/4AgADBKgKoNAIgEd8ABsKgZANkEArQIwsHSB/f/gCAAd8CAjBkA2QQDlPwCB/f/gCAAd8AAACAAAEHguBkBQLQZANkEAUFB0rQK9A80EjIWB+v/gCACGAQAAgfn/4AgALQqMGiH0/x3wAAQAABDYLgZANkEArQIwsyBAxCCB/P/gCAAtCowaIfj/HfAAABQsBkA2QQCB/v/gCAAMEqAqg0AiAR3wABAg9D8AIPQ/NkEAZTsAgfz/kqAAwCAAkmgAoqABkfn/UKoBwCAAqQnAIACoCVZ6/8AgACgIICAEHfAAAAQg9D82QQDl8/+lNwCB/P+AIhEgKEHAIAApCAwZger/gJkBwCAAmQjAIACYCFZ5/x3wAAA2QQDl8P+lNACB8P+AIhEgKEHAIAApCAwZgd7/kJkBwCAAmQjAIACYCFZ5/x3wAAD0LQZANkEAgf7/4AgAHfAAYC4GQDZBAIH+/+AIAB3wALAoBkA2QQCB/v/gCAAMEqAqg0AiAR3wADbBAIKgBIJhAYKgEokhDIiJMSwIiVEMCIlhiZGJoa0BDBgpATlBSXFZgYmxgkEw5VwAHfA2wQCioBCi2ieyoABlvv99Ai0K7Nrl5f8MWIkRDIiJMSwIiVGtAQwYeQFJITlBKWEpcSmBKZEpoYmxgkEwpVgAxgAAACGZ+x3wAAAANmEAsqP/YJB0KRG6ZQwKt7YBDBoASkBgaoE8CqLadaCGgqBmookBFtkKMKUgoKA0Icz+VhoPZfH/JU8ADBLl8v9AIgFWegiiIQBgtiCltf8tChZqByGB+8YcAAAwsFQwoHTcO7KvP7q6PPy3vBJMB1c8HoYCAAAAADCwRBwHVgsBgq8fiqoc+6e7BCwHVzsBHAe9BK0DzQelSQDl2P+oAb0GZdH/Vsr6qBHQ1xG9AwvdDAzl7P9lSACoAWC2IKWu/1YK+XpEcDOAcFXAVsX45ej/hhQAAAAAoiEAYLYgpaz/oCogLA4WugMhXPsGDgAAADBwdHLX/+ClY3BwYKB3Y2XS/6gRcND0vQPQ3RHNBCXn/6gBvQYlqf9Wyvx6RHozcFXALA5Whfwd8AAANsEAoqAQotonsqAA5ab/IHIgLQpWygRGEAAAAACwZWOCoASSoCCCYQGZUQzIYJD0iSHQmREMiIkxiWGZoQwIDBmtATlBSZF5AYlxiYGZsYJBMGBVwKU/AGpEajMcC1a1+4YAACEz+x3wAAAANkEArQK9AywcJeH/LQod8DZBACCiIDCzIMKg3OXf/6AqIB3weJIAQDZBACCgdIH9/+AIAB3wAABYkgBANkEAIKB0gf3/4AgAHfAAAHzaBUA2QQAgoiCB/f/gCAAd8AAAnNoFQDZBAK0CvQNAxCCB/P/gCAAd8AAAHNsFQDZBAL0CrQOB/f/gCAAd8ABw4vo/NkEAIf7/HfCAIPQ/NkEAgf7/DAnAIACZCKKgAZEa/0CqAcAgAKJpAMAgAKgJVnr/wCAAKAggIHUd8AAA+CD0PzZBAJH+/8AgAIgJgIAkVkj/HfAAHCD0P1zt/T82QQCM0oH8/8AgAJgIgfv/mQiJAh3wAABYhgBANkEAgf7/4AgAfQqMMq0CZf3/cKcgsqAApbX/kfD/oq//wCAAiAkQqgGgiCDAIACJCR3wAIC6jAEAWmICALTEBHCA9D+fZNEBtID0P4iFAEA2QQCB+/+SoAHAIACCKABQmQGAixVQiAEh9f+XGE6B9//gCACB9P8h8P+nOAIh7f+h8v8MC8AgAIgKDByAkPWAgPSQiMCAy5MMGJCLg4cMD3z4gID1hxkHQCkRhgMAAAAgnEEAiRGaiMAgAIkKHfAAzJAAQDZBAHKgiHLXE60HpZH/5ff/ICB0wKoRMDrCrQLl4/+tAr0Dgfb/4AgArQelj/8d8DZBACEB/B3wfID0P////+dg7f0/AGiJCRgw9D9QhQBANkEAkfn/DHrAIACICVCqEaCIIMAgAIkJkcX/ofT/wCAAiAmgiBAMGlCqAaCIIMAgAIkJge//ke//oqCgmQiB7//gCACB7f8MCcAgAJkIHfBIgPQ/pID0P6E62FCMgPQ/NkEAkfv/DIrAIACICaCIIMAgAIkJgff/kfj/ofj/wCAAmQgMCcAgAJkKwCAAmQgd8AAAADZBAJICAYICAICZEYCZIIICAiICAwCIEZCIIIAiAYAiIB3wADZBACKg/4AiER3wADZBAHxIgthAioIAiBEMCbYiBZKgBzCZEZqIwCAAKCjAIAApSB3wAAA2QQB8SILYQIqCAIgRDAm2IgWSoAcwmRGaiMAgACgIICB0HfA2QQAMAh3wADZBAB3wAAAANkEADAId8AA2QQAMAh3wADZBAAwCHfAANkEADBId8AA2QQAd8AAAADZBAAwCHfAANkEAHfAAAAA2QQAMAh3wADZBAB3wAAAANkEADAId8AA2QQAd8AAAADZBAB3wAAAANkEAHfAAAAA2QQAd8AAAADZBACCAdBzJhzkRDBIcGQAYQAAioYc5EAwCxgIAgsjHgPhAgIVBcCgBHfAANkEADBKAIgEd8AAANkEAHfAAAAA2QQAMAh3wAA==",
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{esptool-5.3.dev1 → esptool-5.3.dev2}/esptool/targets/stub_flasher/2/esp32c2.json RENAMED Viewed

@@ -1,6 +1,6 @@
 {
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u7/DvqQUE5bdBEQbGsS6qhwVFmeM1LgYFskBBAYKAQREGxoVHYwz1AolHYw31BAllEwUFca0kAUWNLDcWOECTBhAQEwam55VFAUWNLDcVOEATBeUe7/AvmQFFDaC3BThAk4VFFEVFGSY3FThAEwVFIe/wb5c3FThAEwWFIbJAQQFv8C+XISa3FThAEUaThSXmRUXJJDcVOEATBYUg7/CvlDcVOEATBcUg0b8ByVxJGElURRBFTEEIQQ2mNwUAEBkFgoABEQbOKsYuxMUkokUyRfJABWGBrkERBsYmwiLEuSaVJqqEOSYV7Q0uNwQAEKqFBQS3BwABY/e3ALd3yz8FRyOO59RBZpMH9v8TBwAQhWYmheEkEeEihbJAIkSSREEBgoCqhQFE8bdBESLEBsYqhCkmHEGyQBzAXEFcwBxFHMRcRVzEHEkcyFxJXMgiREEBgoCzZ8UAjYuyhpnrt3fLP4PHx9WJxy6GqoUFReWjFaY3BQAQCQWCgLNnxQCNizaHge+3d8s/g8fH1ZHHsoYuhqqFBUWlodmsNwUAEA0FgoAxpgERIswmykrITsYGzqqJLokBRIFEOSYVwQVFzSCTBxQAM7eHALqUPoTj5iT/YxSZAOPiN/83BQAQJQXyQGJE0kRCSbJJBWGCgAERTsaTNxUAk7kVAAbOIswmykrIUsRWwrPp+QBjjgkANwUAEBkF8kBiRNJEQkmySSJKkkoFYYKALoqqioFFMoWlPyqHNwUAECUFcf8DJAoAGeABRcm/QWmDpAoAY2YkAZOXBAHBg4XPk5dEAQVpzfu3d8s/g8fH1Z3HpoUFRWOCCQJBK03xswckQTM0JAHKlH0UI6CaAH2MIyCKAF2/hUnBv60jxbcmhWOECQC1LOG/gSzRvxfzx/9nAAPwsau5qxN19Q9RqxN19Q9toxN19Q9BqwERtwcAYCLMwQcTFAUBJsoGzq6Eopd9V7KFmMMBRiaFNsaX8Mf/54DAZrJGgcq3BwBgsQc+lBxA1Y8cwGJEBUXyQDMVlQDSRAVhF/PH/2cAw2Q3BwBgkxcFASEHPpcIQzcHAGBBB7qXiMOCgLcHAGDxB0IFPpUIQRN19T+CgJlnPpVCBQhBE3X1D4KAF/PH/2cAo+YBRYKAgoABRYKAAUWCgAFFgoAFRYKAgoABRYKAgoABRYKAgoABRYKAgoBBEQbG0S2yQAllEwUFcUEBEb9vAOBybwDgd28AIHhvAGB4goCCgDcFABAVBYKAgoBBET1FBsaX8Mf/54DgVUVFl/DH/+eAQFVBRZfwx//ngKBUskA5RUEBF/PH/2cAw1NBEQbGl/DH/+eAgOyyQDM1oAByBUEBgoATdfUP8Udj56cAxUdj6qcAAUWCgBMFdfwTNRUAZgWCgIVHM5WnAIKANwUAAYKAAUWCgBfzx/9nAOPqQREGxsU/skCBRUEB9be3B84/A6UH/4KAQREGxpfwx//ngCDn7TeyQAhBQQGCgEERBsbxP7JAQQEX88f/ZwDj40ERBsaBzpfwx//ngIDeAcU3BQAQIQWyQEEBgoCX8Mf/54Cg4O23QREGxpfwx//ngADgAcU3BQAQEQWyQEEBgoBBEQbGl/DH/+eAoNuyQDM1oAByBUEBgoBBEQbGaSY3JwBgtwYACCMmBwKTB8cCFMMUQ/3+iEOyQAWJQQGCgAERKsYGzq03hSYyRTcHAAGTB/f/fY23JwBgyMOYw5hDff/yQAVhgoABESrGBs6JNyUuMkW3JwBgNweAACIFIYHIw5jDmEN9//JABWGCgIKAF/PH/2cAg9IX88f/ZwBD0kERBsaX8Mf/54DA1LJAMzWgAHIFQQGCgF1xkUc+yMlHPsqhRz7MkwcAAirGPtBoAIVHhsYuzgLSMtQ21gLYAto+3CMO8QJlN7ZAYWGCgB1xpsqqhAllysgTBQVxLomBRc7Ghs6izLKJxT4h4SqETTWVRz7IoUc+zJMHAAI+0GgAhUcmxk7KSs4C0gLUAtYC2ALaPtwjDvECmT/2QCKFZkTWREZJtkklYYKANwQAECUE7bd5cZOH9j8m0raEs7bXANoGqYO2l51mk4YGU0rQUsxexmLEZsIG1iLUTs5WylrIs4vXAqqMLokyijO81wJjAgcMs+e0ADcEABC9iw0Ere/FPYE79T03BAAQNeVeheKF7/CftCqEKe39ShML8AOhzBN3+QOTd/kPNedjeZsGE4f385MJAARjdusG0oVKhU6GETv5M16F4oU5Mx3hk5Y5AMqFZoX9FgFGwTURM16F4oXv8J+vEeVOmk6Zs4Q0QUW/NwQAECUESTWyUCKFIlSSVAJZ8kliStJKQkuySyJMkkxFYYKAE3f5AcFJRfPBSeP+mviTh/fxs7f6AJOZRwDBCWm3XoXihe/wP6oqhDnhkwoAEBMLAALN2JN5+Q+ziTpBpodjdJsAkwcAAmPzNwG+iQU7yoVmhZOWOQBShjU1XoXihe/wf6YR5U6aTpmzhDRB2bc3BAAQJQSFvxlx7saqjQllytgTBQVxLomBRabaztaG3qLc0tTW0trQ3s7izObK6siyibaE7/A/oi3lKoRBS5FLMUyhSpMMAAIFTY3g9lAihWZU1lRGWbZZJlqWWgZb9ktmTNZMRk22TQlhgoAmimNzmwBBSpMXOgBoAErOTthuxl7IYspWzGbQVtIC1ALWPtpq3CMOAQKzhERBiTvSmVKZbbc3BAAQJQRVtxMGEAJ5uxMGwA1hu1FFgoAZ6TcFABAZBYKANwUAEBkF8kAFYYKAAREuxgbOKsT5P7JF4+Sl/iJGgUUBRZfwx//ngICdMzWgAHIF2b8X88f/ZwDDmBfzx/9nAAOYNycAYBxDvYv1/4KAAREizCqEBWUTBYU4Bs4uxu/wH6MtJLJFEgWzVbUCIoUuxsk3skUihZfwx//ngMCUYkTyQAVlEwWFOAVhb/BfoLcHDGCYSwERiWYizCbKSshOxgbOVY+Yy7cHDGCYT/l2/RZ1j5jPN4QAYCRUPFTxdpOG9gOT9/f7PNRcTBMFIAOT+QQE9Y+T5wcUXMw8VBP5BAiT9AQgk/f39zzUl/DH/+eAQIo8VLf2AWCThoYGk+cHIDzUnEITlzcBY1QHArf3AWCThwcImEMTd/cPE2cHCJjDmEITFgcBY0UGAJhDBYtt27f3AWC4V+l2/RZ1j4lmVY+417hX/Xb9FnWPuNe4V7cGAYD9FnWPtwYKAFWPt/YBYLjXk4YGCJhCNwZQAJOHhwYTd/cHUY+YwphDNwYAgJMF9v9tj5jDmEOhZVGPmMOYQ22PRce39wFg+Fcdg7f2AWC8VoYHhYO81pnkt4cAYLRXk/b237TXY4IJAreHAGC0V3F2Ewb2A5PmBgS017eGAGDcTvGPk+cHUNzOYwgJALeHAGC0V5PmBgi017dnYgKThwegBc83BQsBEwUFdrM1pwI3hpaYgUYzBacCl/DH/+eAABO3x4wBEwcAApOHB6hjdqcAt2diApOHB6DyQGJE0kRCSbJJPoUFYYKAkEIFiiHasb83BwxgPE/9dpOG9j9BEfWPBsaT5wdAPM+3BwxgmEdtm5jHLTW3d8s/k4cH1ojDBgXIw7dHDwCThwckM1X1ArJAQQEX88f/ZwCj40ERIsQ3dMs/EwQE1ghABsYZ4cU7CMCyQCJEQQGCgLeHAGD4Q7dG2FCThhaqE2eHAPjDE4fHCRTDI6IHCCMgBwD4Q6FmNwYAgFWP+MO3hwBgNzcdj5OHRwoTB6cSmMM3hwBgEwcHChRD0Y4UwyOgBwCCgBcTyP9nAAMjFxPI/2cAwyIXE8j/ZwCDIg==",
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{esptool-5.3.dev1 → esptool-5.3.dev2}/esptool/targets/stub_flasher/2/esp32c3.json RENAMED Viewed

@@ -1,6 +1,6 @@
 {
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{esptool-5.3.dev1 → esptool-5.3.dev2}/esptool/targets/stub_flasher/2/esp32c5.json RENAMED Viewed

@@ -1,6 +1,6 @@
 {
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u7/DvqQUE5bdBEQbG3SaqhwVFmeOBJgYFskBBAYKAQREGxoVHYwz1AolHYw31BAllEwUFcbUkAUWVLDcWgECTBhAQEwam55VFAUWVLDcVgEATBSUf7/AvmQFFDaC3BYBAk4VFFEVFQS43FYBAEwXlKe/wb5c3FYBAEwUlKrJAQQFv8C+XUS63FYBAEUaThSXmRUXVJDcVgEATBSUk7/CvlDcVgEATBaUo0b8ByVxJGElURRBFTEEIQWmuNwUAEBkFgoABEQbOKsYuxKEuokUyRfJABWHJpkERBsYmwiLEwSbZLqqEWSYd7e8AMAs3BAAQqoUFBLcHAAFj97cAtzeFQAVHI47n1EFmkwf2/xMHABCFZiaFPS4R4SKFskAiRJJEQQGCgKqFAUTxt0ERIsQGxiqErS4cQbJAHMBcQVzAHEUcxFxFXMQcSRzIXElcyCJEQQGCgLNnxQCNi7KGmeu3N4VAg8fH1YnHLoaqhQVFma1RrjcFABAJBYKAs2fFAI2LNoeB77c3hUCDx8fVkceyhi6GqoUFRdmpmaY3BQAQDQWCgLWuAREizCbKSshOxgbOqokuiQFEgUS9LhXBBUXNIJMHFAAzt4cAupQ+hOPmJP9jFJkA4+I3/zcFABAlBfJAYkTSREJJskkFYYKAARFOxpM3FQCTuRUABs4izCbKSshSxFbCs+n5AGOOCQA3BQAQGQXyQGJE0kRCSbJJIkqSSgVhgoAuiqqKgUUyhaU/Koc3BQAQJQVx/wMkCgAZ4AFFyb9BaYOkCgBjZiQBk5cEAcGDhc+Tl0QBBWnN+7c3hUCDx8fVncemhQVFY4IJAv0rTfGzByRBMzQkAcqUfRQjoJoAfYwjIIoAXb+FScG/4SvFtyaFY4QJAPUk4b/BJNG/F/N//2cAY+/po/GjE3X1DwmlE3X1DxGlE3X1D5GlARG3BwBgIszBBxMUxQAmygbOroSil31XsoWYwwFGJoU2xpfwf//ngGBeskaByrcHAGCxBz6UHEDVjxzAYkQFRfJAMxWVANJEBWEX83//ZwBjXDcHAGCTF8UAIQc+lwhDNwcAYEEHupeIw4KAtwcAYPEHMgU+lQhBE3X1D4KAtwcGAD6VMgUIQRN19Q+CgBfzf/9nAGPmQREGxpfwf//ngKDrgUcRxYNHhQH1F5O3FwCyQD6FQQGCgG8AAHS39wBgyEfIy4KAt/cAYMhDCYEFiYKAt/cAYIhDE3X1D4KAAREmyk7GsWS3+QBgIsxKyAbOKoQBSZEJk4QENQVF3TWDpwkAiYuB7wUJ4xmZ/gVF8kBiRNJEQkmySQVhgoC39wBggMMBRe23t/cAYNhDE2cXANjDgoABRYKAgoABRYKAgoABRYKAgoBBEQbG7wDgcLJACWUTBQVxQQFptW8AAHT1oc2p5alBEVVFBsaX8H//54BgRkVFl/B//+eAwEVZRZfwf//ngCBFskBBRUEBF/N//2cAQ0RBEQbGl/B//+eAQOeyQDM1oAByBUEBgoATdfUP8Udj56cAxUdj6qcAAUWCgBMFdfwTNRUAZgWCgIVHM5WnAIKAAUWCgBfzf/9nAEPrQREGxsU/skCBRUEB9be3B4ZAA6XH/oKAQREGxpfwf//ngEDi7TeyQAhBQQGCgEERBsbxP7JAQQEX83//ZwAD30ERBsaBzpfwf//ngKDZAcU3BQAQIQWyQEEBgoCX8H//54DA2+23QREGxpfwf//ngCDbAcU3BQAQEQWyQEEBgoBBEQbGl/B//+eAwNayQDM1oAByBUEBgoBBEQbGkSk3NwBgtwYACCMmBwKTB8cCFMMUQ/3+iEOyQAWJQQGCgAERKsYGzq03LSEyRTcHAAGTB/f/fY23NwBgyMOYw5hDff/yQAVhgoABESrGBs6JNwkhMkW3NwBgNweAACIFIYHIw5jDmEN9//JABWGCgBfzf/9nAMPNF/N//2cAg81BEQbGl/B//+eAANCyQDM1oAByBUEBgoBdcZFHPsjJRz7KoUc+zJMHAAIqxj7QaACFR4bGLs4C0jLUNtYC2ALaPtwjDvECHSa2QGFhgoAdcabKqoQJZcrIEwUFcS6JgUXOxobOosyyiUk2IeEqhFU1lUc+yKFHPsyTBwACPtBoAIVHJsZOykrOAtIC1ALWAtgC2j7cIw7xAtEs9kAihWZE1kRGSbZJJWGCgDcEABAlBO23eXGTh/Y/JtK2hLO21wDaBqmDtpedZpOGBlNK0FLMXsZixGbCBtYi1E7OVspayLOL1wKqjC6JMoozvNcCYwIHDLPntAA3BAAQvYsNBK3vxT3VJPU9NwQAEDXlXoXihe/wv60qhCnt/UoTC/ADocwTd/kDk3f5DzXnY3mbBhOH9/OTCQAEY3brBtKFSoVOhkUswTteheKF1SQd4ZOWOQDKhWaF/RYBRsE1WS5eheKF7/C/qBHlTppOmbOENEFFvzcEABAlBEk1slAihSJUklQCWfJJYkrSSkJLsksiTJJMRWGCgBN3+QHBSUXzwUnj/pr4k4f38bO3+gCTmUcAwQlpt16F4oXv8F+jKoQ54ZMKABATCwACzdiTefkPs4k6QaaHY3SbAJMHAAJj8zcBvokNO8qFZoWTljkAUoY1NV6F4oXv8J+fEeVOmk6Zs4Q0Qdm3NwQAECUEhb8Zce7Gqo0JZcrYEwUFcS6JgUWm2s7Wht6i3NLU1tLa0N7O4szmyurIsom2hO/wX5st5SqEQUuRSzFMoUqTDAACBU2N4PZQIoVmVNZURlm2WSZalloGW/ZLZkzWTEZNtk0JYYKAJopjc5sAQUqTFzoAaABKzk7YbsZeyGLKVsxm0FbSAtQC1j7aatwjDgECs4REQcEo0plSmW23NwQAECUEVbcTBhACebsTBsANYbtRRYKAGek3BQAQGQWCgDcFABAZBfJABWGCgAERLsYGzirE+T+yRePkpf4iRoFFAUWX8H//54CAlzM1oAByBdm/F/N//2cAA5IBESLMKoQFZRMFhTgGzi7G7/B/nZfwf//ngMD4skUSBbNVtQIihS7GwT+yRSKFl/B//+eA4I5iRPJABWUTBYU4BWFv8F+aF/N//2cA44wX83//ZwCj/hfzf/9nAGP+roeqhT6FF/N//2cAw/0qg4MlQwADJoMAgybDAAMnAwGDJ0MBAyiDAYMowwEDLgMCgy5DAgMvgwKDL8MCtwIAQANDAwODo0IBeXEIQQbWiUIayH7GesR2wnLAY/lyAJfQgv/ngIAdslBFYYKAl7CC/+eAAMDNvzc3AGAcQ72L9f+CgDcFAAKCgLcnAGAjogc0goBBESLEBsY3JwBgk1dWACqEIyD3NBN19QOTBwcwPpWX8H//54DgxLcnAGAjpIc0skAiRAVHI6bnNEEBgoCzZ7UAocMBEUrINykAYCLMJspOxgbOKoSuhBMJiTWJSZM3FAAFRZ2M7/A/iQMnCQB9FLNnlABjCzcF/fM3BQAQJQU1qLcnAGADp4c1iUdjF/cGtycAYAVHI6jnNLcnAGADp4c1jUdjG/cEAUWCgLcnAGADp4c1jUfjEvf8AUXyQGJE0kRCSbJJBWGCgDcnAGCFRiMo1zTh3xMJhzWNSQVF7/C/gYMnCQDjijf9kzcUAJ2MfRSzZ5QA/fNJtzcFABAlBYKAtycAYAVHI6rnNIKAQREixCbCSsATBwUBBsa3BwFgI6znDC6JhUWyhCqEl/B//+eAoNy39wBgfVfYywFGyoUihZfwf//ngMDdkcS39wBgkEtFjpDLBUUzFYUAIkSyQJJEAklBARfzf/9nAAPcN2cJYBMHBxEcQ7cG/f/9FvWPtwYCANWPHMO3Zwlgk4dHFJhDEwUADBNnFwCYw7c3hUA3t3ELI6Dn1hfjf/9nAONktycLYJOHB8OYQ7cGAIA3JgtgVY+Yw7cmC2A3R9hQk4aGwRMHF6qYwiMgBsAjoAYAlEM3BgBA0Y6Uw7cnC2CThwfCmMM3JwtgEwfHwRRDNwYEANGOFMMjoAcAgoAAAA==",
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{esptool-5.3.dev1 → esptool-5.3.dev2}/esptool/targets/stub_flasher/2/esp32c6.json RENAMED Viewed

@@ -1,6 +1,6 @@
 {
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u7/DvqQUE5bdBEQbGzSaqhwVFmeM9LgYFskBBAYKAQREGxoVHYwz1AolHYw31BAllEwUFca0kAUWNLDcWgECTBhAQEwam55VFAUWNLDcVgEATBQUf7/AvmQFFDaC3BYBAk4VFFEVFcSY3FYBAEwWlKe/wb5c3FYBAEwXlKbJAQQFv8C+XeSa3FYBAEUaThSXmRUXNJDcVgEATBeUj7/CvlDcVgEATBWUo0b8ByVxJGElURRBFTEEIQUWmNwUAEBkFgoABEQbOKsYuxLkuokUyRfJABWH5pkERBsYmwiLE8SbNJqqEcSYV7UUuNwQAEKqFBQS3BwABY/e3ALc3hUAFRyOO59RBZpMH9v8TBwAQhWYmhZkmEeEihbJAIkSSREEBgoCqhQFE8bdBESLEBsYqhGEmHEGyQBzAXEFcwBxFHMRcRVzEHEkcyFxJXMgiREEBgoCzZ8UAjYuyhpnrtzeFQIPHx9WJxy6GqoUFRZ2lTaY3BQAQCQWCgLNnxQCNizaHge+3N4VAg8fH1ZHHsoYuhqqFBUXdoZGuNwUAEA0FgoBppgERIswmykrITsYGzqqJLokBRIFEcSYVwQVFzSCTBxQAM7eHALqUPoTj5iT/YxSZAOPiN/83BQAQJQXyQGJE0kRCSbJJBWGCgAERTsaTNxUAk7kVAAbOIswmykrIUsRWwrPp+QBjjgkANwUAEBkF8kBiRNJEQkmySSJKkkoFYYKALoqqioFFMoWlPyqHNwUAECUFcf8DJAoAGeABRcm/QWmDpAoAY2YkAZOXBAHBg4XPk5dEAQVpzfu3N4VAg8fH1Z3HpoUFRWOCCQI5JU3xswckQTM0JAHKlH0UI6CaAH2MIyCKAF2/hUnBv+UjxbcmhWOECQDtLOG/+STRvxfzf/9nAMPv6avxqxN19Q8JrRN19Q8RrRN19Q+RrQERtwcAYCLMwQcTFMUAJsoGzq6Eopd9V7KFmMMBRiaFNsaX8H//54CAW7JGgcq3BwBgsQc+lBxA1Y8cwGJEBUXyQDMVlQDSRAVhF/N//2cAg1k3BwBgkxfFACEHPpcIQzcHAGBBB7qXiMOCgLcHAGDxBzIFPpUIQRN19Q+CgLcHBgA+lTIFCEETdfUPgoAX83//ZwDD5kERBsaX8H//54CA64FHEcWDR4UB9ReTtxcAskA+hUEBgoDRq7f3AGDIR8jLgoC39wBgyEMJgQWJgoC39wBgiEMTdfUPgoABESbKTsaxZLf5AGAizErIBs4qhAFJkQmThAQ1BUXlNYOnCQCJi4HvBQnjGZn+BUXyQGJE0kRCSbJJBWGCgLf3AGCAwwFF7be39wBg2EMTZxcA2MOCgAFFgoCCgAFFgoCCgAFFgoCCgEERBsZFI7JACWUTBQVxQQF5tdmjCaMhozmjgoCCgDcFABAVBYKAgoBBEXVFBsaX8H//54DAQmVFl/B//+eAIEJ5RZfwf//ngIBBskBhRUEBF/N//2cAo0BBEQbGl/B//+eA4OWyQDM1oAByBUEBgoATdfUP8Udj56cAxUdj6qcAAUWCgBMFdfwTNRUAZgWCgIVHM5WnAIKANwUAAYKAAUWCgBfzf/9nAEPpQREGxsU/skCBRUEB9be3B4hAA6XH/oKAQREGxpfwf//ngIDg7TeyQAhBQQGCgEERBsbxP7JAQQEX83//ZwBD3UERBsaBzpfwf//ngODXAcU3BQAQIQWyQEEBgoCX8H//54AA2u23QREGxpfwf//ngGDZAcU3BQAQEQWyQEEBgoBBEQbGl/B//+eAANWyQDM1oAByBUEBgoBBEQbG/SY3NwBgtwYACCMmBwKTB8cCFMMUQ/3+iEOyQAWJQQGCgAERKsYGzq030SYyRTcHAAGTB/f/fY23NwBgyMOYw5hDff/yQAVhgoABESrGBs6JN3EuMkW3NwBgNweAACIFIYHIw5jDmEN9//JABWGCgIKAF/N//2cA48sX83//ZwCjy0ERBsaX8H//54AgzrJAMzWgAHIFQQGCgF1xkUc+yMlHPsqhRz7MkwcAAirGPtBoAIVHhsYuzgLSMtQ21gLYAto+3CMO8QJlN7ZAYWGCgB1xpsqqhAllysgTBQVxLomBRc7Ghs6izLKJjT4h4SqETTWVRz7IoUc+zJMHAAI+0GgAhUcmxk7KSs4C0gLUAtYC2ALaPtwjDvECmT/2QCKFZkTWREZJtkklYYKANwQAECUE7bd5cZOH9j8m0raEs7bXANoGqYO2l51mk4YGU0rQUsxexmLEZsIG1iLUTs5WylrIs4vXAqqMLokyijO81wJjAgcMs+e0ADcEABC9iw0Ere/FPYE79T03BAAQNeVeheKF7/C/rCqEKe39ShML8AOhzBN3+QOTd/kPNedjeZsGE4f385MJAARjdusG0oVKhU6GETv5M16F4oU5Mx3hk5Y5AMqFZoX9FgFGwTURM16F4oXv8L+nEeVOmk6Zs4Q0QUW/NwQAECUESTWyUCKFIlSSVAJZ8kliStJKQkuySyJMkkxFYYKAE3f5AcFJRfPBSeP+mviTh/fxs7f6AJOZRwDBCWm3XoXihe/wX6IqhDnhkwoAEBMLAALN2JN5+Q+ziTpBpodjdJsAkwcAAmPzNwG+iQU7yoVmhZOWOQBShjU1XoXihe/wn54R5U6aTpmzhDRB2bc3BAAQJQSFvxlx7saqjQllytgTBQVxLomBRabaztaG3qLc0tTW0trQ3s7izObK6siyibaE7/Bfmi3lKoRBS5FLMUyhSpMMAAIFTY3g9lAihWZU1lRGWbZZJlqWWgZb9ktmTNZMRk22TQlhgoAmimNzmwBBSpMXOgBoAErOTthuxl7IYspWzGbQVtIC1ALWPtpq3CMOAQKzhERBiTvSmVKZbbc3BAAQJQRVtxMGEAJ5uxMGwA1hu1FFgoAZ6TcFABAZBYKANwUAEBkF8kAFYYKAAREuxgbOKsT5P7JF4+Sl/iJGgUUBRZfwf//ngGCWMzWgAHIF2b8X83//ZwAjkQERIswqhAVlEwWFOAbOLsbv8H+cl/B//+eAIPSyRRIFs1W1AiKFLsbBP7JFIoWX8H//54AAjmJE8kAFZRMFhTgFYW/wX5kX83//ZwADjBfzf/9nAAP5F/N//2cAw/iuh6qFPoUX83//ZwAj+Dc3AGAcQ72L9f8cQ5P3Bw/1+4KAQREixCbCSsAGxrcHAWAjoKcMLomFRbKEKoSX8H//54AA8bf3AGB9V9jLAUbKhSKFl/B//+eA4PGRxLf3AGCQS0WOkMsFRTMVhQAiRLJAkkQCSUEBF/N//2cAI/A3ZwlgEwcHERxDtwb9//0W9Y/BZtWPHMO3d4kJNzeFQJOHB4ATBQAKIyD31hfjf/9nACN9tycLYJOHB8OYQ7cGAIA3JgtgVY+Yw7cmC2A3R9hQk4aGwRMHF6qYwiMgBsAjoAYAlEM3BgBA0Y6Uw7cnC2CThwfCmMM3JwtgEwfHwRRDNwYEANGOFMMjoAcAgoAAAA==",
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esptool 5.3.dev1__tar.gz → 5.3.dev2__tar.gz

esptool 5.3.dev1tar.gz → 5.3.dev2tar.gz