esptool 4.9.dev3__tar.gz → 4.9.dev5__tar.gz

{esptool-4.9.dev3/esptool.egg-info → esptool-4.9.dev5}/PKG-INFO

@@ -1,6 +1,6 @@
-Metadata-Version: 2.1
+Metadata-Version: 2.2
 Name: esptool
-Version: 4.9.dev3
+Version: 4.9.dev5
 Summary: A serial utility to communicate & flash code to Espressif chips.
 Author: Fredrik Ahlberg (themadinventor), Angus Gratton (projectgus), Espressif Systems
 License: GPLv2+

{esptool-4.9.dev3 → esptool-4.9.dev5}/espefuse/efuse/esp32h2/fields.py

@@ -111,6 +111,10 @@ class EspEfuses(base_fields.EspEfusesBase):
                 EfuseField.convert(self, efuse) for efuse in self.Fields.CALC
             ]
 
+        if self.get_chip_version() <= 101:
+            rev = EfuseDefineFields(None, revision="esp32h2_v0.0_v1.1")
+            self.efuses += [EfuseField.convert(self, efuse) for efuse in rev.EFUSES]
+
     def __getitem__(self, efuse_name):
         """Return the efuse field with the given name"""
         for e in self.efuses:
@@ -302,22 +306,9 @@ class EfuseField(base_fields.EfuseFieldBase):
             "keypurpose": EfuseKeyPurposeField,
             "t_sensor": EfuseTempSensor,
             "adc_tp": EfuseAdcPointCalibration,
-            "wafer": EfuseWafer,
         }.get(efuse.class_type, EfuseField)(parent, efuse)
 
 
-class EfuseWafer(EfuseField):
-    def get(self, from_read=True):
-        hi_bits = self.parent["WAFER_VERSION_MINOR_HI"].get(from_read)
-        assert self.parent["WAFER_VERSION_MINOR_HI"].bit_len == 1
-        lo_bits = self.parent["WAFER_VERSION_MINOR_LO"].get(from_read)
-        assert self.parent["WAFER_VERSION_MINOR_LO"].bit_len == 3
-        return (hi_bits << 3) + lo_bits
-
-    def save(self, new_value):
-        raise esptool.FatalError("Burning %s is not supported" % self.name)
-
-
 class EfuseTempSensor(EfuseField):
     def get(self, from_read=True):
         value = self.get_bitstring(from_read)

{esptool-4.9.dev3 → esptool-4.9.dev5}/espefuse/efuse/esp32h2/mem_definition.py

@@ -111,7 +111,7 @@ class EfuseDefineBlocks(EfuseBlocksBase):
 
 
 class EfuseDefineFields(EfuseFieldsBase):
-    def __init__(self, extend_efuse_table) -> None:
+    def __init__(self, extend_efuse_table, revision=None) -> None:
         # List of efuse fields from TRM the chapter eFuse Controller.
         self.EFUSES = []
         self.KEYBLOCKS = []
@@ -120,6 +120,8 @@ class EfuseDefineFields(EfuseFieldsBase):
 
         dir_name = os.path.dirname(os.path.abspath(__file__))
         dir_name, file_name = os.path.split(dir_name)
+        if revision is not None:
+            file_name = revision
         file_name = file_name + ".yaml"
         dir_name, _ = os.path.split(dir_name)
         efuse_file = os.path.join(dir_name, "efuse_defs", file_name)

{esptool-4.9.dev3 → esptool-4.9.dev5}/espefuse/efuse/esp32h2/operations.py

@@ -318,14 +318,16 @@ def burn_key(esp, efuses, args, digest=None):
             if efuses[block.key_purpose_name].is_writeable():
                 disable_wr_protect_key_purpose = True
 
-        if keypurpose == "ECDSA_KEY":
-            if efuses["ECDSA_FORCE_USE_HARDWARE_K"].get() == 0:
-                # For ECDSA key purpose block permanently enable
-                # the hardware TRNG supplied k mode (most secure mode)
-                print("\tECDSA_FORCE_USE_HARDWARE_K: 0 -> 1")
-                efuses["ECDSA_FORCE_USE_HARDWARE_K"].save(1)
-            else:
-                print("\tECDSA_FORCE_USE_HARDWARE_K is already '1'")
+        # >= ESP32-H2 ECO5 revision (v1.2) does not have ECDSA_FORCE_USE_HARDWARE_K
+        if efuses.get_chip_version() <= 101:
+            if keypurpose == "ECDSA_KEY":
+                if efuses["ECDSA_FORCE_USE_HARDWARE_K"].get() == 0:
+                    # For ECDSA key purpose block permanently enable
+                    # the hardware TRNG supplied k mode (most secure mode)
+                    print("\tECDSA_FORCE_USE_HARDWARE_K: 0 -> 1")
+                    efuses["ECDSA_FORCE_USE_HARDWARE_K"].save(1)
+                else:
+                    print("\tECDSA_FORCE_USE_HARDWARE_K is already '1'")
 
         if disable_wr_protect_key_purpose:
             print("\tDisabling write to '%s'." % block.key_purpose_name)

{esptool-4.9.dev3 → esptool-4.9.dev5}/espefuse/efuse_defs/esp32h2.yaml

@@ -1,4 +1,4 @@
-VER_NO: ef562916e77cf77203c1a4c0cff35ac5
+VER_NO: 44563d2af4ebdba4db6c0a34a50c94f9
 EFUSES:
   WR_DIS                           : {show: y, blk : 0, word: 0, pos : 0, len : 32, start  : 0, type : 'uint:32', wr_dis: null, rd_dis: null, alt                            : '', dict             : '', desc: Disable programming of individual eFuses, rloc: EFUSE_RD_WR_DIS_REG, bloc: 'B0,B1,B2,B3'}
   RD_DIS                           : {show: y, blk : 0, word: 1, pos : 0, len  : 7, start : 32, type  : 'uint:7', wr_dis   : 0, rd_dis: null, alt                            : '', dict             : '', desc: Disable reading from BlOCK4-10, rloc: 'EFUSE_RD_REPEAT_DATA0_REG[6:0]', bloc: 'B4[6:0]'}
@@ -18,9 +18,9 @@ EFUSES:
   USB_DREFL                        : {show: n, blk : 0, word: 1, pos: 23, len  : 2, start : 55, type  : 'uint:2', wr_dis  : 30, rd_dis: null, alt                            : '', dict             : '', desc: Represents the single-end input threshold vrefl; 1.76 V to 2 V with step of 80 mV, rloc: 'EFUSE_RD_REPEAT_DATA0_REG[24:23]', bloc: 'B6[7],B7[0]'}
   USB_EXCHG_PINS                   : {show: y, blk : 0, word: 1, pos: 25, len  : 1, start : 57, type      : bool, wr_dis  : 30, rd_dis: null, alt                            : '', dict             : '', desc: 'Represents whether the D+ and D- pins is exchanged. 1: exchanged. 0: not exchanged', rloc: 'EFUSE_RD_REPEAT_DATA0_REG[25]', bloc: 'B7[1]'}
   VDD_SPI_AS_GPIO                  : {show: y, blk : 0, word: 1, pos: 26, len  : 1, start : 58, type      : bool, wr_dis  : 30, rd_dis: null, alt                            : '', dict             : '', desc: 'Represents whether vdd spi pin is functioned as gpio. 1: functioned. 0: not functioned', rloc: 'EFUSE_RD_REPEAT_DATA0_REG[26]', bloc: 'B7[2]'}
-  RPT4_RESERVED0_2                 : {show: n, blk : 0, word: 1, pos: 27, len  : 2, start : 59, type  : 'uint:2', wr_dis: null, rd_dis: null, alt                            : '', dict             : '', desc: Reserved, rloc: 'EFUSE_RD_REPEAT_DATA0_REG[28:27]', bloc: 'B7[4:3]'}
-  RPT4_RESERVED0_1                 : {show: n, blk : 0, word: 1, pos: 29, len  : 1, start : 61, type      : bool, wr_dis: null, rd_dis: null, alt                            : '', dict             : '', desc: Reserved, rloc: 'EFUSE_RD_REPEAT_DATA0_REG[29]', bloc: 'B7[5]'}
-  RPT4_RESERVED0_0                 : {show: n, blk : 0, word: 1, pos: 30, len  : 2, start : 62, type  : 'uint:2', wr_dis: null, rd_dis: null, alt                            : '', dict             : '', desc: Reserved, rloc: 'EFUSE_RD_REPEAT_DATA0_REG[31:30]', bloc: 'B7[7:6]'}
+  ECDSA_CURVE_MODE                 : {show: y, blk : 0, word: 1, pos: 27, len  : 2, start : 59, type  : 'uint:2', wr_dis  : 17, rd_dis: null, alt                            : '', dict             : '', desc: 'Configures the curve of ECDSA calculation: 0: only enable P256. 1: only enable P192. 2: both enable P256 and P192. 3: only enable P256', rloc: 'EFUSE_RD_REPEAT_DATA0_REG[28:27]', bloc: 'B7[4:3]'}
+  ECC_FORCE_CONST_TIME             : {show: y, blk : 0, word: 1, pos: 29, len  : 1, start : 61, type      : bool, wr_dis  : 17, rd_dis: null, alt                            : '', dict             : '', desc: Set this bit to permanently turn on ECC const-time mode, rloc: 'EFUSE_RD_REPEAT_DATA0_REG[29]', bloc: 'B7[5]'}
+  XTS_DPA_PSEUDO_LEVEL             : {show: y, blk : 0, word: 1, pos: 30, len  : 2, start : 62, type  : 'uint:2', wr_dis  : 14, rd_dis: null, alt                            : '', dict             : '', desc: 'Set this bit to control the xts pseudo-round anti-dpa attack function: 0: controlled by register. 1-3: the higher the value is; the more pseudo-rounds are inserted to the xts-aes calculation', rloc: 'EFUSE_RD_REPEAT_DATA0_REG[31:30]', bloc: 'B7[7:6]'}
   RPT4_RESERVED1_1                 : {show: n, blk : 0, word: 2, pos : 0, len : 16, start : 64, type : 'uint:16', wr_dis: null, rd_dis: null, alt                            : '', dict             : '', desc: Reserved, rloc: 'EFUSE_RD_REPEAT_DATA1_REG[15:0]', bloc: 'B8,B9'}
   WDT_DELAY_SEL                    : {show: y, blk : 0, word: 2, pos: 16, len  : 2, start : 80, type  : 'uint:2', wr_dis   : 3, rd_dis: null, alt                            : '', dict             : '', desc: 'Represents whether RTC watchdog timeout threshold is selected at startup. 1: selected. 0: not selected', rloc: 'EFUSE_RD_REPEAT_DATA1_REG[17:16]', bloc: 'B10[1:0]'}
   SPI_BOOT_CRYPT_CNT               : {show: y, blk : 0, word: 2, pos: 18, len  : 3, start : 82, type  : 'uint:3', wr_dis   : 4, rd_dis: null, alt                            : '', dict: '{0: "Disable", 1: "Enable", 3: "Disable", 7: "Enable"}', desc: Enables flash encryption when 1 or 3 bits are set and disables otherwise, rloc: 'EFUSE_RD_REPEAT_DATA1_REG[20:18]', bloc: 'B10[4:2]'}
@@ -34,11 +34,12 @@ EFUSES:
   KEY_PURPOSE_4                    : {show: y, blk : 0, word: 3, pos : 8, len  : 4, start: 104, type  : 'uint:4', wr_dis  : 12, rd_dis: null, alt                  : KEY4_PURPOSE, dict             : '', desc: Represents the purpose of Key4, rloc: 'EFUSE_RD_REPEAT_DATA2_REG[11:8]', bloc: 'B13[3:0]'}
   KEY_PURPOSE_5                    : {show: y, blk : 0, word: 3, pos: 12, len  : 4, start: 108, type  : 'uint:4', wr_dis  : 13, rd_dis: null, alt                  : KEY5_PURPOSE, dict             : '', desc: Represents the purpose of Key5, rloc: 'EFUSE_RD_REPEAT_DATA2_REG[15:12]', bloc: 'B13[7:4]'}
   SEC_DPA_LEVEL                    : {show: y, blk : 0, word: 3, pos: 16, len  : 2, start: 112, type  : 'uint:2', wr_dis  : 14, rd_dis: null, alt                            : '', dict             : '', desc: Represents the spa secure level by configuring the clock random divide mode, rloc: 'EFUSE_RD_REPEAT_DATA2_REG[17:16]', bloc: 'B14[1:0]'}
-  ECDSA_FORCE_USE_HARDWARE_K       : {show: y, blk : 0, word: 3, pos: 18, len  : 1, start: 114, type      : bool, wr_dis  : 17, rd_dis: null, alt                            : '', dict             : '', desc: 'Represents whether hardware random number k is forced used in ESDCA. 1: force used. 0: not force used', rloc: 'EFUSE_RD_REPEAT_DATA2_REG[18]', bloc: 'B14[2]'}
+  RESERVE_0_114                    : {show: n, blk : 0, word: 3, pos: 18, len  : 1, start: 114, type      : bool, wr_dis  : 17, rd_dis: null, alt                            : '', dict             : '', desc: Reserved, rloc: 'EFUSE_RD_REPEAT_DATA2_REG[18]', bloc: 'B14[2]'}
   CRYPT_DPA_ENABLE                 : {show: y, blk : 0, word: 3, pos: 19, len  : 1, start: 115, type      : bool, wr_dis  : 14, rd_dis: null, alt                            : '', dict             : '', desc: 'Represents whether anti-dpa attack is enabled. 1:enabled. 0: disabled', rloc: 'EFUSE_RD_REPEAT_DATA2_REG[19]', bloc: 'B14[3]'}
   SECURE_BOOT_EN                   : {show: y, blk : 0, word: 3, pos: 20, len  : 1, start: 116, type      : bool, wr_dis  : 15, rd_dis: null, alt                            : '', dict             : '', desc: 'Represents whether secure boot is enabled or disabled. 1: enabled. 0: disabled', rloc: 'EFUSE_RD_REPEAT_DATA2_REG[20]', bloc: 'B14[4]'}
   SECURE_BOOT_AGGRESSIVE_REVOKE    : {show: y, blk : 0, word: 3, pos: 21, len  : 1, start: 117, type      : bool, wr_dis  : 16, rd_dis: null, alt                            : '', dict             : '', desc: 'Represents whether revoking aggressive secure boot is enabled or disabled. 1: enabled. 0: disabled', rloc: 'EFUSE_RD_REPEAT_DATA2_REG[21]', bloc: 'B14[5]'}
-  RPT4_RESERVED2_0                 : {show: n, blk : 0, word: 3, pos: 22, len  : 6, start: 118, type  : 'uint:6', wr_dis: null, rd_dis: null, alt                            : '', dict             : '', desc: Reserved, rloc: 'EFUSE_RD_REPEAT_DATA2_REG[27:22]', bloc: 'B14[7:6],B15[3:0]'}
+  POWERGLITCH_EN1                  : {show: y, blk : 0, word: 3, pos: 22, len  : 5, start: 118, type  : 'uint:5', wr_dis   : 2, rd_dis: null, alt                            : '', dict             : '', desc: Set these bits to enable power glitch function when chip power on, rloc: 'EFUSE_RD_REPEAT_DATA2_REG[26:22]', bloc: 'B14[7:6],B15[2:0]'}
+  RESERVED_0_123                   : {show: n, blk : 0, word: 3, pos: 27, len  : 1, start: 123, type      : bool, wr_dis: null, rd_dis: null, alt                            : '', dict             : '', desc: reserved, rloc: 'EFUSE_RD_REPEAT_DATA2_REG[27]', bloc: 'B15[3]'}
   FLASH_TPUW                       : {show: y, blk : 0, word: 3, pos: 28, len  : 4, start: 124, type  : 'uint:4', wr_dis  : 18, rd_dis: null, alt                            : '', dict             : '', desc: Represents the flash waiting time after power-up; in unit of ms. When the value less than 15; the waiting time is the programmed value. Otherwise; the waiting time is 2 times the programmed value, rloc: 'EFUSE_RD_REPEAT_DATA2_REG[31:28]', bloc: 'B15[7:4]'}
   DIS_DOWNLOAD_MODE                : {show: y, blk : 0, word: 4, pos : 0, len  : 1, start: 128, type      : bool, wr_dis  : 18, rd_dis: null, alt                            : '', dict             : '', desc: 'Represents whether Download mode is disabled or enabled. 1: disabled. 0: enabled', rloc: 'EFUSE_RD_REPEAT_DATA3_REG[0]', bloc: 'B16[0]'}
   DIS_DIRECT_BOOT                  : {show: y, blk : 0, word: 4, pos : 1, len  : 1, start: 129, type      : bool, wr_dis  : 18, rd_dis: null, alt                            : '', dict             : '', desc: 'Represents whether direct boot mode is disabled or enabled. 1: disabled. 0: enabled', rloc: 'EFUSE_RD_REPEAT_DATA3_REG[1]', bloc: 'B16[1]'}

esptool-4.9.dev5/espefuse/efuse_defs/esp32h2_v0.0_v1.1.yaml

@@ -0,0 +1,3 @@
+VER_NO: 44563d2af4ebdba4db6c0a34a50c94f9
+EFUSES:
+  ECDSA_FORCE_USE_HARDWARE_K       : {show: y, blk : 0, word: 3, pos: 18, len  : 1, start: 114, type      : bool, wr_dis  : 17, rd_dis: null, alt                            : '', dict             : '', desc: 'Represents whether hardware random number k is forced used in ESDCA. 1: force used. 0: not force used', rloc: 'EFUSE_RD_REPEAT_DATA2_REG[18]', bloc: 'B14[2]'}

{esptool-4.9.dev3 → esptool-4.9.dev5}/espsecure/__init__.py

@@ -65,7 +65,7 @@ def swap_word_order(source):
     return struct.pack(words, *reversed(struct.unpack(words, source)))
 
 
-def _load_hardware_key(keyfile):
+def _load_hardware_key(keyfile, is_flash_encryption_key, aes_xts=None):
     """Load a 128/256/512-bit key, similar to stored in efuse, from a file
 
     128-bit keys will be extended to 256-bit using the SHA256 of the key
@@ -78,6 +78,17 @@ def _load_hardware_key(keyfile):
             "Key file contains wrong length (%d bytes), 16, 24, 32 or 64 expected."
             % len(key)
         )
+    if is_flash_encryption_key:
+        if aes_xts:
+            if len(key) not in [16, 32, 64]:
+                raise esptool.FatalError(
+                    f"AES_XTS supports only 128, 256, and 512-bit keys. Provided key is {len(key) * 8} bits."
+                )
+        else:
+            if len(key) not in [24, 32]:
+                raise esptool.FatalError(
+                    f"ESP32 supports only 192 and 256-bit keys. Provided key is {len(key) * 8} bits. Use --aes_xts for other chips."
+                )
     if len(key) == 16:
         key = _sha256_digest(key)
         print("Using 128-bit key (extended)")
@@ -129,7 +140,7 @@ def digest_secure_bootloader(args):
     # produce the digest. Each block in/out of ECB is reordered
     # (due to hardware quirks not for security.)
 
-    key = _load_hardware_key(args.keyfile)
+    key = _load_hardware_key(args.keyfile, False)
     backend = default_backend()
     cipher = Cipher(algorithms.AES(key), modes.ECB(), backend=backend)
     encryptor = cipher.encryptor()
@@ -1233,7 +1244,19 @@ def generate_flash_encryption_key(args):
 def _flash_encryption_operation_esp32(
     output_file, input_file, flash_address, keyfile, flash_crypt_conf, do_decrypt
 ):
-    key = _load_hardware_key(keyfile)
+    """
+    Perform flash encryption or decryption operation for ESP32.
+
+    This function handles the encryption or decryption of flash data for the ESP32 chip.
+    It reads data from the input file, processes it in 16-byte blocks, and writes the
+    processed data to the output file. The function ensures that the key length is either
+    192 or 256 bits, as required by the ESP32 chip. It also checks that the flash address
+    is a multiple of 16.
+
+    Note: This function is specific to the ESP32 chip. For other chips, use the --aes_xts
+    flag to call the correct function.
+    """
+    key = _load_hardware_key(keyfile, True, aes_xts=False)
 
     if flash_address % 16 != 0:
         raise esptool.FatalError(
@@ -1322,7 +1345,7 @@ def _flash_encryption_operation_aes_xts(
     """
 
     backend = default_backend()
-    key = _load_hardware_key(keyfile)
+    key = _load_hardware_key(keyfile, True, aes_xts=True)
     indata = input_file.read()
 
     if flash_address % 16 != 0:
@@ -1789,8 +1812,7 @@ def main(custom_commandline=None):
     p.add_argument(
         "--aes_xts",
         "-x",
-        help="Decrypt data using AES-XTS as used on "
-        "ESP32-S2, ESP32-C2, ESP32-C3, ESP32-C6, ESP32-C5, ESP32-C61 and ESP32-P4",
+        help="Decrypt data using AES-XTS (not applicable for ESP32)",
         action="store_true",
     )
     p.add_argument(
@@ -1816,7 +1838,7 @@ def main(custom_commandline=None):
     )
     p.add_argument(
         "--flash_crypt_conf",
-        help="Override FLASH_CRYPT_CONF efuse value (default is 0XF).",
+        help="Override FLASH_CRYPT_CONF efuse value (default is 0XF) (applicable only for ESP32).",
         required=False,
         default=0xF,
         type=esptool.arg_auto_int,
@@ -1829,8 +1851,7 @@ def main(custom_commandline=None):
     p.add_argument(
         "--aes_xts",
         "-x",
-        help="Encrypt data using AES-XTS as used on "
-        "ESP32-S2, ESP32-C2, ESP32-C3, ESP32-C6, ESP32-C5, ESP32-C61 and ESP32-P4",
+        help="Encrypt data using AES-XTS (not applicable for ESP32)",
         action="store_true",
     )
     p.add_argument(
@@ -1856,7 +1877,7 @@ def main(custom_commandline=None):
     )
     p.add_argument(
         "--flash_crypt_conf",
-        help="Override FLASH_CRYPT_CONF efuse value (default is 0XF).",
+        help="Override FLASH_CRYPT_CONF efuse value (default is 0XF) (applicable only for ESP32)",
         required=False,
         default=0xF,
         type=esptool.arg_auto_int,

{esptool-4.9.dev3 → esptool-4.9.dev5}/esptool/__init__.py

@@ -29,7 +29,7 @@ __all__ = [
     "write_mem",
 ]
 
-__version__ = "4.9.dev3"
+__version__ = "4.9.dev5"
 
 import argparse
 import inspect
@@ -151,7 +151,13 @@ def main(argv=None, esp=None):
         "--after",
         "-a",
         help="What to do after esptool.py is finished",
-        choices=["hard_reset", "soft_reset", "no_reset", "no_reset_stub"],
+        choices=[
+            "hard_reset",
+            "soft_reset",
+            "no_reset",
+            "no_reset_stub",
+            "watchdog_reset",
+        ],
         default=os.environ.get("ESPTOOL_AFTER", "hard_reset"),
     )
 
@@ -823,11 +829,14 @@ def main(argv=None, esp=None):
             )
 
         if esp.secure_download_mode:
-            print("Chip is %s in Secure Download Mode" % esp.CHIP_NAME)
+            print(f"Chip is {esp.CHIP_NAME} in Secure Download Mode")
         else:
-            print("Chip is %s" % (esp.get_chip_description()))
-            print("Features: %s" % ", ".join(esp.get_chip_features()))
-            print("Crystal is %dMHz" % esp.get_crystal_freq())
+            print(f"Chip is {esp.get_chip_description()}")
+            print(f"Features: {', '.join(esp.get_chip_features())}")
+            print(f"Crystal is {esp.get_crystal_freq()}MHz")
+            usb_mode = esp.get_usb_mode()
+            if usb_mode is not None:
+                print(f"USB mode: {usb_mode}")
             read_mac(esp, args)
 
         if not args.no_stub:
@@ -1065,6 +1074,15 @@ def main(argv=None, esp=None):
             esp.soft_reset(False)
         elif args.after == "no_reset_stub":
             print("Staying in flasher stub.")
+        elif args.after == "watchdog_reset":
+            if esp.secure_download_mode:
+                print(
+                    "WARNING: Watchdog hard reset is not supported in Secure Download "
+                    "Mode, attempting classic hard reset instead."
+                )
+                esp.hard_reset()
+            else:
+                esp.watchdog_reset()
         else:  # args.after == 'no_reset'
             print("Staying in bootloader.")
             if esp.IS_STUB:

{esptool-4.9.dev3 → esptool-4.9.dev5}/esptool/cmds.py

@@ -495,7 +495,7 @@ def write_flash(esp, args):
     else:  # Check against real flash chip size if not in SDM
         flash_end_str = detect_flash_size(esp)
         flash_end = flash_size_bytes(flash_end_str)
-        if set_flash_size and set_flash_size > flash_end:
+        if set_flash_size and flash_end and set_flash_size > flash_end:
             print(
                 f"WARNING: Set --flash_size {args.flash_size} "
                 f"is larger than the available flash size of {flash_end_str}."

{esptool-4.9.dev3 → esptool-4.9.dev5}/esptool/loader.py

@@ -737,7 +737,7 @@ class ESPLoader(object):
                     " if ESP32-C2 doesn't connect"
                     " (at least 115200 Bd is recommended)."
                 )
-
+            self._port.close()
             raise FatalError(
                 "Failed to connect to {}: {}"
                 f"{additional_msg}"
@@ -1047,9 +1047,34 @@ class ESPLoader(object):
         """
         Read the UARTDEV_BUF_NO register to get the number of the currently used console
         """
-        if self.cache["uart_no"] is None:
-            self.cache["uart_no"] = self.read_reg(self.UARTDEV_BUF_NO) & 0xFF
-        return self.cache["uart_no"]
+        # Some ESP chips do not have this register
+        try:
+            if self.cache["uart_no"] is None:
+                self.cache["uart_no"] = self.read_reg(self.UARTDEV_BUF_NO) & 0xFF
+            return self.cache["uart_no"]
+        except AttributeError:
+            return None
+
+    def uses_usb_jtag_serial(self):
+        """
+        Check if the chip uses USB JTAG/SERIAL mode.
+        """
+        return False
+
+    def uses_usb_otg(self):
+        """
+        Check if the chip uses USB OTG mode.
+        """
+        return False
+
+    def get_usb_mode(self):
+        """
+        Get the USB mode of the chip: USB-Serial/JTAG or USB-OTG. If the usb_mode is None, external USB-UART is used.
+        """
+        usb_jtag_serial = self.uses_usb_jtag_serial()
+        usb_otg = self.uses_usb_otg()
+
+        return "USB-Serial/JTAG" if usb_jtag_serial else "USB-OTG" if usb_otg else None
 
     @classmethod
     def parse_flash_size_arg(cls, arg):
@@ -1581,6 +1606,13 @@ class ESPLoader(object):
                 # in the stub loader
                 self.command(self.ESP_RUN_USER_CODE, wait_response=False)
 
+    def watchdog_reset(self):
+        print(
+            f"WARNING: Watchdog hard reset is not supported on {self.CHIP_NAME}, "
+            "attempting classic hard reset instead."
+        )
+        self.hard_reset()
+
 
 def slip_reader(port, trace_function):
     """Generator to read SLIP packets from a serial port.

{esptool-4.9.dev3 → esptool-4.9.dev5}/esptool/targets/esp32c2.py

@@ -133,9 +133,6 @@ class ESP32C2ROM(ESP32C3ROM):
             self.stub_is_disabled = True
             self.IS_STUB = False
 
-    def hard_reset(self):
-        ESPLoader.hard_reset(self)
-
     """ Try to read (encryption key) and check if it is valid """
 
     def is_flash_encryption_key_valid(self):

{esptool-4.9.dev3 → esptool-4.9.dev5}/esptool/targets/esp32c3.py

@@ -253,21 +253,15 @@ class ESP32C3ROM(ESP32ROM):
         if not self.sync_stub_detected:  # Don't run if stub is reused
             self.disable_watchdogs()
 
-    def hard_reset(self):
-        if self.uses_usb_jtag_serial():
-            self.rtc_wdt_reset()
-            sleep(0.5)  # wait for reset to take effect
-        else:
-            ESPLoader.hard_reset(self)
-
-    def rtc_wdt_reset(self):
-        print("Hard resetting with RTC WDT...")
+    def watchdog_reset(self):
+        print("Hard resetting with a watchdog...")
         self.write_reg(self.RTC_CNTL_WDTWPROTECT_REG, self.RTC_CNTL_WDT_WKEY)  # unlock
         self.write_reg(self.RTC_CNTL_WDTCONFIG1_REG, 2000)  # set WDT timeout
         self.write_reg(
             self.RTC_CNTL_WDTCONFIG0_REG, (1 << 31) | (5 << 28) | (1 << 8) | 2
         )  # enable WDT
         self.write_reg(self.RTC_CNTL_WDTWPROTECT_REG, 0)  # lock
+        sleep(0.5)  # wait for reset to take effect
 
     def check_spi_connection(self, spi_connection):
         if not set(spi_connection).issubset(set(range(0, 22))):

{esptool-4.9.dev3 → esptool-4.9.dev5}/esptool/targets/esp32c5.py

@@ -6,6 +6,7 @@ import struct
 import time
 from typing import Dict
 
+from .esp32c3 import ESP32C3ROM
 from .esp32c6 import ESP32C6ROM
 from ..loader import ESPLoader
 from ..util import FatalError
@@ -162,6 +163,10 @@ class ESP32C5ROM(ESP32C6ROM):
                 "consider using other pins for SPI flash connection."
             )
 
+    def watchdog_reset(self):
+        # Watchdog reset disabled in parent (ESP32-C6) ROM, re-enable it
+        ESP32C3ROM.watchdog_reset(self)
+
 
 class ESP32C5StubLoader(ESP32C5ROM):
     """Access class for ESP32C5 stub loader, runs on top of ROM.

{esptool-4.9.dev3 → esptool-4.9.dev5}/esptool/targets/esp32c6.py

@@ -192,10 +192,10 @@ class ESP32C6ROM(ESP32C3ROM):
                 "consider using other pins for SPI flash connection."
             )
 
-    def hard_reset(self):
+    def watchdog_reset(self):
         # Bug in the USB-Serial/JTAG controller can cause the port to disappear
-        # if the chip is reset with RTC WDT, do a classic reset
-        ESPLoader.hard_reset(self)
+        # if watchdog reset happens, disable it on ESP32-C6
+        ESPLoader.watchdog_reset(self)
 
 
 class ESP32C6StubLoader(ESP32C6ROM):

{esptool-4.9.dev3 → esptool-4.9.dev5}/esptool/targets/esp32c61.py

@@ -5,6 +5,7 @@
 import struct
 from typing import Dict
 
+from .esp32c3 import ESP32C3ROM
 from .esp32c6 import ESP32C6ROM
 
 
@@ -118,6 +119,10 @@ class ESP32C61ROM(ESP32C6ROM):
         }
         return macs.get(mac_type, None)
 
+    def watchdog_reset(self):
+        # Watchdog reset disabled in parent (ESP32-C6) ROM, re-enable it
+        ESP32C3ROM.watchdog_reset(self)
+
 
 class ESP32C61StubLoader(ESP32C61ROM):
     """Access class for ESP32C61 stub loader, runs on top of ROM.

{esptool-4.9.dev3 → esptool-4.9.dev5}/esptool/targets/esp32h2.py

@@ -24,6 +24,9 @@ class ESP32H2ROM(ESP32C6ROM):
     RTC_CNTL_SWD_WPROTECT_REG = DR_REG_LP_WDT_BASE + 0x0024  # LP_WDT_SWD_WPROTECT_REG
     RTC_CNTL_SWD_WKEY = 0x50D83AA1  # LP_WDT_SWD_WKEY, same as WDT key in this case
 
+    UARTDEV_BUF_NO = 0x4084FEFC  # Variable in ROM .bss which indicates the port in use
+    UARTDEV_BUF_NO_USB_JTAG_SERIAL = 3  # The above var when USB-JTAG/Serial is used
+
     FLASH_FREQUENCY = {
         "48m": 0xF,
         "24m": 0x0,
@@ -76,9 +79,9 @@ class ESP32H2ROM(ESP32C6ROM):
         # ESP32H2 XTAL is fixed to 32MHz
         return 32
 
-    def hard_reset(self):
-        # RTC WDT reset not available, do a classic reset
-        ESPLoader.hard_reset(self)
+    # Watchdog reset is not supported on ESP32-H2
+    def watchdog_reset(self):
+        ESPLoader.watchdog_reset(self)
 
     def check_spi_connection(self, spi_connection):
         if not set(spi_connection).issubset(set(range(0, 28))):

{esptool-4.9.dev3 → esptool-4.9.dev5}/esptool/targets/esp32h21.py

@@ -5,7 +5,6 @@
 
 
 from .esp32h2 import ESP32H2ROM
-from ..loader import ESPLoader
 from ..util import FatalError
 
 
@@ -46,10 +45,6 @@ class ESP32H21ROM(ESP32H2ROM):
         # ESP32H21 XTAL is fixed to 32MHz
         return 32
 
-    def hard_reset(self):
-        # RTC WDT reset not available, do a classic reset
-        ESPLoader.hard_reset(self)
-
     def check_spi_connection(self, spi_connection):
         if not set(spi_connection).issubset(set(range(0, 28))):
             raise FatalError("SPI Pin numbers must be in the range 0-27.")

{esptool-4.9.dev3 → esptool-4.9.dev5}/esptool/targets/esp32p4.py

@@ -262,19 +262,19 @@ class ESP32P4ROM(ESP32ROM):
                 "consider using other pins for SPI flash connection."
             )
 
-    def rtc_wdt_reset(self):
-        print("Hard resetting with RTC WDT...")
+    def watchdog_reset(self):
+        print("Hard resetting with a watchdog...")
         self.write_reg(self.RTC_CNTL_WDTWPROTECT_REG, self.RTC_CNTL_WDT_WKEY)  # unlock
         self.write_reg(self.RTC_CNTL_WDTCONFIG1_REG, 2000)  # set WDT timeout
         self.write_reg(
             self.RTC_CNTL_WDTCONFIG0_REG, (1 << 31) | (5 << 28) | (1 << 8) | 2
         )  # enable WDT
         self.write_reg(self.RTC_CNTL_WDTWPROTECT_REG, 0)  # lock
+        sleep(0.5)  # wait for reset to take effect
 
     def hard_reset(self):
-        if self.uses_usb_jtag_serial() or self.uses_usb_otg():
-            self.rtc_wdt_reset()
-            sleep(0.5)  # wait for reset to take effect
+        if self.uses_usb_otg():
+            self.watchdog_reset()
         else:
             ESPLoader.hard_reset(self)
 

{esptool-4.9.dev3 → esptool-4.9.dev5}/esptool/targets/esp32s2.py

@@ -288,27 +288,27 @@ class ESP32S2ROM(ESP32ROM):
         if self.uses_usb_otg():
             self.ESP_RAM_BLOCK = self.USB_RAM_BLOCK
 
-    def rtc_wdt_reset(self):
-        print("Hard resetting with RTC WDT...")
+    def watchdog_reset(self):
+        print("Hard resetting with a watchdog...")
         self.write_reg(self.RTC_CNTL_WDTWPROTECT_REG, self.RTC_CNTL_WDT_WKEY)  # unlock
         self.write_reg(self.RTC_CNTL_WDTCONFIG1_REG, 2000)  # set WDT timeout
         self.write_reg(
             self.RTC_CNTL_WDTCONFIG0_REG, (1 << 31) | (5 << 28) | (1 << 8) | 2
         )  # enable WDT
         self.write_reg(self.RTC_CNTL_WDTWPROTECT_REG, 0)  # lock
+        sleep(0.5)  # wait for reset to take effect
 
     def hard_reset(self):
         uses_usb_otg = self.uses_usb_otg()
         if uses_usb_otg:
-            # Check the strapping register to see if we can perform RTC WDT reset
+            # Check the strapping register to see if we can perform a watchdog reset
             strap_reg = self.read_reg(self.GPIO_STRAP_REG)
             force_dl_reg = self.read_reg(self.RTC_CNTL_OPTION1_REG)
             if (
                 strap_reg & self.GPIO_STRAP_SPI_BOOT_MASK == 0  # GPIO0 low
                 and force_dl_reg & self.RTC_CNTL_FORCE_DOWNLOAD_BOOT_MASK == 0
             ):
-                self.rtc_wdt_reset()
-                sleep(0.5)  # wait for reset to take effect
+                self.watchdog_reset()
                 return
 
         ESPLoader.hard_reset(self, uses_usb_otg)

{esptool-4.9.dev3 → esptool-4.9.dev5}/esptool/targets/esp32s3.py

@@ -352,14 +352,15 @@ class ESP32S3ROM(ESP32ROM):
         if not self.sync_stub_detected:  # Don't run if stub is reused
             self.disable_watchdogs()
 
-    def rtc_wdt_reset(self):
-        print("Hard resetting with RTC WDT...")
+    def watchdog_reset(self):
+        print("Hard resetting with a watchdog...")
         self.write_reg(self.RTC_CNTL_WDTWPROTECT_REG, self.RTC_CNTL_WDT_WKEY)  # unlock
         self.write_reg(self.RTC_CNTL_WDTCONFIG1_REG, 2000)  # set WDT timeout
         self.write_reg(
             self.RTC_CNTL_WDTCONFIG0_REG, (1 << 31) | (5 << 28) | (1 << 8) | 2
         )  # enable WDT
         self.write_reg(self.RTC_CNTL_WDTWPROTECT_REG, 0)  # lock
+        sleep(0.5)  # wait for reset to take effect
 
     def hard_reset(self):
         try:
@@ -372,16 +373,15 @@ class ESP32S3ROM(ESP32ROM):
             # Skip if response was not valid and proceed to reset; e.g. when monitoring while resetting
             pass
         uses_usb_otg = self.uses_usb_otg()
-        if uses_usb_otg or self.uses_usb_jtag_serial():
-            # Check the strapping register to see if we can perform RTC WDT reset
+        if uses_usb_otg:
+            # Check the strapping register to see if we can perform a watchdog reset
             strap_reg = self.read_reg(self.GPIO_STRAP_REG)
             force_dl_reg = self.read_reg(self.RTC_CNTL_OPTION1_REG)
             if (
                 strap_reg & self.GPIO_STRAP_SPI_BOOT_MASK == 0  # GPIO0 low
                 and force_dl_reg & self.RTC_CNTL_FORCE_DOWNLOAD_BOOT_MASK == 0
             ):
-                self.rtc_wdt_reset()
-                sleep(0.5)  # wait for reset to take effect
+                self.watchdog_reset()
                 return
 
         ESPLoader.hard_reset(self, uses_usb_otg)

{esptool-4.9.dev3 → esptool-4.9.dev5/esptool.egg-info}/PKG-INFO

@@ -1,6 +1,6 @@
-Metadata-Version: 2.1
+Metadata-Version: 2.2
 Name: esptool
-Version: 4.9.dev3
+Version: 4.9.dev5
 Summary: A serial utility to communicate & flash code to Espressif chips.
 Author: Fredrik Ahlberg (themadinventor), Angus Gratton (projectgus), Espressif Systems
 License: GPLv2+

{esptool-4.9.dev3 → esptool-4.9.dev5}/esptool.egg-info/SOURCES.txt

@@ -99,6 +99,7 @@ espefuse/efuse_defs/esp32c6.yaml
 espefuse/efuse_defs/esp32c61.yaml
 espefuse/efuse_defs/esp32h2.yaml
 espefuse/efuse_defs/esp32h21.yaml
+espefuse/efuse_defs/esp32h2_v0.0_v1.1.yaml
 espefuse/efuse_defs/esp32p4.yaml
 espefuse/efuse_defs/esp32s2.yaml
 espefuse/efuse_defs/esp32s3.yaml