digsim-logic-simulator 0.9.0__tar.gz → 0.11.0__tar.gz

{digsim_logic_simulator-0.9.0/src/digsim_logic_simulator.egg-info → digsim_logic_simulator-0.11.0}/PKG-INFO

@@ -1,6 +1,6 @@
 Metadata-Version: 2.4
 Name: digsim-logic-simulator
-Version: 0.9.0
+Version: 0.11.0
 Summary: Interactive Digital Logic Simulator
 Author-email: Fredrik Andersson <freand@gmail.com>
 Maintainer-email: Fredrik Andersson <freand@gmail.com>

{digsim_logic_simulator-0.9.0 → digsim_logic_simulator-0.11.0}/pyproject.toml

@@ -5,7 +5,7 @@ build-backend = "setuptools.build_meta"
 [project]
 name = "digsim-logic-simulator"
 description = "Interactive Digital Logic Simulator"
-version = "0.9.0"
+version = "0.11.0"
 authors = [{name = "Fredrik Andersson", email = "freand@gmail.com"}]
 maintainers =  [{name = "Fredrik Andersson", email = "freand@gmail.com"}]
 readme = "README.md"

{digsim_logic_simulator-0.9.0 → digsim_logic_simulator-0.11.0}/src/digsim/app/model/_model_settings.py

@@ -27,7 +27,7 @@ class ModelSettings:
 
     def from_dict(self, circuit_dict):
         """Get settings from circuit dict"""
-        for key, data in circuit_dict.get("settings", {}).items():
+        for key, data in circuit_dict.items():
             self._settings[key] = data
 
     def get(self, key):

{digsim_logic_simulator-0.9.0 → digsim_logic_simulator-0.11.0}/src/digsim/app/model/_model_shortcuts.py

@@ -77,10 +77,9 @@ class ModelShortcuts:
             shortcuts_dict[key] = component.name()
         return shortcuts_dict
 
-    def from_dict(self, model_dict):
+    def from_dict(self, shortcuts_dict):
         """Generate shortcuts from dict"""
         self.clear()
-        shortcuts_dict = model_dict.get("shortcuts")
         if shortcuts_dict is not None:
             for key, component_name in shortcuts_dict.items():
                 component = self._app_model.objects.circuit.get_component(component_name)

{digsim_logic_simulator-0.9.0 → digsim_logic_simulator-0.11.0}/src/digsim/utils/_yosys_netlist.py

@@ -88,11 +88,16 @@ class YosysModule:
 
     def is_same_interface(self, netlist):
         is_same = True
-        for netlist_port_name, netlist_port in netlist.ports.items():
-            module_port = self.ports.get(netlist_port_name)
-            if module_port is None or not module_port.is_same(netlist_port):
-                is_same = False
-                break
+        if len(netlist.ports) == len(self.ports):
+            for netlist_port_name, netlist_port in netlist.ports.items():
+                module_port = self.ports.get(netlist_port_name)
+                if module_port is None or not module_port.is_same(netlist_port):
+                    # Port does not exist or has a different bitwidth
+                    is_same = False
+                    break
+        else:
+            # The number of ports does not match
+            is_same = False
         return is_same
 
     def get_nets(self):

{digsim_logic_simulator-0.9.0 → digsim_logic_simulator-0.11.0/src/digsim_logic_simulator.egg-info}/PKG-INFO

@@ -1,6 +1,6 @@
 Metadata-Version: 2.4
 Name: digsim-logic-simulator
-Version: 0.9.0
+Version: 0.11.0
 Summary: Interactive Digital Logic Simulator
 Author-email: Fredrik Andersson <freand@gmail.com>
 Maintainer-email: Fredrik Andersson <freand@gmail.com>

{digsim_logic_simulator-0.9.0 → digsim_logic_simulator-0.11.0}/tests/test_yosys_netlist.py

@@ -61,6 +61,33 @@ netlist_dict_if_four = {
     }
 }
 
+netlist_dict_if_2outports = {
+    "modules": {
+        "counter": {
+            "ports": {
+                "in_port": {"direction": "input", "bits": [2, 3, 4, 5]},
+                "out_port_a": {"direction": "output", "bits": [2, 3, 4, 5]},
+                "out_port_b": {"direction": "output", "bits": [2, 3, 4, 5]},
+            },
+            "cells": {},
+        }
+    }
+}
+
+netlist_dict_if_3outports = {
+    "modules": {
+        "counter": {
+            "ports": {
+                "in_port": {"direction": "input", "bits": [2, 3, 4, 5]},
+                "out_port_a": {"direction": "output", "bits": [2, 3, 4, 5]},
+                "out_port_b": {"direction": "output", "bits": [2, 3, 4, 5]},
+                "out_port_c": {"direction": "output", "bits": [2, 3, 4, 5]},
+            },
+            "cells": {},
+        }
+    }
+}
+
 
 def test_yosys_component_create():
     """Test create YosysComponent"""
@@ -93,7 +120,7 @@ def test_yosys_component_create_reload():
     assert comp.out_port.value == 0xA
 
 
-def test_yosys_component_create_reload_fail():
+def test_yosys_component_create_reload_fail_portwidth():
     """Test create YosysComponent - and reload changed netlist OK"""
     circuit = Circuit()
     comp = YosysComponent(circuit)
@@ -113,6 +140,34 @@ def test_yosys_component_create_reload_fail():
         comp.reload_from_netlist(yosys_netlist)
 
 
+def test_yosys_component_create_reload_fail_extra_ports():
+    """Test create YosysComponent - and reload changed netlist OK"""
+    circuit = Circuit()
+    comp = YosysComponent(circuit)
+    yosys_netlist = YosysNetlist(**netlist_dict_if_2outports)
+    comp.create_from_netlist(yosys_netlist)
+
+    yosys_netlist = YosysNetlist(**netlist_dict_if_3outports)
+
+    # Fail due to extra port
+    with pytest.raises(YosysComponentException):
+        comp.reload_from_netlist(yosys_netlist)
+
+
+def test_yosys_component_create_reload_fail_less_ports():
+    """Test create YosysComponent - and reload changed netlist OK"""
+    circuit = Circuit()
+    comp = YosysComponent(circuit)
+    yosys_netlist = YosysNetlist(**netlist_dict_if_3outports)
+    comp.create_from_netlist(yosys_netlist)
+
+    yosys_netlist = YosysNetlist(**netlist_dict_if_2outports)
+
+    # Fail due to extra port
+    with pytest.raises(YosysComponentException):
+        comp.reload_from_netlist(yosys_netlist)
+
+
 def test_yosys_component_create_static_levels():
     """Test create YosysComponent - with static levels"""
     netlist_dict_static = {