digsim-logic-simulator 0.8.0__tar.gz → 0.9.0__tar.gz

{digsim_logic_simulator-0.8.0/src/digsim_logic_simulator.egg-info → digsim_logic_simulator-0.9.0}/PKG-INFO

@@ -1,6 +1,6 @@
 Metadata-Version: 2.4
 Name: digsim-logic-simulator
-Version: 0.8.0
+Version: 0.9.0
 Summary: Interactive Digital Logic Simulator
 Author-email: Fredrik Andersson <freand@gmail.com>
 Maintainer-email: Fredrik Andersson <freand@gmail.com>
@@ -22,7 +22,7 @@ Requires-Dist: pyside6==6.9.1
 Requires-Dist: pexpect==4.9.0
 Requires-Dist: pydantic==2.11.7
 Requires-Dist: qtawesome==1.4.0
-Requires-Dist: yowasp-yosys==0.55.0.0.post944
+Requires-Dist: yowasp-yosys==0.57.0.0.post986
 Dynamic: license-file
 
 # DigSim - Interactive Digital Logic Simulator

{digsim_logic_simulator-0.8.0 → digsim_logic_simulator-0.9.0}/pyproject.toml

@@ -5,7 +5,7 @@ build-backend = "setuptools.build_meta"
 [project]
 name = "digsim-logic-simulator"
 description = "Interactive Digital Logic Simulator"
-version = "0.8.0"
+version = "0.9.0"
 authors = [{name = "Fredrik Andersson", email = "freand@gmail.com"}]
 maintainers =  [{name = "Fredrik Andersson", email = "freand@gmail.com"}]
 readme = "README.md"
@@ -30,7 +30,7 @@ dependencies = [
   "pexpect==4.9.0",
   "pydantic==2.11.7",
   "qtawesome==1.4.0",
-  "yowasp-yosys==0.55.0.0.post944",
+  "yowasp-yosys==0.57.0.0.post986",
 ]
 
 keywords = ["educational", "simulation", "digital"]

{digsim_logic_simulator-0.8.0 → digsim_logic_simulator-0.9.0}/src/digsim/circuit/components/_yosys_component.py

@@ -10,8 +10,9 @@ import json
 
 import digsim.circuit.components._yosys_atoms
 from digsim.synth import Synthesis
-from digsim.utils import YosysNetlist
+from digsim.utils import YosysCell, YosysModule, YosysNetlist
 
+from ._static_level import GND, VDD
 from .atoms import Component, DigsimException, MultiComponent, PortMultiBitWire
 
 
@@ -29,6 +30,7 @@ class YosysComponent(MultiComponent):
         self._gates_comp = None
         self._net_comp = None
         self._netlist_module = None
+        self._netlist_nets = None
         self._setup_base()
 
         if nets:
@@ -47,13 +49,15 @@ class YosysComponent(MultiComponent):
         modules = netlist_object.get_modules()
         module_name = list(modules.keys())[0]
         self._netlist_module = netlist_object.get_modules()[module_name]
+        self._netlist_nets = self._netlist_module.get_nets()
+
         # Set Name
         self.set_name(module_name)
         self.set_display_name(module_name)
         # Add External Ports
-        for portname, port_dict in self._netlist_module.get_external_interface().items():
+        for portname, port_dict in self._netlist_module.ports.items():
             external_port = PortMultiBitWire(
-                self, portname, width=len(port_dict["nets"]), output=not port_dict["output"]
+                self, portname, width=len(port_dict.bits), output=port_dict.is_output
             )
             self.add_port(external_port)
         # Create component
@@ -64,18 +68,10 @@ class YosysComponent(MultiComponent):
         modules = netlist_object.get_modules()
         module_name = list(modules.keys())[0]
         reload_module = netlist_object.get_modules()[module_name]
+        reload_nets = reload_module.get_nets()
 
-        # Verify that new external interface is the same as the current
-        current_ext_if = self._netlist_module.get_external_interface()
-        new_ext_if = reload_module.get_external_interface()
-
-        if current_ext_if.keys() != new_ext_if.keys():
+        if not self._netlist_module.is_same_interface(reload_module):
             raise YosysComponentException("Yosys component interface differs")
-        for key, _ in current_ext_if.items():
-            if len(current_ext_if[key]["nets"]) != len(new_ext_if[key]["nets"]):
-                raise YosysComponentException("Yosys component interface differs")
-            if current_ext_if[key]["output"] != new_ext_if[key]["output"]:
-                raise YosysComponentException("Yosys component interface differs")
 
         # Disconnect ports
         self._disconnect_external_ports()
@@ -86,63 +82,79 @@ class YosysComponent(MultiComponent):
             self._net_comp.delete_all_ports()
         # Setup netlist
         self._netlist_module = reload_module
+        self._netlist_nets = reload_nets
         # Create component
         self._create_component()
 
     def _create_cells(self):
         """Create cells in component"""
         components_dict = {}
-        for cellname, cell in self._netlist_module.get_cells().items():
+        for cellname, cell in self._netlist_module.cells.items():
+            if cell.type == "$scopeinfo":
+                continue
             component_class = getattr(
-                digsim.circuit.components._yosys_atoms, cell.get_friendly_type()
+                digsim.circuit.components._yosys_atoms, cell.component_type()
             )
-            component = component_class(self._circuit, name=cell.get_friendly_name())
+            component = component_class(self._circuit, name=cell.component_name(cellname))
             self._gates_comp.add(component)
             components_dict[cellname] = component
+
+        vdd = VDD(self._circuit)
+        self._gates_comp.add(vdd)
+        components_dict["VDD"] = vdd
+        gnd = GND(self._circuit)
+        self._gates_comp.add(gnd)
+        components_dict["GND"] = gnd
+
         return components_dict
 
-    def _connect_cell_port(self, components_dict, src_cell, source_port):
-        """Connect cell ports"""
-        src_comp = components_dict[src_cell.name()]
-        src_comp_port = src_comp.port(source_port.name())
-        net = source_port.get_nets()[0]
-        for sink_port in source_port.get_sinks():
-            if sink_port.get_parent().get_type() == "module":
+    def _connect_sinks(self, components_dict, src_comp_port, sinks):
+        """Connect a source port to multiple sinks"""
+        for sink_port in sinks:
+            if isinstance(sink_port.parent, YosysModule):
                 # Connect cell output to module top
-                for dst_bit, sink_net in enumerate(sink_port.get_nets()):
-                    if net == sink_net:
-                        dst_port = self.port(sink_port.name()).get_bit(dst_bit)
-                        src_comp_port.wire = dst_port
+                dst_port = self.port(sink_port.name).get_bit(sink_port.bit_index)
+                src_comp_port.wire = dst_port
             else:
                 # Connect cell output to cell input
-                dst_comp = components_dict[sink_port.get_parent().name()]
-                src_comp_port.wire = dst_comp.port(sink_port.name())
+                dst_comp = components_dict[sink_port.parent_name]
+                src_comp_port.wire = dst_comp.port(sink_port.name)
 
     def _connect_cells(self, components_dict):
         """Connect all cells"""
-        for _, src_cell in self._netlist_module.get_cells().items():
-            for source_port in src_cell.get_source_ports():
-                self._connect_cell_port(components_dict, src_cell, source_port)
+        for net, source in self._netlist_nets.source.items():
+            if isinstance(source.parent, YosysModule):
+                # Only connect cells here
+                continue
+            if isinstance(source.parent, YosysCell):
+                src_comp = components_dict[source.parent_name]
+                self._connect_sinks(
+                    components_dict, src_comp.port(source.name), self._netlist_nets.sinks[net]
+                )
+
+        gnd_sinks = self._netlist_nets.sinks.get("0", [])
+        self._connect_sinks(components_dict, components_dict["GND"].port("O"), gnd_sinks)
+        vdd_sinks = self._netlist_nets.sinks.get("1", [])
+        self._connect_sinks(components_dict, components_dict["VDD"].port("O"), vdd_sinks)
 
     def _connect_external_input_port(self, components_dict, portname, port_dict):
-        """Conenct external input port"""
-        for bit_idx, net in enumerate(port_dict["nets"]):
-            for sink_port in self._netlist_module.get_sinks(net):
-                if sink_port.get_parent().get_type() == "module":
+        """Connect external input port"""
+        for bit_idx, net in enumerate(port_dict.bits):
+            for sink_port in self._netlist_nets.sinks[net]:
+                if isinstance(sink_port.parent, YosysModule):
                     # Connect module input to module output
-                    for dst_bit, sink_net in enumerate(sink_port.get_nets()):
-                        if net == sink_net:
-                            dst_port = self.port(sink_port.name()).get_bit(dst_bit)
-                            self.port(portname).get_bit(bit_idx).wire = dst_port
+                    dst_port = self.port(sink_port.name).get_bit(sink_port.bit_index)
+                    self.port(portname).get_bit(bit_idx).wire = dst_port
                 else:
                     # Connect module input to cell input
-                    dst_comp = components_dict[sink_port.get_parent().name()]
-                    self.port(portname).get_bit(bit_idx).wire = dst_comp.port(sink_port.name())
+                    self._connect_sinks(
+                        components_dict, self.port(portname).get_bit(bit_idx), [sink_port]
+                    )
 
     def _connect_external_input(self, components_dict):
         """Connect all external input ports"""
-        for portname, port_dict in self._netlist_module.get_external_interface().items():
-            if not port_dict["output"]:
+        for portname, port_dict in self._netlist_module.ports.items():
+            if port_dict.direction == "output":
                 continue
             self._connect_external_input_port(components_dict, portname, port_dict)
 
@@ -176,8 +188,7 @@ class YosysComponent(MultiComponent):
         else:
             raise YosysComponentException(f"Unknown file extension '{self._path}'")
 
-        yosys_netlist = YosysNetlist()
-        yosys_netlist.from_dict(netlist_dict)
+        yosys_netlist = YosysNetlist(**netlist_dict)
         modules = yosys_netlist.get_modules()
 
         if len(modules) > 1:

{digsim_logic_simulator-0.8.0 → digsim_logic_simulator-0.9.0}/src/digsim/circuit/components/ic/74162.json

@@ -1,6 +1,6 @@
 
 {
-  "creator": "Yosys 0.53+101 (git sha1 2a25d9241, g++ 13.3.0-6ubuntu2~24.04 -fPIC -O3)",
+  "creator": "Yosys 0.57 (git sha1 3aca86049, ccache clang++ 18.1.3 -O3 -flto -flto)",
   "modules": {
     "ttl_74162": {
       "attributes": {
@@ -821,7 +821,7 @@
         }
       },
       "netnames": {
-        "$abc$895$auto$opt_dff.cc:194:make_patterns_logic$32": {
+        "$abc$895$auto$opt_dff.cc:247:make_patterns_logic$32": {
           "hide_name": 1,
           "bits": [ 18 ],
           "attributes": {
@@ -1111,3 +1111,4 @@
     }
   }
 }
+

{digsim_logic_simulator-0.8.0 → digsim_logic_simulator-0.9.0}/src/digsim/circuit/components/ic/7448.json

@@ -1,6 +1,6 @@
 
 {
-  "creator": "Yosys 0.53+101 (git sha1 2a25d9241, g++ 13.3.0-6ubuntu2~24.04 -fPIC -O3)",
+  "creator": "Yosys 0.57 (git sha1 3aca86049, ccache clang++ 18.1.3 -O3 -flto -flto)",
   "modules": {
     "ic7448": {
       "attributes": {
@@ -76,8 +76,8 @@
             "Y": "output"
           },
           "connections": {
-            "A": [ 2 ],
-            "B": [ 3 ],
+            "A": [ 3 ],
+            "B": [ 2 ],
             "Y": [ 15 ]
           }
         },
@@ -114,8 +114,8 @@
             "Y": "output"
           },
           "connections": {
-            "A": [ 3 ],
-            "B": [ 4 ],
+            "A": [ 4 ],
+            "B": [ 3 ],
             "Y": [ 17 ]
           }
         },
@@ -170,8 +170,8 @@
             "Y": "output"
           },
           "connections": {
-            "A": [ 2 ],
-            "B": [ 3 ],
+            "A": [ 3 ],
+            "B": [ 2 ],
             "Y": [ 19 ]
           }
         },
@@ -376,8 +376,8 @@
             "Y": "output"
           },
           "connections": {
-            "A": [ 2 ],
-            "B": [ 3 ],
+            "A": [ 3 ],
+            "B": [ 2 ],
             "Y": [ 28 ]
           }
         },
@@ -526,8 +526,8 @@
             "Y": "output"
           },
           "connections": {
-            "A": [ 2 ],
-            "B": [ 3 ],
+            "A": [ 3 ],
+            "B": [ 2 ],
             "Y": [ 34 ]
           }
         },
@@ -600,8 +600,8 @@
             "Y": "output"
           },
           "connections": {
-            "A": [ 2 ],
-            "B": [ 3 ],
+            "A": [ 3 ],
+            "B": [ 2 ],
             "Y": [ 37 ]
           }
         },
@@ -895,3 +895,4 @@
     }
   }
 }
+

{digsim_logic_simulator-0.8.0 → digsim_logic_simulator-0.9.0}/src/digsim/utils/__init__.py

@@ -3,4 +3,4 @@
 
 """All classes within digsim.utils namespace"""
 
-from ._yosys_netlist import YosysNetlist  # noqa: F401
+from ._yosys_netlist import YosysCell, YosysModule, YosysNetlist  # noqa: F401

digsim_logic_simulator-0.9.0/src/digsim/utils/_yosys_netlist.py

@@ -0,0 +1,123 @@
+# Copyright (c) Fredrik Andersson, 2023
+# All rights reserved
+
+"""
+Module with classes to parse a yosys netlist
+"""
+
+from __future__ import annotations
+
+from typing import Any, Optional, Union
+
+from pydantic import Field
+from pydantic.dataclasses import dataclass
+
+
+@dataclass
+class NetPort:
+    parent: Union[YosysModule, YosysCell]
+    parent_name: str
+    name: str
+    bit_index: Optional[int] = None
+
+
+@dataclass
+class Nets:
+    source: dict[int, NetPort] = Field(default_factory=dict)
+    sinks: dict[int, list[NetPort]] = Field(default_factory=dict)
+
+
+@dataclass
+class YosysPort:
+    direction: str
+    bits: list[Union[int, str]]
+
+    @property
+    def is_output(self):
+        return self.direction == "output"
+
+    def is_same(self, compare_port):
+        return (compare_port.direction == self.direction) and (
+            len(compare_port.bits) == len(self.bits)
+        )
+
+
+@dataclass
+class YosysCell:
+    type: str
+    port_directions: dict[str, str] = Field(default_factory=dict)
+    connections: dict[str, list[Union[str, int]]] = Field(default_factory=dict)
+    hide_name: int = 0
+    parameters: dict[str, Any] = Field(default_factory=dict)
+    attributes: dict[str, Any] = Field(default_factory=dict)
+
+    def get_nets(self, name, nets):
+        for port_name, net_list in self.connections.items():
+            net = net_list[0]
+            port = NetPort(parent=self, parent_name=name, name=port_name)
+            if self.port_directions[port_name] == "input":
+                if net not in nets.sinks:
+                    nets.sinks[net] = []
+                nets.sinks[net].append(port)
+            else:
+                nets.source[net] = port
+
+    def component_name(self, name):
+        """Return a friendly name for a netlist cell"""
+        return f"{name.split('$')[-1]}_{self.component_type()}"
+
+    def component_type(self):
+        """Return a friendly type for a netlist cell"""
+        return f"_{self.type[2:-1]}_"
+
+
+@dataclass
+class YosysNetName:
+    bits: list[int]
+    attributes: dict[str, Any] = Field(default_factory=dict)
+    hide_name: int = 0
+
+
+@dataclass
+class YosysModule:
+    attributes: dict[str, Any] = Field(default_factory=dict)
+    parameter_default_values: dict[str, Any] = Field(default_factory=dict)
+    ports: dict[str, YosysPort] = Field(default_factory=dict)
+    cells: dict[str, YosysCell] = Field(default_factory=dict)
+    netnames: dict[str, YosysNetName] = Field(default_factory=dict)
+
+    def is_same_interface(self, netlist):
+        is_same = True
+        for netlist_port_name, netlist_port in netlist.ports.items():
+            module_port = self.ports.get(netlist_port_name)
+            if module_port is None or not module_port.is_same(netlist_port):
+                is_same = False
+                break
+        return is_same
+
+    def get_nets(self):
+        nets = Nets()
+
+        for port_name, port_item in self.ports.items():
+            for bit_index, net in enumerate(port_item.bits):
+                port = NetPort(parent=self, parent_name="top", name=port_name, bit_index=bit_index)
+                if port_item.is_output:
+                    if net not in nets.sinks:
+                        nets.sinks[net] = []
+                    nets.sinks[net].append(port)
+                else:
+                    nets.source[net] = port
+
+        for cell_name, cell in self.cells.items():
+            cell.get_nets(cell_name, nets)
+
+        return nets
+
+
+@dataclass
+class YosysNetlist:
+    creator: Optional[str] = None
+    modules: dict[str, YosysModule] = Field(default_factory=dict)
+
+    def get_modules(self):
+        return self.modules

{digsim_logic_simulator-0.8.0 → digsim_logic_simulator-0.9.0/src/digsim_logic_simulator.egg-info}/PKG-INFO

@@ -1,6 +1,6 @@
 Metadata-Version: 2.4
 Name: digsim-logic-simulator
-Version: 0.8.0
+Version: 0.9.0
 Summary: Interactive Digital Logic Simulator
 Author-email: Fredrik Andersson <freand@gmail.com>
 Maintainer-email: Fredrik Andersson <freand@gmail.com>
@@ -22,7 +22,7 @@ Requires-Dist: pyside6==6.9.1
 Requires-Dist: pexpect==4.9.0
 Requires-Dist: pydantic==2.11.7
 Requires-Dist: qtawesome==1.4.0
-Requires-Dist: yowasp-yosys==0.55.0.0.post944
+Requires-Dist: yowasp-yosys==0.57.0.0.post986
 Dynamic: license-file
 
 # DigSim - Interactive Digital Logic Simulator

{digsim_logic_simulator-0.8.0 → digsim_logic_simulator-0.9.0}/src/digsim_logic_simulator.egg-info/requires.txt

@@ -3,4 +3,4 @@ pyside6==6.9.1
 pexpect==4.9.0
 pydantic==2.11.7
 qtawesome==1.4.0
-yowasp-yosys==0.55.0.0.post944
+yowasp-yosys==0.57.0.0.post986

{digsim_logic_simulator-0.8.0 → digsim_logic_simulator-0.9.0}/tests/test_yosys_netlist.py

@@ -3,6 +3,9 @@
 
 """Pystest module to test functionality of yosys component"""
 
+import json
+from pathlib import Path
+
 import pytest
 
 from digsim.circuit import Circuit
@@ -63,8 +66,7 @@ def test_yosys_component_create():
     """Test create YosysComponent"""
     circuit = Circuit()
     comp = YosysComponent(circuit)
-    yosys_netlist = YosysNetlist()
-    yosys_netlist.from_dict(netlist_dict_if_one)
+    yosys_netlist = YosysNetlist(**netlist_dict_if_one)
     comp.create_from_netlist(yosys_netlist)
 
     comp.in_port.value = 0xA
@@ -76,16 +78,14 @@ def test_yosys_component_create_reload():
     """Test create YosysComponent - and reload changed netlist OK"""
     circuit = Circuit()
     comp = YosysComponent(circuit)
-    yosys_netlist = YosysNetlist()
-    yosys_netlist.from_dict(netlist_dict_if_one)
+    yosys_netlist = YosysNetlist(**netlist_dict_if_one)
     comp.create_from_netlist(yosys_netlist)
 
     comp.in_port.value = 0xA
     circuit.run(ms=1)
     assert comp.out_port.value == 0x5
 
-    yosys_netlist = YosysNetlist()
-    yosys_netlist.from_dict(netlist_dict_if_two)
+    yosys_netlist = YosysNetlist(**netlist_dict_if_two)
     comp.reload_from_netlist(yosys_netlist)
 
     comp.in_port.value = 0xA
@@ -97,18 +97,16 @@ def test_yosys_component_create_reload_fail():
     """Test create YosysComponent - and reload changed netlist OK"""
     circuit = Circuit()
     comp = YosysComponent(circuit)
-    yosys_netlist = YosysNetlist()
-    yosys_netlist.from_dict(netlist_dict_if_one)
+    yosys_netlist = YosysNetlist(**netlist_dict_if_one)
     comp.create_from_netlist(yosys_netlist)
 
-    yosys_netlist = YosysNetlist()
-    yosys_netlist.from_dict(netlist_dict_if_three)
+    yosys_netlist = YosysNetlist(**netlist_dict_if_three)
 
     # Fail due to wider in_port
     with pytest.raises(YosysComponentException):
         comp.reload_from_netlist(yosys_netlist)
 
-    yosys_netlist.from_dict(netlist_dict_if_four)
+    yosys_netlist = YosysNetlist(**netlist_dict_if_four)
 
     # Fail due to wider out_port
     with pytest.raises(YosysComponentException):
@@ -132,8 +130,7 @@ def test_yosys_component_create_static_levels():
     }
     circuit = Circuit()
     comp = YosysComponent(circuit)
-    yosys_netlist = YosysNetlist()
-    yosys_netlist.from_dict(netlist_dict_static)
+    yosys_netlist = YosysNetlist(**netlist_dict_static)
     comp.create_from_netlist(yosys_netlist)
     circuit.init()
     circuit.run(ms=1)
@@ -167,8 +164,7 @@ def test_yosys_component_not_gate_multiple_outputs():
     }
     circuit = Circuit()
     comp = YosysComponent(circuit)
-    yosys_netlist = YosysNetlist()
-    yosys_netlist.from_dict(netlist_dict)
+    yosys_netlist = YosysNetlist(**netlist_dict)
     comp.create_from_netlist(yosys_netlist)
     circuit.init()
     comp.in_port.value = 0
@@ -202,10 +198,18 @@ def test_yosys_component_not_gate_static_input():
     }
     circuit = Circuit()
     comp = YosysComponent(circuit)
-    yosys_netlist = YosysNetlist()
-    yosys_netlist.from_dict(netlist_dict)
+    yosys_netlist = YosysNetlist(**netlist_dict)
     comp.create_from_netlist(yosys_netlist)
     circuit.init()
     assert comp.out_port.value == "X"
     circuit.run(ms=1)
     assert comp.out_port.value == 1
+
+
+def test_yosys_complex_netlist():
+    comlex_json_netlist_file = (
+        Path(__file__).parent.parent / "src/digsim/circuit/components/ic/74162.json"
+    )
+    with open(comlex_json_netlist_file, encoding="utf-8") as json_file:
+        netlist_dict = json.load(json_file)
+    YosysNetlist(**netlist_dict)