digsim-logic-simulator 0.7.0__tar.gz → 0.9.0__tar.gz

{digsim_logic_simulator-0.7.0/src/digsim_logic_simulator.egg-info → digsim_logic_simulator-0.9.0}/PKG-INFO

@@ -1,42 +1,9 @@
 Metadata-Version: 2.4
 Name: digsim-logic-simulator
-Version: 0.7.0
+Version: 0.9.0
 Summary: Interactive Digital Logic Simulator
 Author-email: Fredrik Andersson <freand@gmail.com>
 Maintainer-email: Fredrik Andersson <freand@gmail.com>
-License: The Clear BSD License
-        
-        Copyright (c) 2023-2024, Fredrik Andersson
-        All rights reserved.
-        
-        Redistribution and use in source and binary forms, with or without
-        modification, are permitted provided that the following conditions are met:
-        
-        * Redistributions of source code must retain the above copyright notice, this
-          list of conditions and the following disclaimer.
-        
-        * Redistributions in binary form must reproduce the above copyright notice,
-          this list of conditions and the following disclaimer in the documentation
-          and/or other materials provided with the distribution.
-        
-        * Neither the name of the copyright holder nor the names of its
-          contributors may be used to endorse or promote products derived from
-          this software without specific prior written permission.
-        
-        NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS
-        LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-        "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-        THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-        ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
-        LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-        CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
-        GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-        HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-        LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
-        OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-        
-        -------------------------------------------------------------------------------
-        
 Project-URL: homepage, https://github.com/freand76/digsim
 Keywords: educational,simulation,digital
 Classifier: Development Status :: 5 - Production/Stable
@@ -50,12 +17,12 @@ Classifier: Programming Language :: Python :: 3 :: Only
 Requires-Python: >=3.9
 Description-Content-Type: text/markdown
 License-File: LICENSE.md
-Requires-Dist: pyvcd>=0.4.1
-Requires-Dist: pyside6>=6.9.0
+Requires-Dist: pyvcd==0.4.1
+Requires-Dist: pyside6==6.9.1
 Requires-Dist: pexpect==4.9.0
-Requires-Dist: pydantic==2.11.4
+Requires-Dist: pydantic==2.11.7
 Requires-Dist: qtawesome==1.4.0
-Requires-Dist: yowasp-yosys==0.53.0.0.post912
+Requires-Dist: yowasp-yosys==0.57.0.0.post986
 Dynamic: license-file
 
 # DigSim - Interactive Digital Logic Simulator

{digsim_logic_simulator-0.7.0 → digsim_logic_simulator-0.9.0}/pyproject.toml

@@ -5,11 +5,11 @@ build-backend = "setuptools.build_meta"
 [project]
 name = "digsim-logic-simulator"
 description = "Interactive Digital Logic Simulator"
-version = "0.7.0"
+version = "0.9.0"
 authors = [{name = "Fredrik Andersson", email = "freand@gmail.com"}]
 maintainers =  [{name = "Fredrik Andersson", email = "freand@gmail.com"}]
 readme = "README.md"
-license = { file = "LICENSE.md" }
+license-files = ["LICENSE.md"]
 urls = { homepage = "https://github.com/freand76/digsim" }
 
 classifiers = [
@@ -25,12 +25,12 @@ classifiers = [
 
 requires-python = ">=3.9"
 dependencies = [
-  "pyvcd>=0.4.1",
-  "pyside6>=6.9.0",
+  "pyvcd==0.4.1",
+  "pyside6==6.9.1",
   "pexpect==4.9.0",
-  "pydantic==2.11.4",
+  "pydantic==2.11.7",
   "qtawesome==1.4.0",
-  "yowasp-yosys==0.53.0.0.post912",
+  "yowasp-yosys==0.57.0.0.post986",
 ]
 
 keywords = ["educational", "simulation", "digital"]

{digsim_logic_simulator-0.7.0 → digsim_logic_simulator-0.9.0}/src/digsim/app/gui/_circuit_area.py

@@ -1,4 +1,4 @@
-# Copyright (c) Fredrik Andersson, 2023-2024
+# Copyright (c) Fredrik Andersson, 2023-2025
 # All rights reserved
 
 """The circuit area and component widget"""
@@ -275,7 +275,7 @@ class _CircuitAreaScene(QGraphicsScene):
         component_objects = self._app_model.objects.components.get_object_list()
         for src_comp_item in component_objects:
             for src_port in src_comp_item.component.outports():
-                for dst_port in src_port.get_wires():
+                for dst_port in src_port.wired_ports:
                     dst_comp_item = self._app_model.objects.components.get_object(
                         dst_port.parent()
                     )

{digsim_logic_simulator-0.7.0 → digsim_logic_simulator-0.9.0}/src/digsim/app/gui_objects/_image_objects.py

@@ -3,6 +3,8 @@
 
 """A component with an image as symbol the GUI"""
 
+from __future__ import annotations
+
 from pathlib import Path
 
 from PySide6.QtCore import QPoint, Qt
@@ -14,8 +16,8 @@ from ._component_object import ComponentObject
 class ImageObject(ComponentObject):
     """The class for a image component placed in the GUI"""
 
-    IMAGE_FILENAME = None
-    ACTIVE_IMAGE_FILENAME = None
+    IMAGE_FILENAME: str | None = None
+    ACTIVE_IMAGE_FILENAME: str | None = None
     _pixmap = None
     _pixmap_active = None
 

{digsim_logic_simulator-0.7.0 → digsim_logic_simulator-0.9.0}/src/digsim/circuit/_circuit.py

@@ -1,16 +1,19 @@
-# Copyright (c) Fredrik Andersson, 2023-2024
+# Copyright (c) Fredrik Andersson, 2023-2025
 # All rights reserved
 
 """
 Module that handles the circuit simulation of components
 """
 
+from __future__ import annotations
+
 import os
+from typing import Tuple
 
 from digsim.storage_model import CircuitDataClass, CircuitFileDataClass
 
 from ._waves_writer import WavesWriter
-from .components.atoms import DigsimException
+from .components.atoms import Component, DigsimException, PortOutDelta
 
 
 class CircuitError(DigsimException):
@@ -23,90 +26,89 @@ class CircuitEvent:
     delta events in the simulation.
     """
 
-    def __init__(self, time_ns, port, value):
-        self._time_ns = time_ns
-        self._port = port
-        self._value = value
+    def __init__(self, time_ns: int, port: PortOutDelta, value: int | str | None):
+        self._time_ns: int = time_ns
+        self._port: PortOutDelta = port
+        self._value: int | str | None = value
 
     @property
-    def time_ns(self):
+    def time_ns(self) -> int:
         """Get the simulation time (ns) of this event"""
         return self._time_ns
 
     @property
-    def port(self):
+    def port(self) -> PortOutDelta:
         """Get the port of this event"""
         return self._port
 
     @property
-    def value(self):
+    def value(self) -> int | str | None:
         """Get the delta cycle value of this event"""
         return self._value
 
-    def is_same_event(self, port):
+    def is_same_event(self, port: PortOutDelta):
         """Return True if the in the event is the same as"""
         return port == self._port
 
-    def update(self, time_ns, value):
+    def update(self, time_ns: int, value: int | str | None):
         """Update the event with a new time (ns) and a new value"""
         self._time_ns = time_ns
         self._value = value
 
-    def __lt__(self, other):
+    def __lt__(self, other) -> bool:
         return other.time_ns > self.time_ns
 
 
 class Circuit:
     """Class thay handles the circuit simulation"""
 
-    def __init__(self, name=None, vcd=None):
-        self._components = {}
-        self._circuit_events = []
-        self._name = name
-        self._time_ns = 0
-        self._folder = None
+    def __init__(self, name: str | None = None, vcd: str | None = None):
+        self._components: dict[str, Component] = {}
+        self._circuit_events: list[CircuitEvent] = []
+        self._name: str | None = name
+        self._time_ns: int = 0
+        self._folder: str | None = None
+        self._vcd: WavesWriter | None = None
 
         if vcd is not None:
             self._vcd = WavesWriter(filename=vcd)
-        else:
-            self._vcd = None
 
     @property
-    def name(self):
+    def name(self) -> str | None:
         """Get the circuit name"""
         return self._name
 
     @property
-    def time_ns(self):
+    def time_ns(self) -> int:
         """Get the current simulation time (ns)"""
         return self._time_ns
 
     @property
-    def components(self):
+    def components(self) -> list[Component]:
         """Get the components in this circuit"""
         comp_array = []
         for _, comp in self._components.items():
             comp_array.append(comp)
         return comp_array
 
-    def load_path(self, path):
+    def load_path(self, path) -> str:
         """Get the load path relative to the circuit path"""
         if self._folder is not None:
             return self._folder + "/" + path
         return path
 
-    def store_path(self, path):
+    def store_path(self, path) -> str:
         """Get the store path relative to the circuit path"""
         if self._folder is not None:
             return os.path.relpath(path, self._folder)
         return path
 
-    def delete_component(self, component):
+    def delete_component(self, component: Component):
         """Delete a component from the circuit"""
         del self._components[component.name()]
         component.remove_connections()
 
-    def get_toplevel_components(self):
+    def get_toplevel_components(self) -> list[Component]:
         """Get toplevel components in the circuit"""
         toplevel_components = []
         for _, comp in self._components.items():
@@ -157,7 +159,7 @@ class Circuit:
             for port in comp.ports:
                 self._vcd.write(port, self._time_ns)
 
-    def _time_to_ns(self, s=None, ms=None, us=None, ns=None):
+    def _time_to_ns(self, s=None, ms=None, us=None, ns=None) -> int:
         time_ns = 0
         time_ns += s * 1e9 if s is not None else 0
         time_ns += ms * 1e6 if ms is not None else 0
@@ -168,7 +170,7 @@ class Circuit:
     def __exit__(self, exc_type, exc_value, exc_traceback):
         self._vcd.close()
 
-    def process_single_event(self, stop_time_ns=None):
+    def process_single_event(self, stop_time_ns=None) -> Tuple[bool, bool]:
         """
         Process one simulation event
         Return False if ther are now events of if the stop_time has passed
@@ -190,13 +192,20 @@ class Circuit:
             self._vcd.write(event.port, self._time_ns)
         return True, toplevel
 
-    def _is_toplevel_event(self):
+    def _is_toplevel_event(self) -> bool:
         if len(self._circuit_events) == 0:
             return False
         event = self._circuit_events[0]
         return event.port.parent().is_toplevel()
 
-    def run(self, s=None, ms=None, us=None, ns=None, single_step=False):
+    def run(
+        self,
+        s: int | None = None,
+        ms: int | None = None,
+        us: int | None = None,
+        ns: int | None = None,
+        single_step: bool = False,
+    ) -> bool:
         """Run simulation for a period of time"""
         stop_time_ns = self._time_ns + self._time_to_ns(s=s, ms=ms, us=us, ns=ns)
         single_step_stop = False
@@ -210,13 +219,19 @@ class Circuit:
         self._time_ns = max(self._time_ns, stop_time_ns)
         return single_step_stop
 
-    def run_until(self, s=None, ms=None, us=None, ns=None):
+    def run_until(
+        self,
+        s: int | None = None,
+        ms: int | None = None,
+        us: int | None = None,
+        ns: int | None = None,
+    ):
         """Run simulation until a specified time"""
         stop_time_ns = self._time_to_ns(s=s, ms=ms, us=us, ns=ns)
         if stop_time_ns >= self._time_ns:
             self.run(ns=stop_time_ns - self._time_ns)
 
-    def add_event(self, port, value, propagation_delay_ns):
+    def add_event(self, port: PortOutDelta, value: int | str | None, propagation_delay_ns: int):
         """Add delta cycle event, this will also write values to .vcd file"""
         event_time_ns = self._time_ns + propagation_delay_ns
         # print(f"Add event {port.parent().name()}:{port.name()} => {value}")
@@ -226,7 +241,7 @@ class Circuit:
                 return
         self._circuit_events.append(CircuitEvent(event_time_ns, port, value))
 
-    def add_component(self, component):
+    def add_component(self, component: Component):
         """Add component to circuit"""
         name_id = 1
         namebase = component.name()
@@ -235,21 +250,21 @@ class Circuit:
             name_id += 1
         self._components[component.name()] = component
 
-    def change_component_name(self, component, name):
+    def change_component_name(self, component: Component, name: str):
         """Change component name"""
         comp = self._components[component.name()]
         del self._components[component.name()]
         comp.set_name(name, update_circuit=False)
         self.add_component(comp)
 
-    def get_component(self, component_name):
+    def get_component(self, component_name: str) -> Component:
         """Get component witgh 'component_name'"""
         comp = self._components.get(component_name)
         if comp is not None:
             return comp
         raise CircuitError(f"Component '{component_name}' not found")
 
-    def to_dataclass(self, folder=None):
+    def to_dataclass(self, folder: str | None = None) -> CircuitDataClass:
         """Generate dict from circuit, used when storing circuit"""
         if self._name is None:
             raise CircuitError("Circuit must have a name")
@@ -257,8 +272,12 @@ class Circuit:
         return CircuitDataClass.from_circuit(self)
 
     def from_dataclass(
-        self, circuit_dc, folder=None, component_exceptions=True, connect_exceptions=True
-    ):
+        self,
+        circuit_dc: CircuitDataClass,
+        folder: str | None = None,
+        component_exceptions: bool = True,
+        connect_exceptions: bool = True,
+    ) -> list[str]:
         """Clear circuit and add components from dict"""
         self._folder = folder
         self.clear()
@@ -285,12 +304,12 @@ class Circuit:
 
         return exception_str_list
 
-    def to_json_file(self, filename):
+    def to_json_file(self, filename: str):
         """Store circuit in json file"""
         circuitfile_dc = CircuitFileDataClass(circuit=self.to_dataclass())
         circuitfile_dc.save(filename)
 
-    def from_json_file(self, filename, folder=None):
+    def from_json_file(self, filename: str, folder: str | None = None):
         """Load circuit from json file"""
         file_dc = CircuitFileDataClass.load(filename)
         self.from_dataclass(file_dc.circuit, folder)

{digsim_logic_simulator-0.7.0 → digsim_logic_simulator-0.9.0}/src/digsim/circuit/_waves_writer.py

@@ -1,35 +1,46 @@
-# Copyright (c) Fredrik Andersson, 2023-2024
+# Copyright (c) Fredrik Andersson, 2023-2025
 # All rights reserved
 
 """
 Module that handles the creation of vcd files
 """
 
+import io
+from typing import Any, Tuple
+
 from vcd import VCDWriter
 
+from .components.atoms import Port
+
 
 class WavesWriter:
     """Class that handles the creation of vcd files"""
 
-    def __init__(self, filename):
-        self._vcd_name = filename
-        self._vcd_file = None
-        self._vcd_writer = None
-        self._vcd_dict = {}
+    def __init__(self, filename: str):
+        self._vcd_name: str = filename
+        self._vcd_file: io.TextIOWrapper | None = None
+        self._vcd_writer: VCDWriter | None = None
+        self._vcd_dict: dict[str, Any] = {}
 
-    def init(self, port_info):
+    def init(self, port_info: list[Tuple[str, str, int]]):
         """Initialize vcd writer"""
         if self._vcd_file is not None or self._vcd_writer is not None:
             self.close()
         self._vcd_file = open(self._vcd_name, mode="w", encoding="utf-8")
+        if self._vcd_file is None:
+            raise RuntimeError("VCD file is None")
         self._vcd_writer = VCDWriter(self._vcd_file, timescale="1 ns", date="today")
         for port_path, port_name, port_width in port_info:
             var = self._vcd_writer.register_var(port_path, port_name, "wire", size=port_width)
             self._vcd_dict[f"{port_path}.{port_name}"] = var
         self._vcd_file.flush()
 
-    def write(self, port, time_ns):
+    def write(self, port: Port, time_ns: int):
         """Write port value to vcd file"""
+        if self._vcd_file is None:
+            raise RuntimeError("VCD file is None")
+        if self._vcd_writer is None:
+            raise RuntimeError("VCD Writer is None")
         for wired_port in port.get_wired_ports_recursive():
             var = self._vcd_dict.get(f"{wired_port.path()}.{wired_port.name()}")
             if var is None:

{digsim_logic_simulator-0.7.0 → digsim_logic_simulator-0.9.0}/src/digsim/circuit/components/_label_wire.py

@@ -3,15 +3,15 @@
 
 """Label Wire components module"""
 
-from .atoms import Component, DigsimException, PortWire
+from .atoms import Component, DigsimException, PortIn, PortWire
 
 
 class _LabelWireStorage:
     """Singleton class with label wires"""
 
     _instance = None
-    _wire_drivers = {}
-    _wire_sinks = {}
+    _wire_drivers: dict[str, PortWire] = {}
+    _wire_sinks: dict[str, PortIn] = {}
 
     def __new__(cls):
         if cls._instance is None:

{digsim_logic_simulator-0.7.0 → digsim_logic_simulator-0.9.0}/src/digsim/circuit/components/_yosys_component.py

@@ -10,8 +10,9 @@ import json
 
 import digsim.circuit.components._yosys_atoms
 from digsim.synth import Synthesis
-from digsim.utils import YosysNetlist
+from digsim.utils import YosysCell, YosysModule, YosysNetlist
 
+from ._static_level import GND, VDD
 from .atoms import Component, DigsimException, MultiComponent, PortMultiBitWire
 
 
@@ -29,6 +30,7 @@ class YosysComponent(MultiComponent):
         self._gates_comp = None
         self._net_comp = None
         self._netlist_module = None
+        self._netlist_nets = None
         self._setup_base()
 
         if nets:
@@ -47,13 +49,15 @@ class YosysComponent(MultiComponent):
         modules = netlist_object.get_modules()
         module_name = list(modules.keys())[0]
         self._netlist_module = netlist_object.get_modules()[module_name]
+        self._netlist_nets = self._netlist_module.get_nets()
+
         # Set Name
         self.set_name(module_name)
         self.set_display_name(module_name)
         # Add External Ports
-        for portname, port_dict in self._netlist_module.get_external_interface().items():
+        for portname, port_dict in self._netlist_module.ports.items():
             external_port = PortMultiBitWire(
-                self, portname, width=len(port_dict["nets"]), output=not port_dict["output"]
+                self, portname, width=len(port_dict.bits), output=port_dict.is_output
             )
             self.add_port(external_port)
         # Create component
@@ -64,18 +68,10 @@ class YosysComponent(MultiComponent):
         modules = netlist_object.get_modules()
         module_name = list(modules.keys())[0]
         reload_module = netlist_object.get_modules()[module_name]
+        reload_nets = reload_module.get_nets()
 
-        # Verify that new external interface is the same as the current
-        current_ext_if = self._netlist_module.get_external_interface()
-        new_ext_if = reload_module.get_external_interface()
-
-        if current_ext_if.keys() != new_ext_if.keys():
+        if not self._netlist_module.is_same_interface(reload_module):
             raise YosysComponentException("Yosys component interface differs")
-        for key, _ in current_ext_if.items():
-            if len(current_ext_if[key]["nets"]) != len(new_ext_if[key]["nets"]):
-                raise YosysComponentException("Yosys component interface differs")
-            if current_ext_if[key]["output"] != new_ext_if[key]["output"]:
-                raise YosysComponentException("Yosys component interface differs")
 
         # Disconnect ports
         self._disconnect_external_ports()
@@ -86,63 +82,79 @@ class YosysComponent(MultiComponent):
             self._net_comp.delete_all_ports()
         # Setup netlist
         self._netlist_module = reload_module
+        self._netlist_nets = reload_nets
         # Create component
         self._create_component()
 
     def _create_cells(self):
         """Create cells in component"""
         components_dict = {}
-        for cellname, cell in self._netlist_module.get_cells().items():
+        for cellname, cell in self._netlist_module.cells.items():
+            if cell.type == "$scopeinfo":
+                continue
             component_class = getattr(
-                digsim.circuit.components._yosys_atoms, cell.get_friendly_type()
+                digsim.circuit.components._yosys_atoms, cell.component_type()
             )
-            component = component_class(self._circuit, name=cell.get_friendly_name())
+            component = component_class(self._circuit, name=cell.component_name(cellname))
             self._gates_comp.add(component)
             components_dict[cellname] = component
+
+        vdd = VDD(self._circuit)
+        self._gates_comp.add(vdd)
+        components_dict["VDD"] = vdd
+        gnd = GND(self._circuit)
+        self._gates_comp.add(gnd)
+        components_dict["GND"] = gnd
+
         return components_dict
 
-    def _connect_cell_port(self, components_dict, src_cell, source_port):
-        """Connect cell ports"""
-        src_comp = components_dict[src_cell.name()]
-        src_comp_port = src_comp.port(source_port.name())
-        net = source_port.get_nets()[0]
-        for sink_port in source_port.get_sinks():
-            if sink_port.get_parent().get_type() == "module":
+    def _connect_sinks(self, components_dict, src_comp_port, sinks):
+        """Connect a source port to multiple sinks"""
+        for sink_port in sinks:
+            if isinstance(sink_port.parent, YosysModule):
                 # Connect cell output to module top
-                for dst_bit, sink_net in enumerate(sink_port.get_nets()):
-                    if net == sink_net:
-                        dst_port = self.port(sink_port.name()).get_bit(dst_bit)
-                        src_comp_port.wire = dst_port
+                dst_port = self.port(sink_port.name).get_bit(sink_port.bit_index)
+                src_comp_port.wire = dst_port
             else:
                 # Connect cell output to cell input
-                dst_comp = components_dict[sink_port.get_parent().name()]
-                src_comp_port.wire = dst_comp.port(sink_port.name())
+                dst_comp = components_dict[sink_port.parent_name]
+                src_comp_port.wire = dst_comp.port(sink_port.name)
 
     def _connect_cells(self, components_dict):
         """Connect all cells"""
-        for _, src_cell in self._netlist_module.get_cells().items():
-            for source_port in src_cell.get_source_ports():
-                self._connect_cell_port(components_dict, src_cell, source_port)
+        for net, source in self._netlist_nets.source.items():
+            if isinstance(source.parent, YosysModule):
+                # Only connect cells here
+                continue
+            if isinstance(source.parent, YosysCell):
+                src_comp = components_dict[source.parent_name]
+                self._connect_sinks(
+                    components_dict, src_comp.port(source.name), self._netlist_nets.sinks[net]
+                )
+
+        gnd_sinks = self._netlist_nets.sinks.get("0", [])
+        self._connect_sinks(components_dict, components_dict["GND"].port("O"), gnd_sinks)
+        vdd_sinks = self._netlist_nets.sinks.get("1", [])
+        self._connect_sinks(components_dict, components_dict["VDD"].port("O"), vdd_sinks)
 
     def _connect_external_input_port(self, components_dict, portname, port_dict):
-        """Conenct external input port"""
-        for bit_idx, net in enumerate(port_dict["nets"]):
-            for sink_port in self._netlist_module.get_sinks(net):
-                if sink_port.get_parent().get_type() == "module":
+        """Connect external input port"""
+        for bit_idx, net in enumerate(port_dict.bits):
+            for sink_port in self._netlist_nets.sinks[net]:
+                if isinstance(sink_port.parent, YosysModule):
                     # Connect module input to module output
-                    for dst_bit, sink_net in enumerate(sink_port.get_nets()):
-                        if net == sink_net:
-                            dst_port = self.port(sink_port.name()).get_bit(dst_bit)
-                            self.port(portname).get_bit(bit_idx).wire = dst_port
+                    dst_port = self.port(sink_port.name).get_bit(sink_port.bit_index)
+                    self.port(portname).get_bit(bit_idx).wire = dst_port
                 else:
                     # Connect module input to cell input
-                    dst_comp = components_dict[sink_port.get_parent().name()]
-                    self.port(portname).get_bit(bit_idx).wire = dst_comp.port(sink_port.name())
+                    self._connect_sinks(
+                        components_dict, self.port(portname).get_bit(bit_idx), [sink_port]
+                    )
 
     def _connect_external_input(self, components_dict):
         """Connect all external input ports"""
-        for portname, port_dict in self._netlist_module.get_external_interface().items():
-            if not port_dict["output"]:
+        for portname, port_dict in self._netlist_module.ports.items():
+            if port_dict.direction == "output":
                 continue
             self._connect_external_input_port(components_dict, portname, port_dict)
 
@@ -176,8 +188,7 @@ class YosysComponent(MultiComponent):
         else:
             raise YosysComponentException(f"Unknown file extension '{self._path}'")
 
-        yosys_netlist = YosysNetlist()
-        yosys_netlist.from_dict(netlist_dict)
+        yosys_netlist = YosysNetlist(**netlist_dict)
         modules = yosys_netlist.get_modules()
 
         if len(modules) > 1:

{digsim_logic_simulator-0.7.0 → digsim_logic_simulator-0.9.0}/src/digsim/circuit/components/atoms/__init__.py

@@ -1,4 +1,4 @@
-# Copyright (c) Fredrik Andersson, 2023
+# Copyright (c) Fredrik Andersson, 2023-2025
 # All rights reserved
 
 """All classes within digsim.circuit.components.atoms namespace"""
@@ -11,6 +11,7 @@ from ._component import (  # noqa: F401
 )
 from ._digsim_exception import DigsimException  # noqa: F401
 from ._port import (  # noqa: F401
+    Port,
     PortConnectionError,
     PortIn,
     PortMultiBitWire,