da4ml 0.3.0__tar.gz → 0.3.1__tar.gz

{da4ml-0.3.0/src/da4ml.egg-info → da4ml-0.3.1}/PKG-INFO

@@ -1,6 +1,6 @@
 Metadata-Version: 2.4
 Name: da4ml
-Version: 0.3.0
+Version: 0.3.1
 Summary: Digital Arithmetic for Machine Learning
 Author-email: Chang Sun <chsun@cern.ch>
 License: GNU Lesser General Public License v3 (LGPLv3)

{da4ml-0.3.0 → da4ml-0.3.1}/src/da4ml/_version.py

@@ -17,5 +17,5 @@ __version__: str
 __version_tuple__: VERSION_TUPLE
 version_tuple: VERSION_TUPLE
 
-__version__ = version = '0.3.0'
-__version_tuple__ = version_tuple = (0, 3, 0)
+__version__ = version = '0.3.1'
+__version_tuple__ = version_tuple = (0, 3, 1)

{da4ml-0.3.0 → da4ml-0.3.1}/src/da4ml/codegen/verilog/source/build_prj.tcl

@@ -1,7 +1,7 @@
 set project_name "${PROJECT_NAME}"
 set device "${DEVICE}"
 
-set top_module "${project_name}_wrapper"
+set top_module "${project_name}"
 set output_dir "./output_${project_name}"
 
 create_project $project_name "${output_dir}/$project_name" -force -part $device
@@ -9,9 +9,10 @@ create_project $project_name "${output_dir}/$project_name" -force -part $device
 set_property TARGET_LANGUAGE Verilog [current_project]
 set_property DEFAULT_LIB work [current_project]
 
-read_verilog "${project_name}_wrapper.v"
 read_verilog "${project_name}.v"
 read_verilog "shift_adder.v"
+read_verilog "negative.v"
+read_verilog "mux.v"
 foreach file [glob -nocomplain "${project_name}_stage*.v"] {
     read_verilog $file
 }
@@ -25,8 +26,7 @@ file mkdir "${output_dir}/reports"
 
 # synth
 synth_design -top $top_module -mode out_of_context -retiming \
-    -flatten_hierarchy rebuilt -resource_sharing auto \
-    -directive AlternateRoutability
+    -flatten_hierarchy full -resource_sharing auto
 
 write_checkpoint -force "${output_dir}/${project_name}_post_synth.dcp"
 
@@ -34,15 +34,13 @@ report_timing_summary -file "${output_dir}/reports/${project_name}_post_synth_ti
 report_power -file "${output_dir}/reports/${project_name}_post_synth_power.rpt"
 report_utilization -file "${output_dir}/reports/${project_name}_post_synth_util.rpt"
 
-# set_property CARRY_REMAP 3 [get_cells -hier -filter {ref_name == CARRY8}]
-
-opt_design -directive ExploreSequentialArea
+# opt_design -directive ExploreSequentialArea
 opt_design -directive ExploreWithRemap
 
 report_design_analysis -congestion -file "${output_dir}/reports/${project_name}_post_opt_congestion.rpt"
 
 # place
-place_design -directive AltSpreadLogic_high -fanout_opt
+place_design -directive SSI_HighUtilSLRs -fanout_opt
 report_design_analysis -congestion -file "${output_dir}/reports/${project_name}_post_place_congestion_initial.rpt"
 
 phys_opt_design -directive AggressiveExplore

{da4ml-0.3.0 → da4ml-0.3.1}/src/da4ml/codegen/verilog/verilog_model.py

@@ -28,10 +28,10 @@ class VerilogModel:
         solution: Solution | CascadedSolution,
         prj_name: str,
         path: str | Path,
-        latency_cutoff: int = -1,
+        latency_cutoff: float = -1,
         print_latency: bool = True,
         part_name: str = 'xcvu13p-flga2577-2-e',
-        clock_period: int = 5,
+        clock_period: float = 5,
         clock_uncertainty: float = 0.1,
         io_delay_minmax: tuple[float, float] = (0.2, 0.4),
         register_layers: int = 1,

{da4ml-0.3.0 → da4ml-0.3.1}/src/da4ml/converter/hgq2/replica.py

@@ -157,7 +157,7 @@ class MirrorQDense(MirrorOperationBase):
             dim = inputs._vars.ndim
             axis = op.axis
             assert axis != 0, 'Cannot normalizing on batch axis'
-            axis -= 1
+            axis = axis - 1 if axis >= 0 else dim + axis
             idx = ''.join(chr(ord('a') + i) for i in range(dim))
             eq = f'...{idx},{idx[axis]}->...{idx}'
         else:

{da4ml-0.3.0 → da4ml-0.3.1}/src/da4ml/trace/ops/conv_utils.py

@@ -40,7 +40,7 @@ def stride_arr(stride: int | tuple[int, ...], arr: np.ndarray):
         stride = (stride,) * (ndim - 1)
 
     _idx = tuple(slice(None, None, st) for st in stride)
-    return arr[*_idx]
+    return arr[_idx]
 
 
 TA = TypeVar('TA', 'FixedVariableArray', NDArray[np.integer | np.floating])

{da4ml-0.3.0 → da4ml-0.3.1/src/da4ml.egg-info}/PKG-INFO

@@ -1,6 +1,6 @@
 Metadata-Version: 2.4
 Name: da4ml
-Version: 0.3.0
+Version: 0.3.1
 Summary: Digital Arithmetic for Machine Learning
 Author-email: Chang Sun <chsun@cern.ch>
 License: GNU Lesser General Public License v3 (LGPLv3)