da4ml 0.2.0__tar.gz → 0.3.0__tar.gz

da4ml-0.3.0/.clang-format

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+SpacesInContainerLiterals: false
+Standard: Cpp11
+BinPackArguments: false
+BinPackParameters: false
+ColumnLimit: 120
+IndentWidth: 4
+TabWidth: 4
+UseTab: Never

da4ml-0.3.0/DAIS-spec.md

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+Distributed Arithmetic Instruction Set (DAIS)
+=================================================
+
+DAIS is a minimal domain-specific language (DSL) for the da4ml framework. It is designed to be minimal to satisfy the requirements for reqpresenting a neural network in high-granularity. Specifically, each DAIS program contains one block of logic that are fully-parallelizable (i.e., fully combinational), and resource multiplexing shall be performed on a higher level.
+
+As the name suggests, DAIS is a Instruction Set level language for easy interperting and compilation into HDL or HLS languages. One program in DAIS consists of the following components:
+
+## Program Structure
+
+- `shape`: tuple<int, int>
+    - The number of inputs and outputs of the program.
+- `inp_shift`: vector<int>
+    - The shifts required to interpret the input data. (i.e., number of integers in the fixed-point representation)
+- `out_idxs`: vector<int>
+    - The indices of the output data shall be read from the buffer
+- `out_shifts`: vector<int>
+    - The shifts required to interpret the output data.
+- `out_negs`: vector<bool>
+    - The signs of the output data.
+- `ops`: vector<Op>
+    - The core list of operations for populating the full buffer.
+
+Each operation is reqpresented as a `Op` object, consists of the following components:
+- `opcode`: int
+    - The operation code, see [OpCode](#opcode).
+- `id0`, `id1`: int
+    - The first and second operand indices in the buffer. Unused operands must be set to `-1`.
+- `data`: int64
+    - Extra integer data for the operation, functionality depends on the opcode.
+- `dtype`: tuple<float, float, float> OR tuple<int/bool, int, int>
+    - Annotates the datatype of the output buffer as a quantization interval.
+    - (min, max, step) or (signed, integer_bits (excl sign bit), fractional_bits). If using (min, max, step), format, it is assumed that the minimal fixed-point representation that contains the full range of the quantization interval is used. (e.g., (-3., 3., 1.) is the same as (-4., 3., 1.): both are (1, 2, 0) in fixed point representation). Step **must** be of a power of two.
+    - **Must** cause no overflow if the operation itself does not imply quantization.
+
+The program is executed in the following:
+1. Instantiate a empty buffer of size `len(ops)`.
+2. Go through the list of operations in `ops`. Fill the i-th index of the buffer with the result of the i-th operation: buf[i] = ops[i](buf, inp)
+3. Instantiate the output buffer of size `shape[1]`.
+4. Fill output buffer:
+  - `output_buf[i] = buf[out_idxs[i]] * 2^out_shifts[i] * (-1 if out_negs[i] else 1)`
+
+### OpCode
+The operation codes are defined as follows:
+- `-1`: Copy from input buffer (**implies quantization**)
+  - `buf[i] = input[id0]`
+- `0/1`: Addition/Subtraction
+  - `buf[i] = buf[id0] +/- buf[id1] * 2^data`
+- `2/-2`: ReLU (**implies quantization**)
+  - `buf[i] = quantize(relu(+/- buf[id0]))`
+- `3/-3`: Quantization (**implies quantization**)
+  - `buf[i] = quantize(+/- buf[id0])`
+- `4`: Add a constant
+  - `buf[i] = buf[id0] + data * qint.step`
+- `5`: Define a constant
+  - `buf[i] = data * qint.step`
+- `6/-6`: Mux by MSB
+  - `buf[i] = MSB(buf[int32(data_lower_i32)]) ? buf[id0] : +/- buf[id1] * 2^int32(data_higher_i32)`
+- `*`: Multiplication (**NOT IMPLEMENTED**)
+  - `buf[i] = buf[id0] * buf[id1]`
+
+In all cases, unused id0 or id1 **must** be set to `-1`; id0, id1 (and data for opcode=+/-6) **must** be smaller than the index of the operation itself to ensure causality. All quantization are direct bit-drop in binary format (i.e., WRAP for overflow and TRUNC for rounding).
+
+### Binary Representation
+The binary representation of the program is as follows, in order:
+- `shape`: int32[2]
+- `len(ops)`: int32
+- `inp_shift`: int32[shape[0]]
+- `out_idxs`: int32[shape[1]]
+- `out_shifts`: int32[shape[1]]
+- `out_negs`: int32[shape[1]]
+- `ops`: Op[len(ops)]
+    - `opcode`: int32
+    - `id0`: int32
+    - `id1`: int32
+    - `data_higher`: int32
+    - `data_lower`: int32
+    - `dtype`: int32[3] (only (signed, integer_bits, fractional_bits) format for binary representation)
+
+In execution, the internal buffer **must** have larger bitwidth than the maximum bitwidth appears in any of the operations. When an operation implies quantization, the program **must** apply the quantization explicitly. When an operation does not imply quantization, the program **may** apply quantization and verify no value change is incurred as a result.

da4ml-0.3.0/PKG-INFO

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+Metadata-Version: 2.4
+Name: da4ml
+Version: 0.3.0
+Summary: Digital Arithmetic for Machine Learning
+Author-email: Chang Sun <chsun@cern.ch>
+License: GNU Lesser General Public License v3 (LGPLv3)
+Project-URL: repository, https://github.com/calad0i/da4ml
+Keywords: CMVM,distributed arithmetic,hls4ml,MCM,subexpression elimination
+Classifier: Development Status :: 4 - Beta
+Classifier: License :: OSI Approved :: GNU Lesser General Public License v3 (LGPLv3)
+Classifier: Operating System :: OS Independent
+Classifier: Programming Language :: Python :: 3 :: Only
+Classifier: Programming Language :: Python :: 3.10
+Classifier: Programming Language :: Python :: 3.11
+Classifier: Programming Language :: Python :: 3.12
+Classifier: Programming Language :: Python :: 3.13
+Requires-Python: >=3.10
+Description-Content-Type: text/markdown
+License-File: LICENSE
+Requires-Dist: llvmlite>=0.44
+Requires-Dist: numba>=0.61
+Dynamic: license-file
+
+# da4ml: Distributed Arithmetic for Machine Learning
+
+This project performs Constant Matrix-Vector Multiplication (CMVM) with Distributed Arithmetic (DA) for Machine Learning (ML) on a Field Programmable Gate Arrays (FPGAs).
+
+CMVM optimization is done through greedy CSE of two-term subexpressions, with possible Delay Constraints (DC). The optimization is done in jitted Python (Numba), and a list of optimized operations is generated as traced Python code.
+
+The project generates Verilog or Vitis HLS code for the optimized CMVM operations. This project can be used in conjunction with [`hls4ml`](https://github.com/fastmachinelearning/hls4ml/) for optimizing the neural networks deployed on FPGAs. For a subset of neural networks, the full design can be generated standalone in Verilog or Vitis HLS.
+
+
+## Installation
+
+The project is available on PyPI and can be installed with pip:
+
+```bash
+pip install da4ml
+```
+
+Notice that `numba>=6.0.0` is required for the project to work. The project does not work with `python<3.10`. If the project fails to compile, try upgrading `numba` and `llvmlite` to the latest versions.
+
+## `hls4ml`
+
+The major use of this project is through the `distributed_arithmetic` strategy in the `hls4ml`:
+
+```python
+model_hls = hls4ml.converters.convert_from_keras_model(
+    model,
+    hls_config={
+        'Model': {
+            ...
+            'Strategy': 'distributed_arithmetic',
+        },
+        ...
+    },
+    ...
+)
+```
+
+Currently, `Dense/Conv1D/Conv2D` layers are supported for both `io_parallel` and `io_stream` dataflows. However, notice that distributed arithmetic implies `reuse_factor=1`, as the whole kernel is implemented in combinational logic.
+
+## Standalone usage
+
+### `HGQ2`
+
+For some models trained with `HGQ2`, the `da4ml` can be used to generate the whole model in Verilog or Vitis HLS:
+
+```python
+from da4ml.codegen import HLSModel, VerilogModel
+from da4ml.converter.hgq2.parser import trace_model
+from da4ml.trace import comb_trace
+
+inp, out = trace_model(hgq2_model)
+comb_logic = comb_trace(inp[0], out[0]) # Currently, only models with 1 input and 1 output are supported
+
+# Pipelined Verilog model generation
+# `latency_cutoff` is used to control auto piplining behavior. To disable pipelining, set it to -1.
+verilog_model = VerilogModel(sol, prj_name='barbar', path='/tmp/barbar', latency_cutoff=5)
+verilog_model.compile() # write and verilator binding
+verilog_model.predict(inputs)
+
+vitis_hls_model = HLSModel(sol, prj_name='foo', path='/tmp/foo', flavor='vitis') # Only vitis is supported for now
+vitis_hls_model.compile() # write and hls binding
+vitis_hls_model.predict(inputs)
+```
+
+### Functional Definition
+For generic operations, one can define a combinational logic with the functional API:
+
+```python
+from da4ml.trace import FixedVariableArray, HWConfig, comb_trace
+from da4ml.trace.ops import einsum, relu, quantize, conv, pool
+
+# k, i, f are numpy arrays of integers: keep_negative (0/1), integer bits (excl. sign), fractional bits
+inp = FixedVariableArray.from_kif(k, i, f, HWConfig(1, -1, -1), solver_options={'hard_dc':2})
+out = inp @ kernel
+out = relu(out)
+out = einsum(equation, out, weights)
+...
+
+comb = comb_trace(inp, out)
+```
+
+`+`, `-`, `@` are supported as well as `einsum`, `relu`, `quantize` (WRAP, with TRN or RND), `conv`, `pool` (average only). For multiplications, only power-of-two multipliers are supported, otherwise use `einsum` or `@` operators.
+
+The `comb_trace` returns a `Solution` objects that contains a list of low-level operations that are used to implement the combinational logic, which in turn can be used to generate Verilog or Vitis HLS code.

da4ml-0.3.0/README.md

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+# da4ml: Distributed Arithmetic for Machine Learning
+
+This project performs Constant Matrix-Vector Multiplication (CMVM) with Distributed Arithmetic (DA) for Machine Learning (ML) on a Field Programmable Gate Arrays (FPGAs).
+
+CMVM optimization is done through greedy CSE of two-term subexpressions, with possible Delay Constraints (DC). The optimization is done in jitted Python (Numba), and a list of optimized operations is generated as traced Python code.
+
+The project generates Verilog or Vitis HLS code for the optimized CMVM operations. This project can be used in conjunction with [`hls4ml`](https://github.com/fastmachinelearning/hls4ml/) for optimizing the neural networks deployed on FPGAs. For a subset of neural networks, the full design can be generated standalone in Verilog or Vitis HLS.
+
+
+## Installation
+
+The project is available on PyPI and can be installed with pip:
+
+```bash
+pip install da4ml
+```
+
+Notice that `numba>=6.0.0` is required for the project to work. The project does not work with `python<3.10`. If the project fails to compile, try upgrading `numba` and `llvmlite` to the latest versions.
+
+## `hls4ml`
+
+The major use of this project is through the `distributed_arithmetic` strategy in the `hls4ml`:
+
+```python
+model_hls = hls4ml.converters.convert_from_keras_model(
+    model,
+    hls_config={
+        'Model': {
+            ...
+            'Strategy': 'distributed_arithmetic',
+        },
+        ...
+    },
+    ...
+)
+```
+
+Currently, `Dense/Conv1D/Conv2D` layers are supported for both `io_parallel` and `io_stream` dataflows. However, notice that distributed arithmetic implies `reuse_factor=1`, as the whole kernel is implemented in combinational logic.
+
+## Standalone usage
+
+### `HGQ2`
+
+For some models trained with `HGQ2`, the `da4ml` can be used to generate the whole model in Verilog or Vitis HLS:
+
+```python
+from da4ml.codegen import HLSModel, VerilogModel
+from da4ml.converter.hgq2.parser import trace_model
+from da4ml.trace import comb_trace
+
+inp, out = trace_model(hgq2_model)
+comb_logic = comb_trace(inp[0], out[0]) # Currently, only models with 1 input and 1 output are supported
+
+# Pipelined Verilog model generation
+# `latency_cutoff` is used to control auto piplining behavior. To disable pipelining, set it to -1.
+verilog_model = VerilogModel(sol, prj_name='barbar', path='/tmp/barbar', latency_cutoff=5)
+verilog_model.compile() # write and verilator binding
+verilog_model.predict(inputs)
+
+vitis_hls_model = HLSModel(sol, prj_name='foo', path='/tmp/foo', flavor='vitis') # Only vitis is supported for now
+vitis_hls_model.compile() # write and hls binding
+vitis_hls_model.predict(inputs)
+```
+
+### Functional Definition
+For generic operations, one can define a combinational logic with the functional API:
+
+```python
+from da4ml.trace import FixedVariableArray, HWConfig, comb_trace
+from da4ml.trace.ops import einsum, relu, quantize, conv, pool
+
+# k, i, f are numpy arrays of integers: keep_negative (0/1), integer bits (excl. sign), fractional bits
+inp = FixedVariableArray.from_kif(k, i, f, HWConfig(1, -1, -1), solver_options={'hard_dc':2})
+out = inp @ kernel
+out = relu(out)
+out = einsum(equation, out, weights)
+...
+
+comb = comb_trace(inp, out)
+```
+
+`+`, `-`, `@` are supported as well as `einsum`, `relu`, `quantize` (WRAP, with TRN or RND), `conv`, `pool` (average only). For multiplications, only power-of-two multipliers are supported, otherwise use `einsum` or `@` operators.
+
+The `comb_trace` returns a `Solution` objects that contains a list of low-level operations that are used to implement the combinational logic, which in turn can be used to generate Verilog or Vitis HLS code.

da4ml-0.3.0/interperter/DAISInterpreter.cc

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+#include "DAISInterpreter.hh"
+#include <cstring>
+#include <stdexcept>
+#include <fstream>
+#include <iostream>
+#include <cmath>
+
+namespace dais
+{
+
+    void DAISInterpreter::load_from_binary(const std::vector<int32_t> &binary_data)
+    {
+        n_in = binary_data[0];
+        n_out = binary_data[1];
+        n_ops = binary_data[2];
+        size_t expect_length = 3 + n_in + 3 * n_out + 8 * n_ops;
+        const static size_t d_size = sizeof(int32_t);
+
+        if(binary_data.size() != expect_length)
+            throw std::runtime_error(
+                "Binary data size mismatch: expected " + std::to_string(expect_length * d_size) + "bytes , got " +
+                std::to_string(binary_data.size() * d_size) + " bytes"
+            );
+
+        ops.resize(n_ops);
+        inp_shift.resize(n_in);
+        out_idxs.resize(n_out);
+        out_shifts.resize(n_out);
+        out_negs.resize(n_out);
+
+        std::memcpy(inp_shift.data(), &binary_data[3], n_in * d_size);
+        std::memcpy(out_idxs.data(), &binary_data[3 + n_in], n_out * d_size);
+        std::memcpy(out_shifts.data(), &binary_data[3 + n_in + n_out], n_out * d_size);
+        std::memcpy(out_negs.data(), &binary_data[3 + n_in + 2 * n_out], n_out);
+        std::memcpy(ops.data(), &binary_data[3 + n_in + 3 * n_out], n_ops * 8 * d_size);
+
+        for(const auto &op : ops)
+            {
+                int32_t width = op.dtype.width();
+                if(op.opcode == -1)
+                    max_inp_width = std::max(max_inp_width, width);
+                max_ops_width = std::max(max_ops_width, width);
+            }
+        for(const int32_t &idx : out_idxs)
+            {
+                if(idx >= 0)
+                    max_out_width = std::max(max_out_width, ops[idx].dtype.width());
+            }
+        validate();
+    }
+
+    void DAISInterpreter::load_from_file(const std::string &path)
+    {
+        std::ifstream file(path, std::ios::binary);
+        if(!file)
+            throw std::runtime_error("Failed to open file: " + path);
+
+        std::vector<int32_t> binary_data;
+        file.seekg(0, std::ios::end);
+        size_t file_size = file.tellg();
+        file.seekg(0, std::ios::beg);
+        if(file_size % sizeof(int32_t) != 0)
+            throw std::runtime_error("File size is not a multiple of int32_t size");
+        if(file_size < 3 * sizeof(int32_t))
+            throw std::runtime_error("File size is too small to contain valid DAIS model file");
+        size_t num_elements = file_size / sizeof(int32_t);
+        binary_data.resize(num_elements);
+        file.read(reinterpret_cast<char *>(binary_data.data()), file_size);
+        load_from_binary(binary_data);
+    }
+
+    int64_t DAISInterpreter::shift_add(
+        int64_t v1,
+        int64_t v2,
+        int32_t shift,
+        bool is_minus,
+        const DType &dtype0,
+        const DType &dtype1,
+        const DType &dtype_out
+    ) const
+    {
+        int32_t actual_shift = shift + dtype0.fractionals - dtype1.fractionals;
+        int64_t _v2 = is_minus ? -v2 : v2;
+        if(actual_shift > 0)
+            return v1 + (_v2 << actual_shift);
+        else
+            return (v1 << -actual_shift) + _v2;
+    }
+
+    int64_t DAISInterpreter::quantize(int64_t value, const DType &dtype_from, const DType &dtype_to) const
+    {
+        int32_t shift = dtype_from.fractionals - dtype_to.fractionals;
+        value = value >> shift;
+        int32_t int_max = dtype_to.int_max();
+        int32_t int_min = dtype_to.int_min();
+        const int64_t _mod = 1LL << dtype_to.width();
+        // std::cout << "value = " << value << " (min=" << int_min << ", max=" << int_max << ", mod=" << _mod <<
+        // std::endl;
+        value = ((value - int_min + (std::abs(value) / _mod + 1) * _mod) % _mod) + int_min;
+        return value;
+    }
+
+    int64_t DAISInterpreter::relu(int64_t value, const DType &dtype_from, const DType &dtype_to) const
+    {
+        if(value < 0)
+            return 0;
+        return quantize(value, dtype_from, dtype_to);
+    }
+
+    int64_t
+    DAISInterpreter::const_add(int64_t value, DType dtype_from, DType dtype_to, int32_t data_high, int32_t data_low)
+        const
+    {
+        const int32_t _shift = dtype_to.fractionals - dtype_from.fractionals;
+        int64_t data = (static_cast<int64_t>(data_high) << 32) | static_cast<uint32_t>(data_low);
+        // std::cout << "v=" << value << " c=" << data << " shift=" << _shift << std::endl;
+        return (value << _shift) + data;
+    }
+
+    bool DAISInterpreter::get_msb(int64_t value, const DType &dtype) const
+    {
+        if(dtype.is_signed)
+            return value < 0;
+        return value >= (1LL << (dtype.width() - 2));
+    }
+
+    int64_t DAISInterpreter::msb_mux(
+        int64_t v0,
+        int64_t v1,
+        int64_t v_cond,
+        int32_t _shift,
+        const DType &dtype0,
+        const DType &dtype1,
+        const DType &dtype_cond,
+        const DType &dtype_out
+    ) const
+    {
+        bool cond = get_msb(v_cond, dtype_cond);
+        int32_t shift = dtype0.fractionals - dtype1.fractionals + _shift;
+        int64_t shifted_v0 = shift > 0 ? v0 : (v0 << -shift);
+        int64_t shifted_v1 = shift > 0 ? (v1 << shift) : v1;
+        if(cond)
+            return shifted_v0;
+        else
+            return shifted_v1;
+    }
+
+    std::vector<int64_t> DAISInterpreter::exec_ops(const std::vector<double> &inputs)
+    {
+        if(inputs.size() != n_in)
+            throw std::runtime_error(
+                "Input size mismatch: expected " + std::to_string(n_in) + ", got " + std::to_string(inputs.size())
+            );
+
+        std::vector<int64_t> buffer(n_ops);
+        std::vector<int64_t> output_buffer(n_out);
+
+        for(size_t i = 0; i < n_ops; ++i)
+            {
+                const Op &op = ops[i];
+                switch(op.opcode)
+                    {
+                        case -1: {
+                            int64_t input_value = static_cast<int64_t>(
+                                std::floor(inputs[op.id0] * std::pow(2.0, inp_shift[op.id0] + ops[i].dtype.fractionals))
+                            );
+                            buffer[i] = quantize(input_value, op.dtype, op.dtype);
+                            break;
+                        }
+                    case 0:
+                    case 1:
+                        buffer[i] = shift_add(
+                            buffer[op.id0],
+                            buffer[op.id1],
+                            op.data_low,
+                            op.opcode == 1,
+                            ops[op.id0].dtype,
+                            ops[op.id1].dtype,
+                            ops[i].dtype
+                        );
+                        break;
+                    case 2:
+                    case -2:
+                        buffer[i] =
+                            relu(op.opcode == -2 ? -buffer[op.id0] : buffer[op.id0], ops[op.id0].dtype, ops[i].dtype);
+                        break;
+                    case 3:
+                    case -3:
+                        buffer[i] = quantize(
+                            op.opcode == -3 ? -buffer[op.id0] : buffer[op.id0], ops[op.id0].dtype, ops[i].dtype
+                        );
+                        break;
+                    case 4:
+                        buffer[i] =
+                            const_add(buffer[op.id0], ops[op.id0].dtype, ops[i].dtype, op.data_high, op.data_low);
+                        break;
+                    case 5:
+                        buffer[i] = static_cast<int64_t>(op.data_high) << 32 | static_cast<uint32_t>(op.data_low);
+                        break;
+                    case 6:
+                    case -6:
+                        buffer[i] = msb_mux(
+                            buffer[op.id0],
+                            op.opcode == -6 ? -buffer[op.id1] : buffer[op.id1],
+                            buffer[op.data_low],
+                            op.data_high,
+                            ops[op.id0].dtype,
+                            ops[op.id1].dtype,
+                            ops[op.data_low].dtype,
+                            ops[i].dtype
+                        );
+                        break;
+                    default:
+                        throw std::runtime_error(
+                            "Unknown opcode: " + std::to_string(op.opcode) + " at index " + std::to_string(i)
+                        );
+                    }
+            }
+        for(size_t i = 0; i < n_out; ++i)
+            output_buffer[i] = out_idxs[i] >= 0 ? buffer[out_idxs[i]] : 0;
+        return output_buffer;
+    }
+
+    std::vector<double> DAISInterpreter::inference(const std::vector<double> &inputs)
+    {
+        std::vector<int64_t> int_outputs = exec_ops(inputs);
+        std::vector<double> outputs(n_out);
+        for(size_t i = 0; i < n_out; ++i)
+            {
+                const int64_t tmp = out_negs[i] ? -int_outputs[i] : int_outputs[i];
+                outputs[i] =
+                    static_cast<double>(tmp) * std::pow(2.0, out_shifts[i] - ops[out_idxs[i]].dtype.fractionals);
+            }
+
+        return outputs;
+    }
+
+    void DAISInterpreter::print_program_info() const
+    {
+        size_t bits_in = 0, bits_out = 0;
+        for(int32_t i = 0; i < n_ops; ++i)
+            {
+                const Op op = ops[i];
+                if(op.opcode == -1)
+                    bits_in += op.dtype.width();
+            }
+        for(int32_t i = 0; i < n_out; ++i)
+            {
+                if(out_idxs[i] >= 0)
+                    bits_out += ops[out_idxs[i]].dtype.width();
+            }
+        std::cout << "DAIS Sequence:\n";
+        std::cout << n_in << " (" << bits_in << " bits) -> " << n_out << " (" << bits_out << " bits)\n";
+        std::cout << "# operations: " << n_ops << "\n";
+        std::cout << "Maximum intermediate width: " << max_ops_width << " bits\n";
+    }
+
+    void DAISInterpreter::validate() const
+    {
+        for(int32_t i = 0; i < n_ops; ++i) // Causality check
+            {
+                const Op &op = ops[i];
+                if(op.id0 >= i && op.opcode != -1)
+                    throw std::runtime_error(
+                        "Operation " + std::to_string(i) + " has id0=" + std::to_string(op.id0) + "violating causality"
+                    );
+                if(op.id1 >= i)
+                    throw std::runtime_error(
+                        "Operation " + std::to_string(i) + " has id1=" + std::to_string(op.id1) + " violating causality"
+                    );
+                if(abs(op.opcode) == 6 && op.data_low >= i)
+                    throw std::runtime_error(
+                        "Operation " + std::to_string(i) + " has cond_idx=" + std::to_string(op.data_low) +
+                        " violating causality"
+                    );
+            }
+
+        if(max_inp_width > 32 || max_out_width > 32)
+            {
+                std::cerr << "Warning: max_inp_width=" << max_inp_width << " or max_out_width=" << max_out_width
+                          << " exceeds 32 bits, which may cause issues with the Verilator binder.\n";
+            }
+        if(max_ops_width > 64)
+            {
+                std::cerr << "Warning: max_ops_width=" << max_ops_width
+                          << " exceeds 64 bits. This may comppromise bit-exactness of the interpreter.\n"
+                          << "This high wdith is very unusual for a properly quantized network, so you may want to "
+                             "check your "
+                             "model.\n";
+            }
+    }
+} // namespace dais
+
+extern "C"
+{
+    void run_interp(int32_t *data, double *inputs, double *outputs, size_t n_copy)
+    {
+        int32_t n_in = data[0];
+        int32_t n_out = data[1];
+        int32_t n_ops = data[2];
+        size_t size = 3 + n_in + 3 * n_out + 8 * n_ops;
+        std::vector<int32_t> binary_data(data, data + size);
+        dais::DAISInterpreter interp;
+        interp.load_from_binary(binary_data);
+        interp.print_program_info();
+
+        for(size_t i = 0; i < n_copy; ++i)
+            {
+                std::vector<double> inp_vec(inputs + i * n_in, inputs + (i + 1) * n_in);
+                auto ret = interp.inference(inp_vec);
+                memcpy(&outputs[i * n_out], ret.data(), n_out * sizeof(double));
+            }
+    }
+}