cimo 0.0.2__tar.gz → 0.0.3__tar.gz

cimo-0.0.3/LICENSE

@@ -0,0 +1,21 @@
+MIT License
+
+Copyright (c) 2026 Fariz Rahman
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in all
+copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+SOFTWARE.

{cimo-0.0.2 → cimo-0.0.3}/PKG-INFO

@@ -1,6 +1,6 @@
 Metadata-Version: 2.4
 Name: cimo
-Version: 0.0.2
+Version: 0.0.3
 Summary: A C compiler written in pure Python: C kernels in, machine code out.
 Author: Fariz Rahman
 License: MIT
@@ -11,17 +11,19 @@ Classifier: Topic :: Software Development :: Compilers
 Classifier: License :: OSI Approved :: MIT License
 Requires-Python: >=3.9
 Description-Content-Type: text/markdown
+License-File: LICENSE
 Provides-Extra: dev
 Requires-Dist: pytest; extra == "dev"
 Requires-Dist: black; extra == "dev"
 Requires-Dist: isort; extra == "dev"
 Requires-Dist: numpy; extra == "dev"
 Requires-Dist: mypy; extra == "dev"
+Dynamic: license-file
 
 # cimo
 
-A C compiler written in pure Python: compile freestanding C kernels at runtime and call them on
-your numpy arrays, with no compiler, SDK or native dependency on the machine.
+A C compiler written in pure Python: compile C kernels at runtime and call them on your numpy
+arrays, with no compiler, SDK or native dependency on the machine.
 
 See the [project README](https://github.com/farizrahman4u/cimo#readme).
 

cimo-0.0.3/README.md

@@ -0,0 +1,8 @@
+# cimo
+
+A C compiler written in pure Python: compile C kernels at runtime and call them on your numpy
+arrays, with no compiler, SDK or native dependency on the machine.
+
+See the [project README](https://github.com/farizrahman4u/cimo#readme).
+
+Development install, from this directory: `pip install -e '.[dev]'`

{cimo-0.0.2 → cimo-0.0.3}/cimo/__init__.py

@@ -2,4 +2,4 @@
 
 from .driver import compile, load, Module, CompileError, KernelError
 
-__version__ = "0.0.2"
+__version__ = "0.0.3"

{cimo-0.0.2 → cimo-0.0.3}/cimo/assembler.py

@@ -935,7 +935,8 @@ _NEON2 = {'neg': (0x6e20b800, 's'), 'fneg': (0x6ea0f800, 'f'), 'fabs': (0x4ea0f8
           'mvn': (0x6e205800, '')}
 _NEONSH = {'shl': 0x4f005400, 'ushr': 0x6f000400, 'sshr': 0x4f000400}
 _LANES = {'16b': 0, '8h': 1, '4s': 2, '2d': 3}
-_VREG = re.compile(r'v(\d+)\.(16b|8h|4s|2d)$')
+_NEONW = {'saddw': 0x0ea01000, 'saddw2': 0x4ea01000, 'uaddw': 0x2ea01000, 'uaddw2': 0x6ea01000}  # 2d, 2d, 2s or 4s
+_VREG = re.compile(r'v(\d+)\.(16b|8h|4s|2d|2s)$')
 _VELEM = re.compile(r'v(\d+)\.([bhsd])\[(\d+)\]$')
 
 
@@ -953,10 +954,14 @@ def _v(s):
 def _neon(mn, ops):
     """The word of a NEON instruction whose first operand is a vector register."""
     d, lane = _v(ops[0])
-    size = _LANES[lane]
+    size = _LANES.get(lane, 2)
     if mn == 'mov':
         n, _ = _v(ops[1])
         return 0x4ea01c00 | n << 16 | n << 5 | d
+    if mn in _NEONW:
+        n, _ = _v(ops[1])
+        m, _ = _v(ops[2])
+        return _NEONW[mn] | m << 16 | n << 5 | d
     if mn == 'dup':
         s = ops[1].strip().lower()
         e = _VELEM.match(s)

{cimo-0.0.2 → cimo-0.0.3}/cimo/assembler_amd64.py

@@ -962,6 +962,36 @@ def _h_round(a, ops, sz, op):
          imm=(1, None, v, None))
 
 
+def _h_sseimm(a, ops, sz, arg):
+    """$imm, xmm/mem -> xmm: arg = (mandatory prefix, opcode)."""
+    _nops(ops, 3)
+    imm, src, dst = ops
+    sym, v = _immop(imm, 1)
+    if sym is not None:
+        raise AssemblerError('expected a constant')
+    _enc(a, arg[1], _xmm(dst), _xmm(src, True), 0, mand=arg[0], imm=(1, None, v, None))
+
+
+def _h_pshift(a, ops, sz, arg):
+    """$imm, xmm: arg = (opcode, /digit)."""
+    _nops(ops, 2)
+    imm, dst = ops
+    sym, v = _immop(imm, 1)
+    if sym is not None:
+        raise AssemblerError('expected a constant')
+    _enc(a, bytes([0x0f, arg[0]]), arg[1], _xmm(dst), 0, mand=b'\x66', imm=(1, None, v, None))
+
+
+def _h_pextrw(a, ops, sz, _):
+    _nops(ops, 3)
+    imm, src, dst = ops
+    sym, v = _immop(imm, 1)
+    if sym is not None or src[0] != 'x':
+        raise AssemblerError('bad operands')
+    _gpr(dst, (4, 8))
+    _enc(a, b'\x0f\xc5', dst, src, 0, mand=b'\x66', imm=(1, None, v, None))
+
+
 # mnemonic table: name -> (handler, suffix size, argument)
 
 _SFX = {'b': 1, 'w': 2, 'l': 4, 'q': 8}
@@ -1054,6 +1084,18 @@ for _n, _p, _op in (('andps', b'', 0x54), ('andpd', b'\x66', 0x54), ('andnps', b
                     ('unpcklpd', b'\x66', 0x14), ('cvtps2pd', b'', 0x5a),
                     ('cvtpd2ps', b'\x66', 0x5a)):
     _INSNS[_n] = (_h_sse, 0, (_p, bytes([0x0f, _op])))
+for _n, _op in (('paddb', 0xfc), ('paddw', 0xfd), ('paddd', 0xfe), ('paddq', 0xd4), ('psubb', 0xf8), ('psubw', 0xf9),
+                ('psubd', 0xfa), ('psubq', 0xfb), ('pmullw', 0xd5), ('pmuludq', 0xf4), ('pcmpeqb', 0x74), ('pcmpeqw', 0x75),
+                ('pcmpeqd', 0x76), ('pcmpgtb', 0x64), ('pcmpgtw', 0x65), ('pcmpgtd', 0x66), ('pminub', 0xda), ('pmaxub', 0xde),
+                ('pminsw', 0xea), ('pmaxsw', 0xee), ('pandn', 0xdf), ('punpcklbw', 0x60), ('punpcklwd', 0x61),
+                ('punpckldq', 0x62), ('punpckhdq', 0x6a), ('punpcklqdq', 0x6c)):
+    _INSNS[_n] = (_h_sse, 0, (b'\x66', bytes([0x0f, _op])))
+for _n, _p, _o in (('pshufd', b'\x66', 0x70), ('pshuflw', b'\xf2', 0x70), ('cmpps', b'', 0xc2), ('cmppd', b'\x66', 0xc2)):
+    _INSNS[_n] = (_h_sseimm, 0, (_p, bytes([0x0f, _o])))
+for _n, _op, _d in (('psllw', 0x71, 6), ('pslld', 0x72, 6), ('psllq', 0x73, 6), ('psrlw', 0x71, 2), ('psrld', 0x72, 2),
+                    ('psrlq', 0x73, 2), ('psraw', 0x71, 4), ('psrad', 0x72, 4)):
+    _INSNS[_n] = (_h_pshift, 0, (_op, _d))
+_INSNS['pextrw'] = (_h_pextrw, 0, None)
 for _n, _p, _ld, _st in (('movss', b'\xf3', 0x10, 0x11), ('movsd', b'\xf2', 0x10, 0x11),
                          ('movups', b'', 0x10, 0x11), ('movupd', b'\x66', 0x10, 0x11),
                          ('movaps', b'', 0x28, 0x29), ('movapd', b'\x66', 0x28, 0x29),

{cimo-0.0.2 → cimo-0.0.3}/cimo/backend/amd64/emit.py

@@ -141,6 +141,11 @@ omap = [
     (Oxcmp, Kd, "ucomisd %D0, %D1"),
     (Oxcmp, Ki, "cmp%k %0, %1"),
     (Oxtest, Ki, "test%k %0, %1"),
+    (D.Oxaddm, Ki, "add%k %0, %M1"),
+    (D.Oxsubm, Ki, "sub%k %0, %M1"),
+    (D.Oxandm, Ki, "and%k %0, %M1"),
+    (D.Oxorm, Ki, "or%k %0, %M1"),
+    (D.Oxxorm, Ki, "xor%k %0, %M1"),
 ]
 omap += [(Oflag + c, Ki, "set" + s + " %B=\n\tmovzb%k %B=, %=") for c, s, _ in _CMP]
 omap += [
@@ -232,6 +237,19 @@ def getarg(c, i):
         die("invalid arg letter %c", c)
 
 
+_FALSEDEP = frozenset((Ofsqrt, Oswtof, Osltof, Oexts, Otruncd))
+
+
+def _xreg(r):
+    return rtype(r) == RTmp and isreg(r) and rval(r) >= XMM0
+
+
+def _xcopy(to, a, e):
+    """cimo: movss and movsd between registers keep the destination's upper bits, so they wait for what last wrote it,
+    which behind a division or a square root is most of the loop (nbody_acc on Intel). movaps doesn't, as gcc and clang."""
+    e.f.write("\tmovaps %%xmm%d, %%xmm%d\n" % (rval(a) - XMM0, rval(to) - XMM0))
+
+
 def emitcopy(r1, r2, k, e):
     icp = Ins(Ocopy, k, r1, r2)
     emitins(icp, e)
@@ -369,11 +387,161 @@ def _table(i, e):
     die("no match for %s(%c)", optab[i.op].name, "wlsd"[i.cls])
 
 
+_QX15 = "%xmm15"
+# (mnemonic, commutes). Two addresses: dest = dest op source
+_QTWO = {'qaddb': ('paddb', 1), 'qaddh': ('paddw', 1), 'qaddw': ('paddd', 1), 'qaddl': ('paddq', 1),
+         'qadds': ('addps', 1), 'qaddd': ('addpd', 1), 'qsubb': ('psubb', 0), 'qsubh': ('psubw', 0),
+         'qsubw': ('psubd', 0), 'qsubl': ('psubq', 0), 'qsubs': ('subps', 0), 'qsubd': ('subpd', 0),
+         'qmulh': ('pmullw', 1), 'qmuls': ('mulps', 1), 'qmuld': ('mulpd', 1), 'qdivs': ('divps', 0), 'qdivd': ('divpd', 0),
+         'qand': ('pand', 1), 'qor': ('por', 1), 'qxor': ('pxor', 1), 'qxandn': ('pandn', 0),
+         'qminh': ('pminsw', 1), 'qmaxh': ('pmaxsw', 1), 'qumin' + 'b': ('pminub', 1), 'qumaxb': ('pmaxub', 1),
+         'qceqb': ('pcmpeqb', 1), 'qceqh': ('pcmpeqw', 1), 'qceqw': ('pcmpeqd', 1),
+         'qcgtb': ('pcmpgtb', 0), 'qcgth': ('pcmpgtw', 0), 'qcgtw': ('pcmpgtd', 0),
+         'qxmuludq': ('pmuludq', 1), 'qxlo': ('punpckldq', 0), 'qxhi': ('punpckhdq', 0),
+         'qxmins': ('minps', 0), 'qxmind': ('minpd', 0), 'qxmaxs': ('maxps', 0), 'qxmaxd': ('maxpd', 0),
+         'qceqs': ('cmpps $0,', 1), 'qceqd': ('cmppd $0,', 1), 'qxunords': ('cmpps $3,', 1), 'qxunordd': ('cmppd $3,', 1)}
+_QSWAPPED = {'qcgts': 'cmpps $1,', 'qcgtd': 'cmppd $1,', 'qcges': 'cmpps $2,', 'qcged': 'cmppd $2,'}  # b < a, b <= a
+_QSHIFT = {'qshlh': 'psllw', 'qshlw': 'pslld', 'qshll': 'psllq', 'qshrh': 'psrlw', 'qshrw': 'psrld', 'qshrl': 'psrlq',
+           'qsarh': 'psraw', 'qsarw': 'psrad'}
+
+
+def _qx(r):
+    return "%%xmm%d" % (rval(r) - XMM0)
+
+
+def _qr(r, sz):
+    return "%%%s" % regtoa(rval(r), sz)
+
+
+def _qtwo(mn, to, a, b, commutes, f):
+    """to = a op b, in two addresses, through xmm15 if b is in the way."""
+    if to == b and to != a:
+        if commutes:
+            a, b = b, a
+        else:
+            f.write("\tmovaps %s, %s\n\tmovaps %s, %s\n" % (_qx(b), _QX15, _qx(a), _qx(to)))
+            f.write("\t%s %s, %s\n" % (mn, _QX15, _qx(to)))
+            return
+    if to != a:
+        f.write("\tmovaps %s, %s\n" % (_qx(a), _qx(to)))
+    f.write("\t%s %s, %s\n" % (mn, _qx(b), _qx(to)))
+
+
+def _qcopy(i, e):
+    f = e.f
+    to, a = i.to, i.arg[0]
+    if to == R or a == R or to == a:
+        return
+    if rtype(to) == RSlot and rtype(a) == RSlot:
+        f.write("\tmovups %d(%%%s), %s\n" % (slot(a, e), regtoa(e.fp, SLong), _QX15))
+        f.write("\tmovups %s, %d(%%%s)\n" % (_QX15, slot(to, e), regtoa(e.fp, SLong)))
+    elif rtype(to) == RSlot:
+        emitf("movups %0, %M=", i, e)
+    elif rtype(a) == RSlot:
+        emitf("movups %M0, %=", i, e)
+    else:
+        f.write("\tmovaps %s, %s\n" % (_qx(a), _qx(to)))
+
+
+def _qins(i, e):
+    """cimo (ext.vector): one instruction on 128 bits; amd64/qlower.py has left only those SSE2 has. True if it was one."""
+    f = e.f
+    op = i.op
+    if op == Ocopy and i.cls == D.Kq:
+        _qcopy(i, e)
+        return True
+    if op == Oswap and i.cls == D.Kq:
+        a, b = _qx(i.arg[0]), _qx(i.arg[1])
+        f.write("\tmovaps %s, %s\n\tmovaps %s, %s\n\tmovaps %s, %s\n" % (a, _QX15, b, a, _QX15, b))
+        return True
+    if (op == Oload and i.cls == D.Kq) or op == D.Oqload:
+        emitf("movups %M0, %=", i, e)
+        return True
+    if op == D.Oqstore:
+        emitf("movups %0, %M1", i, e)
+        return True
+    if not D.isqop(op):
+        return False
+    name = optab[op].name
+    if name in _QTWO:
+        mn, commutes = _QTWO[name]
+        _qtwo(mn, i.to, i.arg[0], i.arg[1], commutes, f)
+    elif name in _QSWAPPED:
+        _qtwo(_QSWAPPED[name], i.to, i.arg[1], i.arg[0], 0, f)
+    elif name in _QSHIFT:
+        if i.to != i.arg[0]:
+            f.write("\tmovaps %s, %s\n" % (_qx(i.arg[0]), _qx(i.to)))
+        f.write("\t%s $%d, %s\n" % (_QSHIFT[name], e.fn.con[rval(i.arg[1])].i, _qx(i.to)))
+    elif name == 'qxshufd':
+        f.write("\tpshufd $%d, %s, %s\n" % (e.fn.con[rval(i.arg[1])].i, _qx(i.arg[0]), _qx(i.to)))
+    elif name in ('qsqrts', 'qsqrtd'):
+        f.write("\tsqrtp%s %s, %s\n" % (name[-1], _qx(i.arg[0]), _qx(i.to)))
+    elif name.startswith('qdup'):
+        _qdup(name[-1], i, e)
+    elif name.startswith('qget'):
+        _qget(name[-1], i, e)
+    else:
+        die("no x86-64 instruction for %s", name)
+    return True
+
+
+def _qdup(x, i, e):
+    f = e.f
+    to = _qx(i.to)
+    a = i.arg[0]
+    if rtype(a) == RCon:  # isel: 0 and -1 only
+        f.write("\t%s %s, %s\n" % ("pxor" if e.fn.con[rval(a)].i == 0 else "pcmpeqd", to, to))
+    elif x in 'sd':
+        f.write("\tpshufd $%d, %s, %s\n" % (0 if x == 's' else 0x44, _qx(a), to))
+    elif x == 'l':
+        f.write("\tmovq %s, %s\n\tpunpcklqdq %s, %s\n" % (_qr(a, SLong), to, to, to))
+    else:
+        f.write("\tmovd %s, %s\n" % (_qr(a, SWord), to))
+        if x == 'b':
+            f.write("\tpunpcklbw %s, %s\n" % (to, to))
+        if x in 'bh':
+            f.write("\tpshuflw $0, %s, %s\n" % (to, to))
+        f.write("\tpshufd $0, %s, %s\n" % (to, to))
+
+
+def _qget(x, i, e):
+    f = e.f
+    n = e.fn.con[rval(i.arg[1])].i
+    a = _qx(i.arg[0])
+    if x == 's':
+        f.write("\tpshufd $%d, %s, %s\n" % (n, a, _qx(i.to)))
+    elif x == 'd':
+        f.write("\tpshufd $%d, %s, %s\n" % (0xee if n else 0x44, a, _qx(i.to)))
+    elif x == 'w':
+        if n:
+            f.write("\tpshufd $%d, %s, %s\n" % (n, a, _QX15))
+            a = _QX15
+        f.write("\tmovd %s, %s\n" % (a, _qr(i.to, SWord)))
+    elif x == 'l':
+        if n:
+            f.write("\tpshufd $238, %s, %s\n" % (a, _QX15))
+            a = _QX15
+        f.write("\tmovq %s, %s\n" % (a, _qr(i.to, SLong)))
+    elif x == 'h':
+        f.write("\tpextrw $%d, %s, %s\n" % (n, a, _qr(i.to, SWord)))
+    else:
+        f.write("\tpextrw $%d, %s, %s\n" % (n >> 1, a, _qr(i.to, SWord)))
+        if n & 1:
+            f.write("\tshrl $8, %s\n" % _qr(i.to, SWord))
+        else:
+            f.write("\tmovzbl %s, %s\n" % (_qr(i.to, SByte), _qr(i.to, SWord)))
+
+
 def emitins(i, e):
     """i: passed by value (copied here)."""
     i = i.copy()
     f = e.f
     op = i.op
+    if (i.cls == D.Kq or D.isqop(op)) and _qins(i, e):
+        return
+    if op in _FALSEDEP and _xreg(i.to) and i.to != i.arg[0]:  # as _xcopy: these keep the upper bits too, as gcc's pxor
+        x = rval(i.to) - XMM0
+        f.write("\txorps %%xmm%d, %%xmm%d\n" % (x, x))
     if op == Onop:
         # just do nothing for nops, they are inserted
         # by some passes
@@ -402,7 +570,7 @@ def emitins(i, e):
             _table(i, e)
     elif op == Oneg:
         if i.to != i.arg[0]:
-            emitf("mov%k %0, %=", i, e)
+            emitcopy(i.to, i.arg[0], i.cls, e)
         if KBASE(i.cls) == 0:
             emitf("neg%k %=", i, e)
         else:
@@ -414,8 +582,8 @@ def emitins(i, e):
         # conversion to 2-address in emitf() would fail
         if i.to == i.arg[1]:
             i.arg[1] = TMP(XMM0 + 15)
-            emitf("mov%k %=, %1", i, e)
-            emitf("mov%k %0, %=", i, e)
+            emitcopy(i.arg[1], i.to, i.cls, e)
+            emitcopy(i.to, i.arg[0], i.cls, e)
             i.arg[0] = i.to
         _table(i, e)
     elif op == Ocopy:
@@ -448,6 +616,9 @@ def emitins(i, e):
             emitf("mov%k %0, %1", i, e)
             emitf("mov%k %1, %=", i, e)
             return
+        if _xreg(i.to) and _xreg(i.arg[0]):
+            _xcopy(i.to, i.arg[0], e)
+            return
         # conveniently, the assembler knows if it
         # should use movabsq when reading movq
         emitf("mov%k %0, %=", i, e)
@@ -545,7 +716,7 @@ def emitins(i, e):
         emitf("sqrt%k %0, %=", i, e)
     elif op == Ofabs:
         if i.to != i.arg[0]:
-            emitf("mov%k %0, %=", i, e)
+            emitcopy(i.to, i.arg[0], i.cls, e)
         f.write("\tandp%c %sfp%d(%%rip), %%%s\n" % (
             "xxsd"[i.cls], D.T.asloc, stashbits(absmask[i.cls], 16),
             regtoa(rval(i.to), SLong)))
@@ -596,6 +767,8 @@ def _usesxmm15(fn):
     b = fn.start
     while b:
         for i in b.ins[:b.nins]:
+            if i.cls == D.Kq or D.isqop(i.op):  # ext.vector: moves, lanes, operands in the way
+                return True
             if i.op == Odiv and KBASE(i.cls) == 1 and i.to == i.arg[1]:
                 return True
             if i.op == Ocopy and rtype(i.to) == RSlot and rtype(i.arg[0]) in (RSlot, RMem):
@@ -710,7 +883,8 @@ def _emitjmp(b, fn, e, id0, rclob, nclr, win):
     else:
         c = jt - Jjf
         if 0 <= c <= NCmp:
-            if b.link is b.s2 or (win and c >= NCmpI):
+            # cimo: a loop's back edge is the conditional jump, not a jump after one that's rarely taken
+            if b.link is b.s2 or (win and c >= NCmpI) or (b.s1 is not b.link and b.s1.id <= b.id < b.s2.id):
                 s = b.s1
                 b.s1 = b.s2
                 b.s2 = s

{cimo-0.0.2 → cimo-0.0.3}/cimo/backend/amd64/isel.py

@@ -129,12 +129,22 @@ def fixarg(lst, idx, k, i, fn):
             r2 = newtmp("isel", Kl, fn)
             cc = Con(CBits, c.i)
             r3 = newcon(cc, fn)
-            if noimm(r3, fn):  # fix over C QBE: an add's immediate is 32 bits
+            # fix over C QBE: lea, not add. For a phi's argument this comes after the block's last instruction, between
+            # a compare and the jump that reads its flags (YARPGen: extern_array + 4 went the wrong way, then crashed)
+            a = Addr()
+            a.base = r2
+            if noimm(r3, fn):  # an address's offset is 32 bits
                 r4 = newtmp("isel", Kl, fn)
-                emit(Oadd, Kl, r1, r2, r4)
-                emit(Ocopy, Kl, r4, r3, R)
+                a.index = r4
+                a.scale = 1
             else:
-                emit(Oadd, Kl, r1, r2, r3)
+                a.offset = cc
+            fn.nmem += 1
+            vgrow(fn.mem, fn.nmem, Addr)
+            fn.mem[fn.nmem - 1] = a
+            emit(Oaddr, Kl, r1, MEM(fn.nmem - 1), R)
+            if noimm(r3, fn):
+                emit(Ocopy, Kl, r4, r3, R)
         else:
             r2 = r1
         if D.T.apple and (c.sym.type & SThr):
@@ -275,7 +285,9 @@ def sel(i, tn, fn):
     i0 = D.curi
     k = i.cls
     op = i.op
-    if op in (Odiv, Orem, Oudiv, Ourem):
+    if D.isqop(op):
+        _qsel(i, tn, fn)
+    elif op in (Odiv, Orem, Oudiv, Ourem):
         if KBASE(k) == 1:
             _emit_fix(i, fn)
         else:
@@ -403,6 +415,9 @@ def sel(i, tn, fn):
             fixarg(ci.arg, 0, Kl, ci, fn)
     elif op == Onop:
         pass
+    elif op in _RMW.values():
+        seladdr(i.arg, 1, tn, fn)
+        _emit_fix(i, fn)
     elif op in (Ostored, Ostores, Ostorel, Ostorew, Ostoreh, Ostoreb):
         if rtype(i.arg[0]) == RCon:
             if i.op == Ostored:
@@ -481,6 +496,35 @@ _EXTINT = frozenset((D.Obclz, D.Obctz, D.Obswap, D.Obswap16))
 _EXTOPS = _EXTINT | frozenset((D.Ogetsp, D.Osetsp, D.Ofsqrt, D.Ofabs))
 
 
+def _qsel(i, tn, fn):
+    """cimo (ext.vector): registers, a whole addressing mode, and a constant for shifts, shuffles and lanes."""
+    op = i.op
+    if op == D.Oqload:
+        seladdr(i.arg, 0, tn, fn)
+    elif op == D.Oqstore:
+        seladdr(i.arg, 1, tn, fn)
+    if D.Oqdupb <= op <= D.Oqdupd and rtype(i.arg[0]) == RCon:
+        c = fn.con[rval(i.arg[0])]
+        if c.type == CBits and c.i in (0, -1) and op not in (D.Oqdups, D.Oqdupd):
+            emiti(i)  # pxor, pcmpeqd
+            return
+        k = argcls(i, 0)
+        r = newtmp("isel", k, fn)
+        a = i.arg[0]
+        i.arg[0] = r
+        emiti(i)
+        emit(Ocopy, k, r, a, R)
+        ci = D.insb[D.curi]
+        fixarg(ci.arg, 0, k, ci, fn)
+        return
+    emiti(i)
+    i1 = D.insb[D.curi]
+    keep1 = D.Oqshlb <= op <= D.Oqsarl or D.Oqgetb <= op <= D.Oqgetd or op == D.Oqxshufd
+    fixarg(i1.arg, 0, argcls(i, 0), i1, fn)
+    if i1.arg[1] != R and argcls(i, 1) != D.Kx and not keep1:
+        fixarg(i1.arg, 1, argcls(i, 1), i1, fn)
+
+
 def _emit_fix(i, fn):
     emiti(i)
     _fix2(i, fn)
@@ -523,6 +567,15 @@ def selsel(fn, b, i, tn):
         isel0 -= 1
     assert ins[isel0].op == Osel0
     r = ins[isel0].arg[0]
+    if rtype(r) == RCon:  # cimo: the middle end's if-conversion, its condition folded since: copies
+        yes = fn.con[rval(r)].type != CBits or fn.con[rval(r)].i != 0
+        isel1 = i
+        while isel0 < isel1:
+            x = ins[isel1]
+            sel(Ins(Ocopy, x.cls, x.to, x.arg[0] if yes else x.arg[1], R), tn, fn)
+            isel1 -= 1
+        ins[isel0] = Ins(Onop)
+        return isel0
     assert rtype(r) == RTmp
     t = fn.tmp[rval(r)]
     fi = flagi(ins, 0, isel0, fn)
@@ -866,6 +919,76 @@ def amatch(a, tn, r, fn):
     return 1
 
 
+_RMW = {Oadd: D.Oxaddm, Osub: D.Oxsubm, Oand: D.Oxandm, Oor: D.Oxorm, Oxor: D.Oxxorm}
+# an extension to 64 bits: the loads of a word it can be, and the load that does both. A 32-bit load is any of three, its
+# extension says which half it means
+_W = (Oload, D.Oloadsw, D.Oloaduw)
+_ZEXT = {D.Oextub: ((D.Oloadub,), D.Oloadub), D.Oextuh: ((D.Oloaduh,), D.Oloaduh), D.Oextuw: (_W, D.Oloaduw),
+         D.Oextsb: ((D.Oloadsb,), D.Oloadsb), D.Oextsh: ((D.Oloadsh,), D.Oloadsh), D.Oextsw: (_W, D.Oloadsw)}
+
+
+def _writes(op):
+    """Whether op may write memory."""
+    return isstore(op) or op in _RMW.values() or op in (Ocall, D.Oblit0, D.Oblit1, D.Ovastart, D.Oqstore)
+
+
+def _loadsfold(fn):
+    """cimo: what x86-64 does in the load or the store itself, as gcc. A load extended to 64 bits extends to 64 bits
+    (movzbl and then movzbq of its byte: 8.8 to 7.2 ms on Zen 4's histogram). A load, an operation on it and a store
+    of the result to the same address, nothing in between that may write memory, are one instruction (addl $1, (mem):
+    5.9 ms, gcc's 6.3). Needs use counts."""
+    tmp = fn.tmp
+    b = fn.start
+    while b:
+        ins = b.ins[:b.nins]
+        defs = {}
+        for k, i in enumerate(ins):
+            if rtype(i.to) == RTmp:
+                defs[rval(i.to)] = k
+        for k, i in enumerate(ins):
+            if i.op in _ZEXT and i.cls == Kl and rtype(i.arg[0]) == RTmp:
+                d = defs.get(rval(i.arg[0]))
+                if d is not None and d < k and ins[d].op in _ZEXT[i.op][0] and ins[d].cls == Kw \
+                        and tmp[rval(i.arg[0])].nuse == 1:
+                    ld = ins[d]
+                    ld.op = _ZEXT[i.op][1]
+                    ld.cls = Kl
+                    ld.to = i.to
+                    ins[k] = Ins(Onop)
+        for k, st in enumerate(ins):
+            k2 = {Ostorew: Kw, Ostorel: Kl}.get(st.op)
+            if k2 is None or rtype(st.arg[0]) != RTmp or fn.hasvolatile:  # a volatile access stays as written
+                continue
+            o = defs.get(rval(st.arg[0]))
+            if o is None or o >= k or ins[o].op not in _RMW or ins[o].cls != k2 or tmp[rval(st.arg[0])].nuse != 1:
+                continue
+            op = ins[o]
+            for n in (0, 1):
+                a = op.arg[n]
+                if rtype(a) != RTmp:
+                    continue
+                d = defs.get(rval(a))
+                if d is None or d >= o or tmp[rval(a)].nuse != 1:
+                    continue
+                ld = ins[d]
+                if not ((ld.op == Oload or (k2 == Kw and ld.op in (D.Oloadsw, D.Oloaduw))) and ld.cls == k2
+                        and ld.arg[0] == st.arg[1]):
+                    continue
+                if n == 1 and op.op == Osub:
+                    continue
+                if any(_writes(x.op) for x in ins[d + 1:k] if x is not op):
+                    continue
+                v = op.arg[1 - n]
+                ins[k] = Ins(_RMW[op.op], k2, R, v, st.arg[1])
+                ins[o] = Ins(Onop)
+                ins[d] = Ins(Onop)
+                tmp[rval(st.arg[1])].nuse -= 1 if rtype(st.arg[1]) == RTmp else 0
+                break
+        b.ins = ins
+        b.nins = len(ins)
+        b = b.link
+
+
 def amd64_isel(fn):
     """instruction selection
     requires use counts (as given by parsing)"""
@@ -892,6 +1015,8 @@ def amd64_isel(fn):
                 b.ins[k] = Ins(Onop)
         n *= 2
 
+    _loadsfold(fn)
+
     # process basic blocks
     b = fn.start
     while b: