cerilog 0.1.0__tar.gz

cerilog-0.1.0/LICENSE

@@ -0,0 +1,21 @@
+MIT License
+
+Copyright (c) 2026 R0mba-Na11avan
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in all
+copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+SOFTWARE.

cerilog-0.1.0/PKG-INFO

@@ -0,0 +1,196 @@
+Metadata-Version: 2.4
+Name: cerilog
+Version: 0.1.0
+Summary: A C-flavored HDL that transpiles to SystemVerilog or Verilog-2005
+Author: R0mba-Na11avan
+License-Expression: MIT
+Project-URL: Homepage, https://github.com/R0mba-Na11avan/Cerilog
+Project-URL: Documentation, https://github.com/R0mba-Na11avan/Cerilog/blob/main/docs/language_spec.md
+Project-URL: Issues, https://github.com/R0mba-Na11avan/Cerilog/issues
+Keywords: verilog,systemverilog,hdl,fpga,transpiler
+Classifier: Development Status :: 3 - Alpha
+Classifier: Environment :: Console
+Classifier: Intended Audience :: Developers
+Classifier: Programming Language :: Python :: 3
+Classifier: Programming Language :: Python :: 3 :: Only
+Classifier: Topic :: Software Development :: Compilers
+Classifier: Topic :: System :: Hardware
+Requires-Python: >=3.10
+Description-Content-Type: text/markdown
+License-File: LICENSE
+Requires-Dist: lark>=1.1
+Provides-Extra: dev
+Requires-Dist: pytest>=7.0; extra == "dev"
+Dynamic: license-file
+
+# Cerilog
+
+Cerilog is a C-flavored hardware description language that transpiles to
+**SystemVerilog** (`.sv`) or **Verilog-2005** (`.v`). Curly braces instead of
+`begin`/`end`, ports declared in the module header, one `logic` type, one
+`always` keyword. The output is plain, readable HDL that goes into Quartus,
+Vivado, Verilator or Icarus unchanged.
+
+```
+counter.cel  ──cerilog──▶  counter.sv / counter.v  ──▶  Quartus / Vivado / Verilator
+```
+
+## Example
+
+```cerilog
+// counter.cel
+module Counter(
+    input  logic       clk,
+    input  logic       rst,
+    output logic[7:0]  count
+) {
+    always(posedge clk) {
+        if (rst) count <= 0;
+        else     count <= count + 1;
+    }
+}
+```
+
+`cerilog counter.cel -o counter.sv`:
+
+```systemverilog
+module Counter (
+    input  logic       clk,
+    input  logic       rst,
+    output logic [7:0] count
+);
+    always_ff @(posedge clk) begin
+        if (rst) begin
+            count <= 0;
+        end else begin
+            count <= count + 1;
+        end
+    end
+endmodule
+```
+
+`cerilog counter.cel -o counter.v`, for tools without SystemVerilog support:
+
+```verilog
+module Counter (
+    input  wire       clk,
+    input  wire       rst,
+    output reg  [7:0] count
+);
+    always @(posedge clk) begin
+        if (rst) begin
+            count <= 0;
+        end else begin
+            count <= count + 1;
+        end
+    end
+endmodule
+```
+
+(Real output also has a header line and `// source: counter.cel:N` comments,
+which tie tool errors back to your source.)
+
+## Features
+
+- `{ }` blocks; braces are optional around single statements, as in C
+- Ports and parameters declared in the module header
+- `logic` everywhere. For Verilog output, `wire` vs `reg` is worked out for you
+- `always()` for combinational logic, `always(posedge clk)` for flip-flops
+- C-style stacked `case` labels (fallthrough)
+- `for` loops: inside `always` they're procedural, at module level they
+  become generate loops
+- Multiple modules per file and SystemVerilog-style instances
+- Memories, `localparam`, initial values, the full SystemVerilog operator set,
+  `$clog2` and friends
+- Errors and warnings with `file:line:col`, the source line and a caret
+- VS Code extension: highlighting, error squiggles on save, a ▶ compile
+  button and an `.sv`/`.v` target picker
+
+The full language is described in [`docs/language_spec.md`](https://github.com/R0mba-Na11avan/Cerilog/blob/main/docs/language_spec.md).
+
+## Install
+
+Requires Python 3.10+.
+
+```bash
+pip install cerilog
+```
+
+This installs the `cerilog` command and its one dependency, the `lark`
+parser library.
+
+To work on Cerilog itself:
+
+```bash
+git clone https://github.com/R0mba-Na11avan/Cerilog.git
+cd Cerilog
+pip install -e ".[dev]"
+```
+
+## Usage
+
+```bash
+cerilog counter.cel                  # SystemVerilog to stdout
+cerilog counter.cel -o counter.sv    # SystemVerilog to a file
+cerilog counter.cel -o counter.v     # Verilog-2005 (target taken from the extension)
+cerilog counter.cel --target v       # Verilog-2005 to stdout
+cerilog counter.cel --check          # only report errors and warnings
+```
+
+| Flag | Meaning |
+|---|---|
+| `-o FILE` | write to `FILE`; a `.sv` or `.v` extension picks the target |
+| `--target sv\|v` | choose the output language (also `systemverilog` / `verilog`); overrides the extension |
+| `--check` | parse and check only; write nothing |
+| `--no-source-maps` | leave out the `// source: file.cel:N` comments |
+| `--tokens`, `--ast` | print the token stream or the syntax tree (debugging) |
+
+Errors and warnings go to stderr. The exit status is 1 if there were errors.
+
+```
+counter.cel:8:28: error: expected ';' before 'else'
+            if (rst) count <= 0
+                               ^
+```
+
+## VS Code
+
+The extension in [`editors/vscode`](https://github.com/R0mba-Na11avan/Cerilog/blob/main/editors/vscode) adds syntax highlighting,
+error checking on save, a ▶ compile button, and a status-bar switch between
+`.sv` and `.v` output. See its [README](https://github.com/R0mba-Na11avan/Cerilog/blob/main/editors/vscode/README.md) to install it.
+
+## Project layout
+
+```
+cerilog/
+├── __main__.py          command line
+├── compiler.py          compile_source(): parse → analyse → emit
+├── errors.py            diagnostics and their formatting
+├── lexer/lexer.py       token stream (debugging, --tokens)
+├── parser/grammar.lark  the grammar: every token and syntax rule
+├── parser/parser.py     Lark parse tree → AST, syntax error messages
+├── ast/nodes.py         AST node dataclasses
+├── analysis/checks.py   symbol checks, drivers, wire/reg inference, warnings
+└── codegen/emitter.py   SystemVerilog and Verilog output
+examples/                example .cel programs
+tests/                   pytest suite, golden outputs, Verilator lint
+editors/vscode/          VS Code extension
+docs/language_spec.md    language reference
+```
+
+## Tests
+
+```bash
+python -m pytest
+```
+
+- `tests/golden/` compiles every file in `examples/` to both targets and
+  compares the result with `tests/golden/expected/`. After an intended output
+  change, regenerate with `CERILOG_UPDATE_GOLDEN=1 python -m pytest tests/golden`
+  and review the diff.
+- `tests/lint/` runs `verilator --lint-only` on every example in both
+  targets. It is skipped when Verilator isn't installed.
+
+## License
+
+MIT

cerilog-0.1.0/README.md

@@ -0,0 +1,171 @@
+# Cerilog
+
+Cerilog is a C-flavored hardware description language that transpiles to
+**SystemVerilog** (`.sv`) or **Verilog-2005** (`.v`). Curly braces instead of
+`begin`/`end`, ports declared in the module header, one `logic` type, one
+`always` keyword. The output is plain, readable HDL that goes into Quartus,
+Vivado, Verilator or Icarus unchanged.
+
+```
+counter.cel  ──cerilog──▶  counter.sv / counter.v  ──▶  Quartus / Vivado / Verilator
+```
+
+## Example
+
+```cerilog
+// counter.cel
+module Counter(
+    input  logic       clk,
+    input  logic       rst,
+    output logic[7:0]  count
+) {
+    always(posedge clk) {
+        if (rst) count <= 0;
+        else     count <= count + 1;
+    }
+}
+```
+
+`cerilog counter.cel -o counter.sv`:
+
+```systemverilog
+module Counter (
+    input  logic       clk,
+    input  logic       rst,
+    output logic [7:0] count
+);
+    always_ff @(posedge clk) begin
+        if (rst) begin
+            count <= 0;
+        end else begin
+            count <= count + 1;
+        end
+    end
+endmodule
+```
+
+`cerilog counter.cel -o counter.v`, for tools without SystemVerilog support:
+
+```verilog
+module Counter (
+    input  wire       clk,
+    input  wire       rst,
+    output reg  [7:0] count
+);
+    always @(posedge clk) begin
+        if (rst) begin
+            count <= 0;
+        end else begin
+            count <= count + 1;
+        end
+    end
+endmodule
+```
+
+(Real output also has a header line and `// source: counter.cel:N` comments,
+which tie tool errors back to your source.)
+
+## Features
+
+- `{ }` blocks; braces are optional around single statements, as in C
+- Ports and parameters declared in the module header
+- `logic` everywhere. For Verilog output, `wire` vs `reg` is worked out for you
+- `always()` for combinational logic, `always(posedge clk)` for flip-flops
+- C-style stacked `case` labels (fallthrough)
+- `for` loops: inside `always` they're procedural, at module level they
+  become generate loops
+- Multiple modules per file and SystemVerilog-style instances
+- Memories, `localparam`, initial values, the full SystemVerilog operator set,
+  `$clog2` and friends
+- Errors and warnings with `file:line:col`, the source line and a caret
+- VS Code extension: highlighting, error squiggles on save, a ▶ compile
+  button and an `.sv`/`.v` target picker
+
+The full language is described in [`docs/language_spec.md`](https://github.com/R0mba-Na11avan/Cerilog/blob/main/docs/language_spec.md).
+
+## Install
+
+Requires Python 3.10+.
+
+```bash
+pip install cerilog
+```
+
+This installs the `cerilog` command and its one dependency, the `lark`
+parser library.
+
+To work on Cerilog itself:
+
+```bash
+git clone https://github.com/R0mba-Na11avan/Cerilog.git
+cd Cerilog
+pip install -e ".[dev]"
+```
+
+## Usage
+
+```bash
+cerilog counter.cel                  # SystemVerilog to stdout
+cerilog counter.cel -o counter.sv    # SystemVerilog to a file
+cerilog counter.cel -o counter.v     # Verilog-2005 (target taken from the extension)
+cerilog counter.cel --target v       # Verilog-2005 to stdout
+cerilog counter.cel --check          # only report errors and warnings
+```
+
+| Flag | Meaning |
+|---|---|
+| `-o FILE` | write to `FILE`; a `.sv` or `.v` extension picks the target |
+| `--target sv\|v` | choose the output language (also `systemverilog` / `verilog`); overrides the extension |
+| `--check` | parse and check only; write nothing |
+| `--no-source-maps` | leave out the `// source: file.cel:N` comments |
+| `--tokens`, `--ast` | print the token stream or the syntax tree (debugging) |
+
+Errors and warnings go to stderr. The exit status is 1 if there were errors.
+
+```
+counter.cel:8:28: error: expected ';' before 'else'
+            if (rst) count <= 0
+                               ^
+```
+
+## VS Code
+
+The extension in [`editors/vscode`](https://github.com/R0mba-Na11avan/Cerilog/blob/main/editors/vscode) adds syntax highlighting,
+error checking on save, a ▶ compile button, and a status-bar switch between
+`.sv` and `.v` output. See its [README](https://github.com/R0mba-Na11avan/Cerilog/blob/main/editors/vscode/README.md) to install it.
+
+## Project layout
+
+```
+cerilog/
+├── __main__.py          command line
+├── compiler.py          compile_source(): parse → analyse → emit
+├── errors.py            diagnostics and their formatting
+├── lexer/lexer.py       token stream (debugging, --tokens)
+├── parser/grammar.lark  the grammar: every token and syntax rule
+├── parser/parser.py     Lark parse tree → AST, syntax error messages
+├── ast/nodes.py         AST node dataclasses
+├── analysis/checks.py   symbol checks, drivers, wire/reg inference, warnings
+└── codegen/emitter.py   SystemVerilog and Verilog output
+examples/                example .cel programs
+tests/                   pytest suite, golden outputs, Verilator lint
+editors/vscode/          VS Code extension
+docs/language_spec.md    language reference
+```
+
+## Tests
+
+```bash
+python -m pytest
+```
+
+- `tests/golden/` compiles every file in `examples/` to both targets and
+  compares the result with `tests/golden/expected/`. After an intended output
+  change, regenerate with `CERILOG_UPDATE_GOLDEN=1 python -m pytest tests/golden`
+  and review the diff.
+- `tests/lint/` runs `verilator --lint-only` on every example in both
+  targets. It is skipped when Verilator isn't installed.
+
+## License
+
+MIT

cerilog-0.1.0/cerilog/__init__.py

@@ -0,0 +1 @@
+# Cerilog

cerilog-0.1.0/cerilog/__main__.py

@@ -0,0 +1,107 @@
+"""
+Cerilog command line.
+
+    cerilog counter.cel                     SystemVerilog to stdout
+    cerilog counter.cel -o counter.sv       SystemVerilog to a file
+    cerilog counter.cel -o counter.v        Verilog-2005 (target from the extension)
+    cerilog counter.cel --target v          Verilog-2005 to stdout
+    cerilog counter.cel --check             check only, write nothing
+
+Diagnostics go to stderr. Exit status is 1 if there were errors.
+"""
+
+from __future__ import annotations
+
+import argparse
+import sys
+from pathlib import Path
+
+from cerilog.codegen.emitter import Target
+from cerilog.compiler import compile_source
+from cerilog.errors import CerilogError, format_diagnostic
+
+
+def _parse_args(argv):
+    parser = argparse.ArgumentParser(
+        prog="cerilog",
+        description="Transpile Cerilog (.cel) to SystemVerilog (.sv) or Verilog-2005 (.v).",
+    )
+    parser.add_argument("input", help="input .cel file")
+    parser.add_argument("-o", "--output", help="output file; .sv or .v picks the target (default: stdout)")
+    parser.add_argument("--target", metavar="{sv,v}",
+                        help="output language: sv/systemverilog or v/verilog "
+                             "(default: from the -o extension, else sv)")
+    parser.add_argument("--check", action="store_true", help="report errors and warnings, write nothing")
+    parser.add_argument("--no-source-maps", action="store_true",
+                        help="leave out the // source: file.cel:N comments")
+    parser.add_argument("--tokens", action="store_true", help="print the token stream and exit (debug)")
+    parser.add_argument("--ast", action="store_true", help="print the AST and exit (debug)")
+    return parser, parser.parse_args(argv)
+
+
+def _resolve_target(parser, args) -> Target:
+    if args.target:
+        try:
+            return Target.parse(args.target)
+        except ValueError as e:
+            parser.error(str(e))
+    if args.output:
+        from_ext = Target.from_extension(args.output)
+        if from_ext is not None:
+            return from_ext
+    return Target.SYSTEMVERILOG
+
+
+def main(argv=None) -> int:
+    parser, args = _parse_args(argv)
+    target = _resolve_target(parser, args)
+
+    input_path = Path(args.input)
+    if not input_path.is_file():
+        print(f"cerilog: error: file not found: {args.input}", file=sys.stderr)
+        return 1
+    if input_path.suffix != ".cel":
+        print(f"cerilog: warning: expected a .cel file, got '{input_path.suffix}'", file=sys.stderr)
+
+    source = input_path.read_text(encoding="utf-8")
+    display_name = args.input
+
+    if args.tokens or args.ast:
+        return _debug_dump(args, source, display_name)
+
+    result = compile_source(source, target=target, filename=input_path.name,
+                            source_maps=not args.no_source_maps)
+    for diag in result.diagnostics:
+        print(format_diagnostic(diag, source, display_name), file=sys.stderr)
+    if not result.ok:
+        return 1
+    if args.check:
+        return 0
+
+    if args.output:
+        Path(args.output).write_text(result.code, encoding="utf-8", newline="\n")
+        print(f"cerilog: wrote {args.output} ({target.display_name})", file=sys.stderr)
+    else:
+        sys.stdout.write(result.code)
+    return 0
+
+
+def _debug_dump(args, source: str, display_name: str) -> int:
+    from cerilog.ast.nodes import dump
+    from cerilog.lexer.lexer import Lexer
+    from cerilog.parser.parser import Parser
+
+    try:
+        if args.tokens:
+            for token in Lexer().tokenize(source):
+                print(token)
+        else:
+            print(dump(Parser().parse(source)))
+    except CerilogError as e:
+        print(format_diagnostic(e.diagnostic, source, display_name), file=sys.stderr)
+        return 1
+    return 0
+
+
+if __name__ == "__main__":
+    sys.exit(main())