c4m-flexcell 0.4.0.dev23__tar.gz → 0.4.2__tar.gz

{c4m_flexcell-0.4.0.dev23 → c4m_flexcell-0.4.2}/.gitlab-ci.yml

@@ -19,7 +19,6 @@ before_script:
 dist:
   only:
     - main
-    - dev_v0.4
   variables:
     TWINE_PASSWORD: '${CI_JOB_TOKEN}'
     TWINE_USERNAME: 'gitlab-ci-token'
@@ -34,7 +33,6 @@ dist:
 dist-test:
   except:
     - main
-    - dev_v0.4
   script:
     # Need to fetch tags
     - git fetch --depth=1 origin +refs/tags/*:refs/tags/*

{c4m_flexcell-0.4.0.dev23 → c4m_flexcell-0.4.2}/PKG-INFO

@@ -1,6 +1,6 @@
 Metadata-Version: 2.1
 Name: c4m_flexcell
-Version: 0.4.0.dev23
+Version: 0.4.2
 Summary: PDKMaster based scalable standard cell library
 Author: Staf Verhaegen
 Author-email: staf@fibraservi.eu
@@ -10,6 +10,9 @@ Project-URL: Bug Tracker, https://gitlab.com/Chips4Makers/c4m-flexcell/issues
 Requires-Python: ~=3.6
 Description-Content-Type: text/markdown
 License-File: LICENSE.md
+Requires-Dist: setuptools
+Requires-Dist: nest-asyncio
+Requires-Dist: PDKMaster~=0.10.0
 
 # Flexible, scalable, standard cell library
 
@@ -19,9 +22,13 @@ Standard cells are introduced into an [ASIC](https://en.wikipedia.org/wiki/Appli
 
 ## Release History
 
-Current development is done on a development branch for version 0.4. Documentation/README will
-be updated together with the release of this version.
-
+* [v0.4.2](https://gitlab.com/Chips4Makers/c4m-flexcell/-/commits/v0.10.2): only internal
+  improvements
+* v0.4.1:
+  major reworking of the code. A new class ActiveColumnsCell has been introduced to generate the layouts of the standard cells. This removes the lambda based dimensions from the cells to compute them all from the design rules.  
+  All cells were converter to this new layout method and this should allow to make standard cell libraries with much lower height of the cells. Compatiblity function are provided so that layout spec can be derived as was done previously as based on a lambda value.  
+  v0.4.0 had only dev releases and code was rebased and squashed for this release.
+* v0.3.3: bug fix; remove public 0.3.2 release
 * v0.3.2: code cleansing, bug fixing, update dependencies
 * v0.3.1: small update for Coriolis export
 * v0.3.0: Update for [release v0.9.0 of PDKMaster](https://gitlab.com/Chips4Makers/PDKMaster/-/blob/v0.9.0/ReleaseNotes/v0.9.0.md); replace Library-> StdCellFactory to follow common usage of a factory to generate cells.
@@ -39,7 +46,5 @@ In future options are planned so libraries can be generated for different target
 ## Status
 
 This repository is currently considered experimental code with no backwards compatibility guarantees whatsoever.  
-This development is done in a development branch for new layout generation code.
-When this development is done it will be released as version 0.4.0.  
 Current implementation is based on the topology of the Coriolis nsxlib standard cells with some area improvements but not yet with optimal area use. For v0.1 of this library a total replacement of the layout generation is planned fully based on minimized area for the technology design rules.  
 If interested head over to [gitter](https://gitter.im/Chips4Makers/community) for further discussion.

{c4m_flexcell-0.4.0.dev23 → c4m_flexcell-0.4.2}/README.md

@@ -6,9 +6,13 @@ Standard cells are introduced into an [ASIC](https://en.wikipedia.org/wiki/Appli
 
 ## Release History
 
-Current development is done on a development branch for version 0.4. Documentation/README will
-be updated together with the release of this version.
-
+* [v0.4.2](https://gitlab.com/Chips4Makers/c4m-flexcell/-/commits/v0.10.2): only internal
+  improvements
+* v0.4.1:
+  major reworking of the code. A new class ActiveColumnsCell has been introduced to generate the layouts of the standard cells. This removes the lambda based dimensions from the cells to compute them all from the design rules.  
+  All cells were converter to this new layout method and this should allow to make standard cell libraries with much lower height of the cells. Compatiblity function are provided so that layout spec can be derived as was done previously as based on a lambda value.  
+  v0.4.0 had only dev releases and code was rebased and squashed for this release.
+* v0.3.3: bug fix; remove public 0.3.2 release
 * v0.3.2: code cleansing, bug fixing, update dependencies
 * v0.3.1: small update for Coriolis export
 * v0.3.0: Update for [release v0.9.0 of PDKMaster](https://gitlab.com/Chips4Makers/PDKMaster/-/blob/v0.9.0/ReleaseNotes/v0.9.0.md); replace Library-> StdCellFactory to follow common usage of a factory to generate cells.
@@ -26,7 +30,5 @@ In future options are planned so libraries can be generated for different target
 ## Status
 
 This repository is currently considered experimental code with no backwards compatibility guarantees whatsoever.  
-This development is done in a development branch for new layout generation code.
-When this development is done it will be released as version 0.4.0.  
 Current implementation is based on the topology of the Coriolis nsxlib standard cells with some area improvements but not yet with optimal area use. For v0.1 of this library a total replacement of the layout generation is planned fully based on minimized area for the technology design rules.  
 If interested head over to [gitter](https://gitter.im/Chips4Makers/community) for further discussion.

{c4m_flexcell-0.4.0.dev23 → c4m_flexcell-0.4.2}/c4m/flexcell/activecolumnscell.py

@@ -1,7 +1,8 @@
 # SPDX-License-Identifier: GPL-2.0-or-later OR AGPL-3.0-or-later OR CERN-OHL-S-2.0+
 from itertools import chain
 import abc
-import asyncio
+import asyncio, nest_asyncio
+from threading import Thread
 from typing import (
     List, Tuple, Iterator, Optional, Union, Callable, TypeVar, Generic, cast,
 )
@@ -1450,7 +1451,6 @@ class _Constraints:
 
         # Place the poly pads that are not in a metal 1 row.
         # self.log("_do_layout: calling _place_polypads")
-        # tasks.append(asyncio.create_task(self._place_polypads_m1rows()))
         tasks.extend((
             asyncio.create_task(self._place_polypads_m1row(m1row=m1row))
             for m1row in chain(*self.m1rows)
@@ -1492,11 +1492,6 @@ class _Constraints:
         # self.log("_do_layout: calling _size_width")
         self._size_width()
 
-        # Add taps where possible
-        # This assumes that the widht of the cell is known
-        # self.log("_do_layout: calling _add_taps")
-        self._add_taps()
-
         return True
 
     def _set_transistor_nets(self) -> None:
@@ -1878,13 +1873,13 @@ class _Constraints:
         cell = self.cell
         canvas = cell.canvas
         ac_canvas = cell.ac_canvas
-        metal1 = canvas._metal1
 
         x: Optional[float] = None
         for multim1col in self.m1columns:
             # self.log(f"_place_m1cols(): computing x of {multim1col.name}")
             x = (
-                0.5*ac_canvas._min_m1col_pitch if (x is None)
+                # First column can contact to polypad so use _firstcol_dx
+                ac_canvas._firstcol_dx if (x is None)
                 else x + ac_canvas._min_m1col_pitch
             )
             assert not multim1col.is_placed, "Internal error"
@@ -1958,11 +1953,7 @@ class _Constraints:
     def _size_width(self) -> None:
         cell = self.cell
         canvas = cell.canvas
-        ac_canvas = cell.ac_canvas
-        layouter = cell.layouter
 
-        nimplant = canvas._nimplant
-        pimplant = canvas._pimplant
         active = canvas._active
 
         lastcol = self.activecolumns[-1]
@@ -1974,105 +1965,14 @@ class _Constraints:
         if nsd is not None:
             lay = nsd._placed
             bb = lay.bounds(mask=active.mask)
-            min_widths.append(bb.right + 0.5*active.min_space)
+            min_widths.append(bb.right + 0.5*canvas._min_active_space)
         if psd is not None:
             lay = psd._placed
             bb = lay.bounds(mask=active.mask)
-            min_widths.append(bb.right + 0.5*active.min_space)
+            min_widths.append(bb.right + 0.5*canvas._min_active_space)
         assert len(min_widths) > 0
 
-        width = self.cell.set_width(min_width=max(min_widths))
-
-        # Draw implants
-        if nimplant is not None:
-            assert canvas._min_active_nimplant_enc is not None
-            assert canvas._min_nsd_enc is not None
-            enc = canvas._min_active_nimplant_enc.first
-            left = -enc
-            right = width + enc
-            bottom = ac_canvas._nact_bottom - canvas._min_nsd_enc.second
-            top = canvas._well_edge_height
-            shape = _geo.Rect(left=left, bottom=bottom, right=right, top=top)
-            layouter.add_portless(prim=nimplant, shape=shape)
-        # Draw implants
-        if pimplant is not None:
-            assert canvas._min_active_pimplant_enc is not None
-            assert canvas._min_psd_enc is not None
-            enc = canvas._min_active_pimplant_enc.first
-            left = -enc
-            right = width + enc
-            top = ac_canvas._pact_top + canvas._min_psd_enc.second
-            bottom = canvas._well_edge_height
-            shape = _geo.Rect(left=left, bottom=bottom, right=right, top=top)
-            layouter.add_portless(prim=pimplant, shape=shape)
-
-    def _add_taps(self) -> None:
-        cell = self.cell
-        tech = cell.tech
-        canvas = cell.canvas
-        layouter = cell.layouter
-
-        width = cell.width
-
-        pwell = canvas._pwell
-        nwell = canvas._nwell
-        active = canvas._active
-        nimplant = canvas._nimplant
-        if canvas._min_active_nimplant_enc is None:
-            assert nimplant is None, "Internal error"
-            nenc = None
-        else:
-            nenc = canvas._min_active_nimplant_enc.wide()
-            if (nenc.first + _geo.epsilon) < 0.5*active.min_space:
-                nenc = _prp.Enclosure((0.5*active.min_space, nenc.second))
-        pimplant = canvas._pimplant
-        if canvas._min_active_pimplant_enc is None:
-            assert pimplant is None, "Internal error"
-            penc = None
-        else:
-            penc = canvas._min_active_pimplant_enc.wide()
-            if (penc.first + _geo.epsilon) < 0.5*active.min_space:
-                penc = _prp.Enclosure((0.5*active.min_space, penc.second))
-        active = canvas._active
-        contact = canvas._contact
-
-        tap_height = tech.computed.min_width(active, up=True, min_enclosure=True)
-
-        # ptap
-        act_left = 0.5*active.min_space
-        act_right = width - act_left
-        act_bottom = 0.5*active.min_space
-        act_top = act_bottom + tap_height
-        lay = layouter.add_wire(
-            net=cell.vss, well_net=cell.pwell_net, wire=contact,
-            bottom=active, bottom_well=pwell, bottom_enclosure="wide",
-            bottom_implant=pimplant, bottom_implant_enclosure=penc,
-            bottom_left=act_left, bottom_bottom=act_bottom,
-            bottom_right=act_right, bottom_top=act_top,
-        )
-        if pimplant is not None:
-            bb = lay.bounds(mask=pimplant.mask)
-            if (bb.bottom - _geo.epsilon) > 0.0:
-                shape = _geo.Rect.from_rect(rect=bb, bottom=0.0)
-                layouter.add_portless(prim=pimplant, shape=shape)
-
-        # ntap
-        act_left = 0.5*active.min_space
-        act_right = width - act_left
-        act_top = canvas._cell_height - 0.5*active.min_space
-        act_bottom = act_top - tap_height
-        lay = layouter.add_wire(
-            net=cell.vdd, well_net=cell.nwell_net, wire=contact,
-            bottom=active, bottom_well=nwell, bottom_enclosure="wide",
-            bottom_implant=nimplant, bottom_implant_enclosure=nenc,
-            bottom_left=act_left, bottom_bottom=act_bottom,
-            bottom_right=act_right, bottom_top=act_top,
-        )
-        if nimplant is not None:
-            bb = lay.bounds(mask=nimplant.mask)
-            if (bb.top + _geo.epsilon) < canvas._cell_height:
-                shape = _geo.Rect.from_rect(rect=bb, top=canvas._cell_height)
-                layouter.add_portless(prim=nimplant, shape=shape)
+        self.cell.set_width(min_width=max(min_widths))
 
     def log(self, *args):
         print(f"[{self.cell.name}:Constraints]", *args)
@@ -2142,8 +2042,14 @@ class _ActiveColumnsCanvas:
             metal1, down=True, up=True, min_enclosure=True,
         )
 
-        dx_act = 0.5*active.min_space + 0.5*self._actcont_width
+        dx_act = 0.5*canvas._min_active_space + 0.5*self._actcont_width
         dx_poly = 0.5*poly.min_space + 0.5*self._polycont_width
+        try:
+            s = tech.computed.min_space(active, poly)
+        except:
+            pass
+        else:
+            dx_poly = max(dx_poly, -0.5*canvas._min_active_space + s + 0.5*self._polycont_width)
         dx_m1 = 0.5*metal1.min_space + 0.5*self._m1col_width
         self._firstcol_dx = tech.on_grid(
             max(dx_act, dx_poly, dx_m1), rounding="ceiling",
@@ -2197,7 +2103,7 @@ class _ActiveColumnsCanvas:
         )
         # Min dx for gap in active
         self._min_actgap_dx = tech.on_grid(
-            0.5*(self._actcont_width + active.min_space),
+            0.5*(self._actcont_width + canvas._min_active_space),
             rounding="ceiling",
         )
 
@@ -2260,22 +2166,170 @@ class _ActiveColumnsCanvas:
         )
 
 
-class ActiveColumnsCell(_Cell, abc.ABC):
-    def __init__(self, *, name: str, fab: "_scfab.StdCellFactory"):
+class ActiveColumnsCellFrame(_Cell):
+    """Subclasses of this class need to call _draw_frame() after they have set
+    the of the cell.
+    """
+    def __init__(self, *, name: str, fab: "_scfab.StdCellFactory", draw_implants: bool=True):
         super().__init__(name=name, fab=fab)
 
         canvas = fab.canvas
         if canvas._ac_canvas is None:
             canvas._ac_canvas = _ActiveColumnsCanvas(fab=fab)
 
-        self._waiterfab = _WaiterFactory(name=f"{name}:waiterfab")
-
-        generator = self.build_generator()
-        asyncio.get_event_loop().run_until_complete(generator._do_layout())
+        self._draw_implants = draw_implants
+        self._vsstap_lay: Optional[_lay.LayoutT] = None
+        self._vddtap_lay: Optional[_lay.LayoutT] = None
 
     @property
     def ac_canvas(self) -> _ActiveColumnsCanvas:
         return self.canvas._ac_canvas
+    @property
+    def draw_implants(self) -> bool:
+        return self._draw_implants
+    @property
+    def vsstap_lay(self) -> _lay.LayoutT:
+        if self._vsstap_lay is None:
+            raise TypeError(
+                f"Accessing vsstap_lay on cell '{self.name}' before set_width has been called"
+            )
+        return self._vsstap_lay
+    @property
+    def vddtap_lay(self) -> _lay.LayoutT:
+        if self._vddtap_lay is None:
+            raise TypeError(
+                f"Accessing vsstap_lay on cell '{self.name}' before set_width has been called"
+            )
+        return self._vddtap_lay
+
+    def set_width(self, **args) -> float:
+        width = super().set_width(**args)
+
+        tech = self.tech
+        canvas = self.canvas
+        ac_canvas = self.ac_canvas
+        layouter = self.layouter
+
+        pwell = canvas._pwell
+        nwell = canvas._nwell
+        active = canvas._active
+        nimplant = canvas._nimplant
+        if canvas._min_active_nimplant_enc is None:
+            assert nimplant is None, "Internal error"
+            nenc = None
+        else:
+            nenc = canvas._min_active_nimplant_enc.wide()
+            if (nenc.first + _geo.epsilon) < 0.5*canvas._min_active_space:
+                nenc = _prp.Enclosure((0.5*canvas._min_active_space, nenc.second))
+        pimplant = canvas._pimplant
+        if canvas._min_active_pimplant_enc is None:
+            assert pimplant is None, "Internal error"
+            penc = None
+        else:
+            penc = canvas._min_active_pimplant_enc.wide()
+            if (penc.first + _geo.epsilon) < 0.5*canvas._min_active_space:
+                penc = _prp.Enclosure((0.5*canvas._min_active_space, penc.second))
+        active = canvas._active
+        contact = canvas._contact
+
+        tap_height = tech.computed.min_width(active, up=True, min_enclosure=True)
+
+        # ptap
+        act_left = 0.5*canvas._min_active_space
+        act_right = width - act_left
+        act_bottom = 0.5*canvas._min_active_space
+        act_top = act_bottom + tap_height
+        self._vsstap_lay = lay = layouter.add_wire(
+            net=self.vss, well_net=self.pwell_net, wire=contact,
+            bottom=active, bottom_well=pwell, bottom_enclosure="wide",
+            bottom_implant=pimplant, bottom_implant_enclosure=penc,
+            bottom_left=act_left, bottom_bottom=act_bottom,
+            bottom_right=act_right, bottom_top=act_top,
+        )
+        if pimplant is not None:
+            bb = lay.bounds(mask=pimplant.mask)
+            args = {}
+            if (bb.bottom - _geo.epsilon) > 0.0:
+                args["bottom"] = 0.0
+            if (bb.left - _geo.epsilon) > 0.0:
+                args["left"] = 0.0
+                args["right"] = width
+            if args:
+                shape = _geo.Rect.from_rect(rect=bb, **args)
+                layouter.add_portless(prim=pimplant, shape=shape)
+
+        # ntap
+        act_left = 0.5*canvas._min_active_space
+        act_right = width - act_left
+        act_top = canvas._cell_height - 0.5*canvas._min_active_space
+        act_bottom = act_top - tap_height
+        self._vddtap_lay = lay = layouter.add_wire(
+            net=self.vdd, well_net=self.nwell_net, wire=contact,
+            bottom=active, bottom_well=nwell, bottom_enclosure="wide",
+            bottom_implant=nimplant, bottom_implant_enclosure=nenc,
+            bottom_left=act_left, bottom_bottom=act_bottom,
+            bottom_right=act_right, bottom_top=act_top,
+        )
+        if nimplant is not None:
+            bb = lay.bounds(mask=nimplant.mask)
+            args = {}
+            if (bb.top + _geo.epsilon) < canvas._cell_height:
+                args["top"] = canvas._cell_height
+            if (bb.left - _geo.epsilon) > 0.0:
+                args["left"] = 0.0
+                args["right"] = width
+            if args:
+                shape = _geo.Rect.from_rect(rect=bb, **args)
+                layouter.add_portless(prim=nimplant, shape=shape)
+
+        if self.draw_implants:
+            # transistor nimplant
+            if nimplant is not None:
+                assert canvas._min_active_nimplant_enc is not None
+                assert canvas._min_nsd_enc is not None
+                enc = canvas._min_active_nimplant_enc.first
+                left = min(0.0, 0.5*canvas._min_active_space - enc)
+                right = max(width, width - 0.5*canvas._min_active_space + enc)
+                bottom = ac_canvas._nact_bottom - canvas._min_nsd_enc.second
+                top = canvas._well_edge_height
+                shape = _geo.Rect(left=left, bottom=bottom, right=right, top=top)
+                lay = layouter.add_portless(prim=nimplant, shape=shape)
+
+            # transistor pimplant
+            if pimplant is not None:
+                assert canvas._min_active_pimplant_enc is not None
+                assert canvas._min_psd_enc is not None
+                enc = canvas._min_active_pimplant_enc.first
+                left = min(0.0, 0.5*canvas._min_active_space - enc)
+                right = max(width, width - 0.5*canvas._min_active_space + enc)
+                top = ac_canvas._pact_top + canvas._min_psd_enc.second
+                bottom = canvas._well_edge_height
+                shape = _geo.Rect(left=left, bottom=bottom, right=right, top=top)
+                layouter.add_portless(prim=pimplant, shape=shape)
+
+        return width
+
+
+class ActiveColumnsCell(ActiveColumnsCellFrame, abc.ABC):
+    def __init__(self, *, name: str, fab: "_scfab.StdCellFactory"):
+        super().__init__(name=name, fab=fab)
+
+        self._waiterfab = _WaiterFactory(name=f"{name}:waiterfab")
+
+        generator = self.build_generator()
+        loop = asyncio.get_event_loop()
+
+        if loop.is_running():
+            class DoLayoutThread(Thread):
+                def run(self):
+                    loop = asyncio.new_event_loop()
+                    loop.run_until_complete(generator._do_layout())
+
+            thread = DoLayoutThread()
+            thread.start()
+            thread.join()
+        else:
+            loop.run_until_complete(generator._do_layout())
 
     @abc.abstractmethod
     def build_generator(self) -> ConstraintsT:

{c4m_flexcell-0.4.0.dev23 → c4m_flexcell-0.4.2}/c4m/flexcell/canvas.py

@@ -163,6 +163,17 @@ class StdCellCanvas:
                 "Different poly wire for nmos and pmos transistor"
             )
 
+        vs = [active.min_space]
+        if inside is not None:
+            for in_ in inside:
+                try:
+                    s = tech.computed.min_space(active.in_(in_))
+                except:
+                    pass
+                else:
+                    vs.append(s)
+        self._min_active_space = max(vs)
+
         self._min_active_poly_space = tech.computed.min_space(active, poly)
 
         self._nactive = nactive = active if nimplant is None else active.in_(nimplant)

{c4m_flexcell-0.4.0.dev23 → c4m_flexcell-0.4.2}/c4m/flexcell/factory.py

@@ -1,10 +1,10 @@
 # SPDX-License-Identifier: GPL-2.0-or-later OR AGPL-3.0-or-later OR CERN-OHL-S-2.0+
 from itertools import product
-from typing import List, Tuple, Optional
+from typing import List, Tuple, Dict, Iterable, Optional, Any, cast
 
-from pdkmaster.technology import geometry as _geo
+from pdkmaster.technology import property_ as _prp,  geometry as _geo
 from pdkmaster.design import (
-    circuit as _ckt, layout as _lay, library as _lbry, factory as _fab,
+    circuit as _ckt, layout as _lay, cell as _cell, library as _lbry, factory as _fab,
 )
 from pdkmaster.io.coriolis import CoriolisExportSpec
 
@@ -43,28 +43,48 @@ class _Fill(_Cell):
 
         canvas = fab.canvas
 
+        nimplant = canvas._nimplant
+        pimplant = canvas._pimplant
+
         self.set_width(width=width*canvas._cell_horplacement_grid)
 
+        layouter = self.layouter
+
+        if pimplant is not None:
+            shape = _geo.Rect(
+                left=0.0, right=self.width,
+                bottom=0.0, top=pimplant.min_width,
+            )
+            layouter.add_portless(prim=pimplant, shape=shape)
 
-class _Tie(_Cell):
+        if nimplant is not None:
+            shape = _geo.Rect(
+                left=0.0, right=self.width,
+                bottom=(canvas._cell_height - nimplant.min_width),
+                top=canvas._cell_height,
+            )
+            layouter.add_portless(prim=nimplant, shape=shape)
+
+
+class _Tie(_acc.ActiveColumnsCellFrame):
     def __init__(self, *,
         fab: "StdCellFactory", name: str, max_diff: bool=False, max_poly: bool=False, width: int=1,
     ):
         if max_diff and max_poly:
             raise ValueError("only one of max_diff and max_poly can be 'True'")
 
+        super().__init__(fab=fab, name=name, draw_implants=(not max_diff))
+
         canvas = fab.canvas
+        ac_canvas = self.ac_canvas
         tech = fab.tech
 
-        super().__init__(fab=fab, name=name)
-
         cell_width = width*canvas._cell_horplacement_grid
         self.set_width(width=cell_width)
 
         active = canvas._active
         nimplant = canvas._nimplant
         pimplant = canvas._pimplant
-        nwell = canvas._nwell
         poly = canvas._poly
         contact = canvas._contact
         metal1 = canvas._metal1
@@ -75,42 +95,21 @@ class _Tie(_Cell):
         vdd = ckt.nets.vdd
         vss = ckt.nets.vss
 
-        min_actwell_space = tech.computed.min_space(primitive1=active, primitive2=nwell)
         min_actpoly_space = tech.computed.min_space(primitive1=active, primitive2=poly)
 
         if not max_diff:
-            # vss min tap
-            l_ch = layouter.wire_layout(
-                net=vss, wire=contact, rows=canvas._min_tap_chs,
-                bottom=active, bottom_implant=pimplant, bottom_enclosure="wide",
-            )
-            impl_bb = l_ch.bounds(mask=pimplant.mask)
-            x = 0.5*cell_width
-            y = 0.5*pimplant.min_space - impl_bb.bottom
-            vss_tap_lay = layouter.place(object_=l_ch, x=x, y=y)
-
-            # vdd min tap
-            l_ch = layouter.wire_layout(
-                net=vdd, well_net=vdd, wire=contact, rows=canvas._min_tap_chs,
-                bottom=active, bottom_implant=nimplant, bottom_well=nwell,
-                bottom_enclosure="wide",
-            )
-            x = 0.5*cell_width
-            if nimplant is not None:
-                impl_bb = l_ch.bounds(mask=nimplant.mask)
-                y = canvas._cell_height - 0.5*nimplant.min_space - impl_bb.top
-            else:
-                # TODO: Proper value
-                act_bb = l_ch.bounds(mask=active.mask)
-                y = canvas._cell_height - active.min_space - act_bb.top
-            vdd_tap_lay = layouter.place(object_=l_ch, x=x, y=y)
-
             if max_poly:
                 # Add big poly
-                vss_dio_tap_bb = vss_tap_lay.bounds(mask=active.mask)
-                vdd_dio_tap_bb = vdd_tap_lay.bounds(mask=active.mask)
+                vss_dio_tap_bb = self.vsstap_lay.bounds(mask=active.mask)
+                vdd_dio_tap_bb = self.vddtap_lay.bounds(mask=active.mask)
                 left = 0.5*poly.min_space
-                right = cell_width - 0.5*poly.min_space
+                try:
+                    s = tech.computed.min_space(active, poly)
+                except:
+                    pass
+                else:
+                    left = max(left, -0.5*canvas._min_active_space + s)
+                right = cell_width - left
                 bottom = vss_dio_tap_bb.top + min_actpoly_space
                 top = vdd_dio_tap_bb.bottom - min_actpoly_space
                 layouter.add_wire(net=vss, wire=poly, shape=_geo.Rect(
@@ -134,96 +133,92 @@ class _Tie(_Cell):
                         rect=vss_polych_m1_bb, bottom=0.0,
                     ))
         else: # max_diff == True
-            # vss tap
-            # First create ch to compute dimension of big diode
+            args: Dict[str, Any]
+
+            # extend vss tap
+            top = canvas._well_edge_height - ac_canvas._min_nact_well_enclosure
+            s = 0.5*canvas._min_active_space
             if pimplant is not None:
-                l_ch = layouter.wire_layout(
-                    net=vss, wire=contact, bottom=active, bottom_implant=pimplant,
-                )
-                impl_bb = l_ch.bounds(mask=pimplant.mask)
-                impl_w = impl_bb.width
-                # Compute the possible hor. expansion
-                d = cell_width - impl_w - pimplant.min_space
-                if tech.on_grid(d) < 0.0:
-                    raise NotEnoughRoom("_Tie cell width")
-                act_bb = l_ch.bounds(mask=active.mask)
-                # Maximize width
-                act_w = act_bb.width + d
-                # Maximize height
-                enc = act_bb.bottom - impl_bb.bottom
-                bottom = 0.5*pimplant.min_space + enc
-                top = canvas._well_edge_height - min_actwell_space
-                act_h = tech.on_grid(
-                    top - bottom, mult=2, rounding="floor",
+                idx = active.implant.index(pimplant)
+                enc = active.min_implant_enclosure[idx].tall()
+                args = {"implant_enclosure": enc}
+                s = max(s, enc.first)
+                if (s - _geo.epsilon) > enc.first:
+                    enc = _prp.Enclosure((s, enc.second))
+                top = min(top, canvas._well_edge_height - pimplant.min_space - enc.second)
+            else:
+                assert nimplant is not None
+                enc = None
+                args = {}
+                s = max(
+                    s, tech.computed.min_space(primitive1=active, primitive2=nimplant),
                 )
+            if nimplant is not None:
+                impl_bb = self.vddtap_lay.bounds(mask=nimplant.mask)
+                ext = max(0.0, -impl_bb.left)
             else:
-                act_w = cell_width - 2*active.min_space
-                bottom = active.min_space
-                top = canvas._well_edge_height - min_actwell_space
-                act_h = tech.on_grid(
-                    top - bottom, mult=2, rounding="floor",
+                assert pimplant is not None
+                ext = max(
+                    0.0,
+                    tech.computed.min_space(
+                        primitive1=active, primitive2=pimplant
+                    ) - 0.5*canvas._min_active_space
                 )
-
-            # diode with right dimensions
-            l_ch = layouter.wire_layout(
-                net=vss, wire=contact, bottom=active, bottom_implant=pimplant,
-                bottom_width=act_w, bottom_height=act_h,
+            act_w = cell_width - 2*ext - 2*s
+            if act_w + _geo.epsilon < active.min_width:
+                raise NotEnoughRoom(f"maximum Tie with w == {width}")
+            bottom = 0.5*canvas._min_active_space
+            shape = _geo.Rect(
+                left=0.5*(cell_width - act_w), bottom=bottom,
+                right=0.5*(cell_width + act_w), top=top,
+            )
+            layouter.add_wire(
+                net=vss, wire=active, shape=shape, implant=pimplant, **args,
             )
-            x = 0.5*cell_width
-            if pimplant is not None:
-                impl_bb = l_ch.bounds(mask=pimplant.mask)
-                y = 0.5*pimplant.min_space - impl_bb.bottom
-            else:
-                act_bb = l_ch.bounds(mask=active.mask)
-                y = active.min_space - act_bb.bottom
-            layouter.place(object_=l_ch, x=x, y=y)
 
-            # vdd tap
-            # First create ch to compute dimension of big diode
+            # extend vdd tap
+            bottom = canvas._well_edge_height + ac_canvas._min_pact_well_enclosure
+            s = 0.5*canvas._min_active_space
             if nimplant is not None:
-                l_ch = layouter.wire_layout(
-                    net=vdd, well_net=vdd, wire=contact,
-                    bottom=active, bottom_implant=nimplant, bottom_well=nwell,
-                )
-                impl_bb = l_ch.bounds(mask=nimplant.mask)
-                impl_w = impl_bb.width
-                # Compute the possible hor. expansion
-                d = cell_width - impl_w - nimplant.min_space
-                assert tech.on_grid(d) >= 0.0
-                act_bb = l_ch.bounds(mask=active.mask)
-                act_w = act_bb.width + d
-                # Maximize height
-                enc = act_bb.bottom - impl_bb.bottom
-                bottom = canvas._well_edge_height + canvas._min_active_well_enclosure
-                top = canvas._cell_height - 0.5*nimplant.min_space - enc
-                act_h = tech.on_grid(
-                    top - bottom, mult=2, rounding="floor",
+                idx = active.implant.index(nimplant)
+                enc = active.min_implant_enclosure[idx].tall()
+                args = {"implant_enclosure": enc}
+                s = max(s, enc.first)
+                if (s - _geo.epsilon) > enc.first:
+                    enc = _prp.Enclosure((s, enc.second))
+                bottom = max(bottom, canvas._well_edge_height + nimplant.min_space + enc.second)
+            else:
+                assert pimplant is not None
+                enc = None
+                args = {}
+                s = max(
+                    s, tech.computed.min_space(primitive1=active, primitive2=pimplant),
                 )
+            if pimplant is not None:
+                impl_bb = self.vsstap_lay.bounds(mask=pimplant.mask)
+                ext = max(0.0, -impl_bb.left)
             else:
-                act_w = cell_width - 2*active.min_space
-                bottom = canvas._well_edge_height + canvas._min_active_well_enclosure
-                top = canvas._cell_height - active.min_space
-                act_h = tech.on_grid(
-                    top - bottom, mult=2, rounding="floor",
+                assert nimplant is not None
+                ext = max(
+                    0.0,
+                    tech.computed.min_space(
+                        primitive1=active, primitive2=nimplant
+                    ) - 0.5*canvas._min_active_space
                 )
-
-            # diode with right dimensions
-            l_ch = layouter.wire_layout(
-                net=vdd, well_net=vdd, wire=contact,
-                bottom=active, bottom_implant=nimplant, bottom_well=nwell,
-                bottom_width=act_w, bottom_height=act_h,
+            act_w = cell_width - 2*ext - 2*s
+            if act_w + _geo.epsilon < active.min_width:
+                raise NotEnoughRoom(f"maximum Tie with w == {width}")
+            top = canvas._cell_height - 0.5*canvas._min_active_space
+            shape = _geo.Rect(
+                left=0.5*(cell_width - act_w), bottom=bottom,
+                right=0.5*(cell_width + act_w), top=top,
+            )
+            layouter.add_wire(
+                net=vdd, wire=active, shape=shape, implant=nimplant, **args,
             )
-            x = 0.5*cell_width
-            if nimplant is not None:
-                impl_bb = l_ch.bounds(mask=nimplant.mask)
-                y = canvas._cell_height - 0.5*nimplant.min_space - impl_bb.top
-            else:
-                act_bb = l_ch.bounds(mask=active.mask)
-                y = canvas._cell_height - active.min_space - act_bb.top
-            layouter.place(object_=l_ch, x=x, y=y)
 
 
-class _Diode(_Cell):
+class _Diode(_acc.ActiveColumnsCellFrame):
     def __init__(self, *,
         fab: "StdCellFactory", name: str,
     ):
@@ -239,6 +234,9 @@ class _Diode(_Cell):
         nimplant = canvas._nimplant
         pimplant = canvas._pimplant
         nwell = canvas._nwell
+        nwell_net = self.nwell_net
+        pwell = canvas._pwell
+        pwell_net = self.pwell_net
         contact = canvas._contact
         metal1 = canvas._metal1
         metal1pin = canvas._metal1pin
@@ -246,54 +244,25 @@ class _Diode(_Cell):
         ckt = self.circuit
         layouter = self._layouter
 
-        vdd = ckt.nets.vdd
-        vss = ckt.nets.vss
-
         i_ = ckt.new_net(name="i", external=True)
 
         min_actwell_space = tech.computed.min_space(primitive1=active, primitive2=nwell)
-        try:
-            s = tech.computed.min_space(primitive1=active.in_(nimplant), primitive2=nwell)
-        except:
-            pass
-        else:
-            min_actwell_space = max(min_actwell_space, s)
+        if nimplant is not None:
+            try:
+                s = tech.computed.min_space(primitive1=active.in_(nimplant), primitive2=nwell)
+            except:
+                pass
+            else:
+                min_actwell_space = max(min_actwell_space, s)
         enc = active.min_substrate_enclosure
         if enc is not None:
             min_actwell_space = max(min_actwell_space, enc.max())
 
         # Min active space without implants overlapping
-        # vss min tap
-        l_ch = layouter.wire_layout(
-            net=vss, wire=contact, rows=canvas._min_tap_chs,
-            bottom=active, bottom_implant=pimplant,
-        )
-        x = 0.5*cell_width
-        if pimplant is not None:
-            impl_bb = l_ch.bounds(mask=pimplant.mask)
-            y = 0.5*pimplant.min_space - impl_bb.bottom
-        else:
-            act_bb = l_ch.bounds(mask=active.mask)
-            y = active.min_space - act_bb.bottom
-        vss_tap_lay = layouter.place(object_=l_ch, x=x, y=y)
-        vss_tap_act_bb = vss_tap_lay.bounds(mask=active.mask)
-
-        # vdd min tap
-        l_ch = layouter.wire_layout(
-            net=vdd, well_net=vdd, wire=contact, rows=canvas._min_tap_chs,
-            bottom=active, bottom_implant=nimplant, bottom_well=nwell
-        )
-        x = 0.5*cell_width
-        if nimplant is not None:
-            impl_bb = l_ch.bounds(mask=nimplant.mask)
-            y = canvas._cell_height - 0.5*nimplant.min_space - impl_bb.top
-        else:
-            act_bb = l_ch.bounds(mask=active.mask)
-            y = canvas._cell_height - active.min_space - act_bb.top
-        vdd_tap_lay = layouter.place(object_=l_ch, x=x, y=y)
-        vdd_tap_act_bb = vdd_tap_lay.bounds(mask=active.mask)
+        vss_tap_act_bb = self.vsstap_lay.bounds(mask=active.mask)
+        vdd_tap_act_bb = self.vddtap_lay.bounds(mask=active.mask)
 
-        # vss diode
+        # ndiode
         bottom = max(
             vss_tap_act_bb.top + canvas._min_nactive_pactive_space_maxenc,
             canvas._m1_vssrail_width + metal1.min_space,
@@ -303,12 +272,13 @@ class _Diode(_Cell):
         vss_dio_x = 0.5*cell_width
         vss_dio_y = bottom + 0.5*h
         vss_dio_lay = layouter.add_wire(
-            net=vss, wire=contact, bottom=active, bottom_implant=nimplant,
+            net=i_, well_net=pwell_net, wire=contact,
+            bottom=active, bottom_implant=nimplant, bottom_well=pwell,
             x=vss_dio_x, y=vss_dio_y, bottom_height=h, top_height=h,
         )
         vss_dio_m1_bb = vss_dio_lay.bounds(mask=metal1.mask)
 
-        # vdd diode
+        # pdiode
         bottom = canvas._well_edge_height + canvas._min_active_well_enclosure
         top = min(
             vdd_tap_act_bb.bottom - canvas._min_nactive_pactive_space_maxenc,
@@ -318,7 +288,7 @@ class _Diode(_Cell):
         vdd_dio_x = 0.5*cell_width
         vdd_dio_y = top - 0.5*h
         vdd_dio_lay = layouter.add_wire(
-            net=vdd, well_net=vdd, wire=contact,
+            net=i_, well_net=nwell_net, wire=contact,
             bottom=active, bottom_implant=pimplant, bottom_well=nwell,
             x=vdd_dio_x, y=vdd_dio_y, bottom_height=h, top_height=h,
         )
@@ -1805,19 +1775,33 @@ class _Xor2(_acc.ActiveColumnsCell):
             name="q_pin", elements=(q_m1knot0, q_m1knot1), top=net1_psd0,
         )
 
+        i1_nmos0: Optional[_acc.NMOST] = None
+        i1_nmos0pad: Optional[_acc.PolyContactT] = None
+        i1_nmospad: Optional[_acc.PolyContactT] = None
+        i1_pmos0: Optional[_acc.PMOST] = None
+        i1_pmos0pad: Optional[_acc.PolyContactT] = None
+        i1_n_nmos: Optional[_acc.NMOST] = None
+        i1_n_nmospad: Optional[_acc.PolyContactT] = None
+        i1_n_pmos: Optional[_acc.PMOST] = None
+        i1_n_pmospad: Optional[_acc.PolyContactT] = None
+        i1_nmosrow0: Optional[_acc.PolyRowT] = None
+        i1_nmosrow1: Optional[_acc.PolyRowT] = None
+        i1_pmosrow0: Optional[_acc.PolyRowT] = None
+        i1_pmosrow1: Optional[_acc.PolyRowT] = None
+
         if not self.inverted:
             i1_nmos0 = self.nmos(name="i1_nmos0", net=i1, w_size="min")
             i1_nmos0pad = self.polypad(
                 name="i1_nmos0pad", net=i1, left=(i0_pass0, q_pin),
             )
-            i1_nmos0row = self.polyrow(
+            i1_nmosrow0 = self.polyrow(
                 name="i1_nmos0row", elements=(i1_nmos0pad, i1_nmos0),
             )
             i1_n_pmos = self.pmos(name="i1_n_pmos", net=_i1_n, w_size="min")
             i1_n_pmospad = self.polypad(
                 name="i1_n_pmospad", net=_i1_n, left=(i0_pass0, q_pin),
             )
-            i1_n_pmosrow = self.polyrow(
+            i1_pmosrow0 = self.polyrow(
                 name="i1_n_pmosrow", elements=(i1_n_pmospad, i1_n_pmos),
             )
             i1_pass0 = self.activecolumn(
@@ -1828,20 +1812,19 @@ class _Xor2(_acc.ActiveColumnsCell):
             i1_n_nmospad = self.polypad(
                 name="i1_n_nmospad", net=_i1_n, left=(i0_pass0, q_pin),
             )
-            i1_n_nmosrow = self.polyrow(
+            i1_nmosrow0 = self.polyrow(
                 name="i1_n_nmosrow", elements=(i1_n_nmospad, i1_n_nmos)
             )
             i1_pmos0 = self.pmos(name="i1_pmos0", net=i1, w_size="min")
             i1_pmos0pad = self.polypad(
                 name="i1_pmos0pad", net=i1, left=(i0_pass0, q_pin),
             )
-            i1_pmos0row = self.polyrow(
+            i1_pmosrow0 = self.polyrow(
                 name="i1_pmos0row", elements=(i1_pmos0pad, i1_pmos0),
             )
             i1_pass0 = self.activecolumn(
                 name="i1_pass0", connect=False, elements=(i1_n_nmos, i1_pmos0),
             )
-
         q_nsd = self.signal_nsd(name="q_nsd", net=q, with_contact=True)
         q_psd = self.signal_psd(name="q_psd", net=q, with_contact=False)
         q_nsdrow = self.m1row(name="q_nsdrow", elements=(q_m1knot0, q_nsd))
@@ -1868,6 +1851,8 @@ class _Xor2(_acc.ActiveColumnsCell):
         i1_n_pad0 = self.polypad(name="i1_n_pad0", net=_i1_n, left=i0_n_pass)
         i1_n_m1knot = self.m1knot(name="i1_n_m1knot", net=_i1_n)
         if not self.inverted:
+            assert i1_n_pmospad is not None, "Internal error"
+
             i1_n_nmos = self.nmos(name="i1_n_nmos", net=_i1_n, w_size="min")
             i1_n_m1row = self.m1row(
                 name="i1_n_m1row", elements=(i1_n_pmospad, i1_n_m1knot),
@@ -1880,6 +1865,8 @@ class _Xor2(_acc.ActiveColumnsCell):
                 name="i1_pass1", connect=False, elements=(i1_n_nmos, i1_pmos0),
             )
         else:
+            assert i1_n_nmospad is not None, "Internal error"
+
             i1_nmos0 = self.nmos(name="i1_nmos0", net=i1, w_size="min")
             i1_nmospad = self.polypad(name="i1_nmospad", net=i1)
             i1_n_m1row = self.m1row(
@@ -1902,24 +1889,31 @@ class _Xor2(_acc.ActiveColumnsCell):
         i1_nmos1 = self.nmos(name="i1_nmos1", net=i1, w_size="min")
         i1_pmos1 = self.pmos(name="i1_pmos1", net=i1, w_size="min")
         if not self.inverted:
+            assert i1_pmos0 is not None
+            assert i1_nmos0pad is not None
+
             i1_nmos1pad = self.polypad(name="i1_nmos1pad", net=i1, left=i1_pass1)
             i1_nmos1knot = self.m1knot(name="i1_nmos1knot", net=i1)
-            i1_nmos1row = self.polyrow(name="i1_nmos1row", elements=(i1_nmos1pad, i1_nmos1))
+            i1_nmosrow1 = self.polyrow(name="i1_nmos1row", elements=(i1_nmos1pad, i1_nmos1))
             i1_m1row = self.m1row(
                 name="i1_m1row", elements=(i1_nmos0pad, i1_nmos1knot),
             )
             i1_pmospad = self.polypad(name="i1_pmospad", net=i1)
-            i1_pmosrow = self.polyrow(
+            i1_pmosrow1 = self.polyrow(
                 name="i1_pmosrow", elements=(i1_pmos0, i1_pmospad, i1_pmos1),
             )
             i1_pin = self.m1pin(name="i1_pin", elements=(i1_nmos1pad, i1_nmos1knot, i1_pmospad))
         else:
-            i1_nmosrow = self.polyrow(
+            assert i1_nmos0 is not None
+            assert i1_nmospad is not None
+            assert i1_pmos0pad is not None
+
+            i1_nmosrow1 = self.polyrow(
                 name="i1_nmosrow", elements=(i1_nmos0, i1_nmospad, i1_nmos1),
             )
             i1_pmos1pad = self.polypad(name="i1_pmos1pad", net=i1, left=i1_pass1)
             i1_pmos1knot = self.m1knot(name="i1_pmos1knot", net=i1)
-            i1_pmos1row = self.polyrow(name="i1_pmos1row", elements=(i1_pmos1pad, i1_pmos1))
+            i1_pmosrow1 = self.polyrow(name="i1_pmos1row", elements=(i1_pmos1pad, i1_pmos1))
             i1_m1row = self.m1row(
                 name="i1_m1row", elements=(i1_pmos0pad, i1_pmos1knot),
             )
@@ -1929,15 +1923,14 @@ class _Xor2(_acc.ActiveColumnsCell):
             name="i1_inv", connect=False, elements=(i1_nmos1, i1_pmos1),
         )
 
+
         i1_n_nsd = self.signal_nsd(name="i1_n_nsd", net=_i1_n, with_contact=True)
         i1_n_psd = self.signal_psd(name="i1_n_psd", net=_i1_n, with_contact=True)
         i1_n_pad = self.polypad(name="i1_n_pad", net=_i1_n)
+        mos = i1_n_nmos if not self.inverted else i1_n_pmos
+        assert mos is not None
         i1_n_polyrow = self.polyrow(
-            name="i1_n_polyrow", elements=(
-                i1_n_pad0,
-                i1_n_nmos if not self.inverted else i1_n_pmos,
-                i1_n_pad,
-            ),
+            name="i1_n_polyrow", elements=(i1_n_pad0, mos, i1_n_pad),
         )
         i1_n_m1col1 = self.m1column(
             name="i1_n_m1col1", elements=(i1_n_nsd, i1_n_pad, i1_n_psd),
@@ -1955,18 +1948,15 @@ class _Xor2(_acc.ActiveColumnsCell):
                 i1_inv, i1_n_sds,
             ),
             polyrows=(
-                self.multipolyrow(name="nmos_multirow", rows=(
-                    i0_nmosrow,
-                    i1_nmos0row if not self.inverted else i1_n_nmosrow,
-                    i1_nmos1row if not self.inverted else i1_nmosrow,
-                )),
+                self.multipolyrow(
+                    name="nmos_multirow", rows=(i0_nmosrow, i1_nmosrow0, i1_nmosrow1),
+                ),
                 self.multipolyrow(name="conn_multirow", rows=(
                     i0_n_polyrow, i1_n_polyrow,
                 )),
-                i1_n_pmosrow.multipolyrow if not self.inverted else i1_pmos0row.multipolyrow,
+                i1_pmosrow0.multipolyrow,
                 self.multipolyrow(name="pmos_multirow", rows=(
-                    i0_pmosrow,
-                    i1_pmosrow if not self.inverted else i1_pmos1row,
+                    i0_pmosrow, i1_pmosrow1,
                 )),
             ),
             m1rows=(
@@ -3171,6 +3161,93 @@ class _DFFnR(_acc.ActiveColumnsCell):
         )
 
 
+class _Gallery(_fab.FactoryCell["StdCellFactory"]):
+    def __init__(self, *, name: str, fab: "StdCellFactory", cells: Iterable[_cell.Cell]):
+        cells = tuple(cells)
+
+        canvas = fab.canvas
+
+        super().__init__(name=name, fab=fab)
+
+        ckt = self.new_circuit()
+        layouter = self.new_circuitlayouter()
+
+        l = len(cells)
+
+        cells2 = tuple(reversed(cells))
+
+        # Make a shuffled row of cells for more DRC checking
+        def shuffled_i(i: int) -> int:
+            is_odd = (i%2) == 1
+            if not is_odd:
+                return l - (i//2) - 1
+            else:
+                return (i//2)
+        cells3 = tuple(cells[shuffled_i(i)] for i in range(l))
+
+        vss_ports = []
+        vdd_ports = []
+        x0 = x1 = x2 = 0.0
+        for i, cell in enumerate(cells):
+            inst = ckt.instantiate(cell, name=f"{cell.name}[0]")
+
+            for port in inst.ports:
+                if port.name == "vss":
+                    vss_ports.append(port)
+                elif port.name == "vdd":
+                    vdd_ports.append(port)
+                else:
+                    ckt.new_net(
+                        name=f"{inst.name}.{port,name}", external=False, childports=port,
+                    )
+
+            layouter.place(inst, x=x0, y=0.0)
+            x0 += cast(_Cell, cell).width
+
+            cell2 = cells2[i]
+            inst = ckt.instantiate(cell2, name=f"{cell2.name}[1]")
+
+            for port in inst.ports:
+                if port.name == "vss":
+                    vss_ports.append(port)
+                elif port.name == "vdd":
+                    vdd_ports.append(port)
+                else:
+                    ckt.new_net(
+                        name=f"{inst.name}.{port,name}", external=False, childports=port,
+                    )
+
+            layouter.place(inst, x=x1, y=0.0, rotation=_geo.Rotation.MX)
+            x1 += cast(_Cell, cell2).width
+
+            cell3 = cells3[i]
+            inst = ckt.instantiate(cell3, name=f"{cell3.name}[2]")
+
+            for port in inst.ports:
+                if port.name == "vss":
+                    vss_ports.append(port)
+                elif port.name == "vdd":
+                    vdd_ports.append(port)
+                else:
+                    ckt.new_net(
+                        name=f"{inst.name}.{port,name}", external=False, childports=port,
+                    )
+
+            layouter.place(inst, x=x2, y=2*canvas._cell_height, rotation=_geo.Rotation.MX)
+            x2 += cast(_Cell, cell3).width
+
+        ckt.new_net(name="vss", external=True, childports=vss_ports)
+        ckt.new_net(name="vdd", external=True, childports=vdd_ports)
+
+        # Set boundary
+        assert abs(x0 - x1) < _geo.epsilon, "Internal error"
+        assert abs(x0 - x2) < _geo.epsilon, "Internal error"
+        layouter.layout.boundary = _geo.Rect(
+            left=0.0, bottom=-canvas._cell_height,
+            right=x0, top=2*canvas._cell_height,
+        )
+
+
 class StdCellFactory(_fab.CellFactory[_Cell]):
     def __init__(self, *,
         lib: _lbry.RoutingGaugeLibrary, cktfab: _ckt.CircuitFactory,
@@ -3208,6 +3285,7 @@ class StdCellFactory(_fab.CellFactory[_Cell]):
         self.add_xors()
         self.add_latches()
         self.add_flops()
+        self.add_gallery()
 
     def add_fillers(self):
         """Add a set of fill cells to the library.
@@ -3301,3 +3379,6 @@ class StdCellFactory(_fab.CellFactory[_Cell]):
     def add_flops(self):
         self.new_cell(name="dff_x1", cell_class=_DFF, drive=1)
         self.new_cell(name="dffnr_x1", cell_class=_DFFnR, drive=1)
+
+    def add_gallery(self):
+        self.new_cell(name="Gallery", cell_class=_Gallery, cells=self.lib.cells)

{c4m_flexcell-0.4.0.dev23 → c4m_flexcell-0.4.2}/c4m_flexcell.egg-info/PKG-INFO

@@ -1,6 +1,6 @@
 Metadata-Version: 2.1
-Name: c4m-flexcell
-Version: 0.4.0.dev23
+Name: c4m_flexcell
+Version: 0.4.2
 Summary: PDKMaster based scalable standard cell library
 Author: Staf Verhaegen
 Author-email: staf@fibraservi.eu
@@ -10,6 +10,9 @@ Project-URL: Bug Tracker, https://gitlab.com/Chips4Makers/c4m-flexcell/issues
 Requires-Python: ~=3.6
 Description-Content-Type: text/markdown
 License-File: LICENSE.md
+Requires-Dist: setuptools
+Requires-Dist: nest-asyncio
+Requires-Dist: PDKMaster~=0.10.0
 
 # Flexible, scalable, standard cell library
 
@@ -19,9 +22,13 @@ Standard cells are introduced into an [ASIC](https://en.wikipedia.org/wiki/Appli
 
 ## Release History
 
-Current development is done on a development branch for version 0.4. Documentation/README will
-be updated together with the release of this version.
-
+* [v0.4.2](https://gitlab.com/Chips4Makers/c4m-flexcell/-/commits/v0.10.2): only internal
+  improvements
+* v0.4.1:
+  major reworking of the code. A new class ActiveColumnsCell has been introduced to generate the layouts of the standard cells. This removes the lambda based dimensions from the cells to compute them all from the design rules.  
+  All cells were converter to this new layout method and this should allow to make standard cell libraries with much lower height of the cells. Compatiblity function are provided so that layout spec can be derived as was done previously as based on a lambda value.  
+  v0.4.0 had only dev releases and code was rebased and squashed for this release.
+* v0.3.3: bug fix; remove public 0.3.2 release
 * v0.3.2: code cleansing, bug fixing, update dependencies
 * v0.3.1: small update for Coriolis export
 * v0.3.0: Update for [release v0.9.0 of PDKMaster](https://gitlab.com/Chips4Makers/PDKMaster/-/blob/v0.9.0/ReleaseNotes/v0.9.0.md); replace Library-> StdCellFactory to follow common usage of a factory to generate cells.
@@ -39,7 +46,5 @@ In future options are planned so libraries can be generated for different target
 ## Status
 
 This repository is currently considered experimental code with no backwards compatibility guarantees whatsoever.  
-This development is done in a development branch for new layout generation code.
-When this development is done it will be released as version 0.4.0.  
 Current implementation is based on the topology of the Coriolis nsxlib standard cells with some area improvements but not yet with optimal area use. For v0.1 of this library a total replacement of the layout generation is planned fully based on minimized area for the technology design rules.  
 If interested head over to [gitter](https://gitter.im/Chips4Makers/community) for further discussion.

c4m_flexcell-0.4.2/c4m_flexcell.egg-info/requires.txt

@@ -0,0 +1,3 @@
+setuptools
+nest-asyncio
+PDKMaster~=0.10.0

{c4m_flexcell-0.4.0.dev23 → c4m_flexcell-0.4.2}/dev-requirements.txt

@@ -5,3 +5,4 @@ sphinx
 build
 setuptools
 setuptools_scm
+nest-asyncio

{c4m_flexcell-0.4.0.dev23 → c4m_flexcell-0.4.2}/dodo.py

@@ -86,7 +86,7 @@ def task_install():
 
     return {
         "title": lambda _: "Installing python module",
-        "file_dep": c4m_py_files,
+        "file_dep": (top_dir.joinpath("setup.py"), *c4m_py_files),
         "targets": (flexcell_inst_dir,),
         "actions": (
             f"{pip} install --no-deps {top_dir}",

{c4m_flexcell-0.4.0.dev23 → c4m_flexcell-0.4.2}/setup.py

@@ -5,7 +5,7 @@ def local_scheme(version):
     if version.tag and not version.distance:
         return version.format_with("")
     else:
-        return version.format_choice("", "+{node}.dirty")
+        return version.format_choice("+{node}", "+{node}.dirty")
 
 # Don't seem to have much success with exclude parameter of find_packages()
 _packages = list(filter(lambda pkg: pkg[:4] != "test", find_packages()))
@@ -28,7 +28,7 @@ setup(
     license="GPL-2.0-or-later OR AGPL-3.0-or-later OR CERN-OHL-S-2.0+",
     python_requires="~=3.6",
     setup_requires=["setuptools_scm"],
-    install_requires=["setuptools", "PDKMaster~=0.9.4"],
+    install_requires=["setuptools", "nest-asyncio", "PDKMaster~=0.10.0"],
     include_package_data=True,
     packages=_packages,
     project_urls={

c4m_flexcell-0.4.0.dev23/c4m_flexcell.egg-info/requires.txt

@@ -1,2 +0,0 @@
-setuptools
-PDKMaster~=0.9.4