bust 0.14.0.dev0__tar.gz → 1.0.0a0__tar.gz

bust-1.0.0a0/LICENSE

@@ -0,0 +1,201 @@
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bust-1.0.0a0/NOTICE

@@ -0,0 +1,5 @@
+bust
+Copyright 2017-2026 Ola Grottvik
+
+This product is licensed under the Apache License, Version 2.0.
+See the LICENSE file for the full license text.

bust-1.0.0a0/PKG-INFO

@@ -0,0 +1,108 @@
+Metadata-Version: 2.4
+Name: bust
+Version: 1.0.0a0
+Summary: Utility for simply creating and modifying VHDL bus slave modules
+Author-email: Ola Groettvik <olagrottvik@gmail.com>
+License-Expression: Apache-2.0
+Project-URL: Homepage, https://github.com/logvik-org/bust
+Keywords: vhdl,bus,axi,ipbus,slave,generator
+Requires-Python: >=3.9.0
+Description-Content-Type: text/markdown
+License-File: LICENSE
+License-File: NOTICE
+Requires-Dist: docopt>=0.6.2
+Requires-Dist: pylatexenc>=2.1
+Requires-Dist: curses-menu>=0.9.0
+Requires-Dist: prettytable>=2.5.0
+Requires-Dist: Jinja2<4.0,>=3.1.5
+Provides-Extra: dev
+Requires-Dist: pytest; extra == "dev"
+Requires-Dist: pytest-cov; extra == "dev"
+Requires-Dist: pylint; extra == "dev"
+Requires-Dist: mypy; extra == "dev"
+Requires-Dist: pydocstyle; extra == "dev"
+Dynamic: license-file
+
+![Workflow status](https://github.com/logvik-org/bust/actions/workflows/python_tests.yml/badge.svg)
+
+# bust bus tool
+
+Utility for simply creating and modifying VHDL bus slave modules.
+
+## Concept
+
+The main goal of the project is to able to automatically create and modify VHDL bus slave modules based on a simple definition format.
+By employing VHDL records the handling of the registers can be completely hidden in a module separate from the rest of the design.
+Every supported bus protocol is a thin wrapper (an "endpoint") around a small protocol-agnostic local bus, so the register-map logic stays the same regardless of bus. The hardware side references each field by name through `to_hw`/`from_hw` records, with software/hardware access modes and side effects (read/write clear/set, single-pulse, hardware set/clear, enumerated values) described in the JSON.
+
+## Bus support
+
+bust currently supports these bus standards:
+
+- [AXI4-lite](https://en.wikipedia.org/wiki/Advanced_eXtensible_Interface#AXI4-Lite)
+- [IPBus](https://ipbus.web.cern.ch/ipbus/)
+- [SBI](https://github.com/UVVM/UVVM) (Simple Bus Interface, as used by UVVM)
+- [Avalon-MM](https://www.intel.com/content/www/us/en/docs/programmable/683091/current/introduction-to-the-interface-specifications.html)
+- [Wishbone](https://wishbone-interconnect.readthedocs.io/)
+- [APB](https://developer.arm.com/documentation/ihi0024/latest/) (AMBA APB)
+
+## Requirements
+
+bust is tested on python 3.9, 3.10, 3.11, 3.12, 3.13 and 3.14.
+
+bust does NOT support python 2.7 and neither should you!
+
+## Getting Started
+
+Install the latest release by using pip:
+
+`pip install bust`
+
+pip skips pre-releases (alpha, beta and release candidates) unless you ask for
+them. To try the newest pre-release:
+
+`pip install --pre bust`
+
+### Usage
+
+`bust FILE [-o DIR]`
+
+`bust --version`
+
+`bust -h | --help`
+
+## Examples
+
+The examples folder contains JSON files for the bus types supported.
+The files are human-readable to the point that you can create your own from this template alone.
+The folder also contains the output files generated based on the JSON files.
+
+### Simulation
+bust does not generate simulator-specific run scripts. There are too many simulators and flows to pick a one-size-fits-all approach, so compiling and running the output is left to you. The repository's own simulation (under `sim/`) exists only to verify that bust itself works and that the generated example designs simulate; it is not a user-facing flow.
+
+The generated testbenches use UVVM - which can be cloned from their [GitHub page](https://github.com/UVVM/UVVM) - and, for IPBus, the vip_ipbus VIP.
+
+### IPBus
+IPBus requires the bus package file from the [IPBus firmware repo](https://github.com/ipbus/ipbus-firmware) and the custom [IPBus BFM repo](https://github.com/olagrottvik/vip_ipbus).
+
+See the example files for how you point to the specific folders.
+
+## Latest Development Version (Bleeding Edge)
+
+To run bust from a clone of the repository, see the development setup in
+[CONTRIBUTING.md](CONTRIBUTING.md).
+
+
+## Release Notes
+
+Release notes are in [CHANGELOG.md](CHANGELOG.md), and each release is on the [Releases page](https://github.com/logvik-org/bust/releases).
+
+
+## Contributing
+
+If you have ideas on how to improve the project, please review [CONTRIBUTING.md](CONTRIBUTING.md) for details. Note that we also have a [Code of Conduct](CODE_OF_CONDUCT.md).
+
+
+## License
+
+This project is licensed under the Apache License, Version 2.0 - see [LICENSE](LICENSE) for details.

bust-1.0.0a0/README.md

@@ -0,0 +1,83 @@
+![Workflow status](https://github.com/logvik-org/bust/actions/workflows/python_tests.yml/badge.svg)
+
+# bust bus tool
+
+Utility for simply creating and modifying VHDL bus slave modules.
+
+## Concept
+
+The main goal of the project is to able to automatically create and modify VHDL bus slave modules based on a simple definition format.
+By employing VHDL records the handling of the registers can be completely hidden in a module separate from the rest of the design.
+Every supported bus protocol is a thin wrapper (an "endpoint") around a small protocol-agnostic local bus, so the register-map logic stays the same regardless of bus. The hardware side references each field by name through `to_hw`/`from_hw` records, with software/hardware access modes and side effects (read/write clear/set, single-pulse, hardware set/clear, enumerated values) described in the JSON.
+
+## Bus support
+
+bust currently supports these bus standards:
+
+- [AXI4-lite](https://en.wikipedia.org/wiki/Advanced_eXtensible_Interface#AXI4-Lite)
+- [IPBus](https://ipbus.web.cern.ch/ipbus/)
+- [SBI](https://github.com/UVVM/UVVM) (Simple Bus Interface, as used by UVVM)
+- [Avalon-MM](https://www.intel.com/content/www/us/en/docs/programmable/683091/current/introduction-to-the-interface-specifications.html)
+- [Wishbone](https://wishbone-interconnect.readthedocs.io/)
+- [APB](https://developer.arm.com/documentation/ihi0024/latest/) (AMBA APB)
+
+## Requirements
+
+bust is tested on python 3.9, 3.10, 3.11, 3.12, 3.13 and 3.14.
+
+bust does NOT support python 2.7 and neither should you!
+
+## Getting Started
+
+Install the latest release by using pip:
+
+`pip install bust`
+
+pip skips pre-releases (alpha, beta and release candidates) unless you ask for
+them. To try the newest pre-release:
+
+`pip install --pre bust`
+
+### Usage
+
+`bust FILE [-o DIR]`
+
+`bust --version`
+
+`bust -h | --help`
+
+## Examples
+
+The examples folder contains JSON files for the bus types supported.
+The files are human-readable to the point that you can create your own from this template alone.
+The folder also contains the output files generated based on the JSON files.
+
+### Simulation
+bust does not generate simulator-specific run scripts. There are too many simulators and flows to pick a one-size-fits-all approach, so compiling and running the output is left to you. The repository's own simulation (under `sim/`) exists only to verify that bust itself works and that the generated example designs simulate; it is not a user-facing flow.
+
+The generated testbenches use UVVM - which can be cloned from their [GitHub page](https://github.com/UVVM/UVVM) - and, for IPBus, the vip_ipbus VIP.
+
+### IPBus
+IPBus requires the bus package file from the [IPBus firmware repo](https://github.com/ipbus/ipbus-firmware) and the custom [IPBus BFM repo](https://github.com/olagrottvik/vip_ipbus).
+
+See the example files for how you point to the specific folders.
+
+## Latest Development Version (Bleeding Edge)
+
+To run bust from a clone of the repository, see the development setup in
+[CONTRIBUTING.md](CONTRIBUTING.md).
+
+
+## Release Notes
+
+Release notes are in [CHANGELOG.md](CHANGELOG.md), and each release is on the [Releases page](https://github.com/logvik-org/bust/releases).
+
+
+## Contributing
+
+If you have ideas on how to improve the project, please review [CONTRIBUTING.md](CONTRIBUTING.md) for details. Note that we also have a [Code of Conduct](CODE_OF_CONDUCT.md).
+
+
+## License
+
+This project is licensed under the Apache License, Version 2.0 - see [LICENSE](LICENSE) for details.

bust-1.0.0a0/bust/__init__.py

@@ -0,0 +1,65 @@
+"""bust - Bus Utility for Simplified VHDL.
+
+bust is a Python tool for creating and modifying VHDL bus slave modules.
+It generates complete VHDL code including register interfaces, testbenches,
+documentation, and language-specific header files from simple JSON configuration.
+
+Supported bus standards:
+    - AXI4-Lite
+    - IPBus
+
+Main components:
+    - Module: Bus slave module definition
+    - Register: Individual register configuration
+    - Field: Bitfield within a register
+    - Bus: Bus interface configuration
+    - Header: Language header file generation
+    - Documentation: LaTeX documentation generation
+
+Package structure:
+    - core: Domain models (Module, Bus, Register, Field, Enums)
+    - generators: Code generation (VHDL, headers, documentation, testbenches)
+    - validation: VHDL identifier and configuration validation
+    - utils: File I/O, JSON parsing, and string formatting utilities
+    - jinja_utils: Jinja2 template utilities
+"""
+
+# Import core domain classes for convenience
+from bust.core import (
+    Module,
+    Bus,
+    Register,
+    Field,
+    RegisterMode,
+    RegisterType,
+    FieldType,
+)
+
+# Import generator classes
+from bust.generators import (
+    HeaderGenerator,
+    DocumentationGenerator,
+    GeneratorFactory,
+)
+
+# Backward compatibility aliases
+Header = HeaderGenerator
+Documentation = DocumentationGenerator
+
+__all__ = [
+    # Core domain classes
+    "Module",
+    "Bus",
+    "Register",
+    "Field",
+    "RegisterMode",
+    "RegisterType",
+    "FieldType",
+    # Generator classes
+    "HeaderGenerator",
+    "DocumentationGenerator",
+    "GeneratorFactory",
+    # Backward compatibility
+    "Header",
+    "Documentation",
+]

{bust-0.14.0.dev0 → bust-1.0.0a0}/bust/__main__.py

@@ -1,22 +1,18 @@
 #!/usr/bin/env python3
-"""bust register tool
+"""bust register tool.
 
 Usage:
-  bust.py FILE [-o DIR] [[[-F | -f] [-u] [-d | -p] [-b] [-t] [-i] [-m]] | [-a] | [-c | -e]]
-  bust.py --version
-  bust.py -h | --help
+  bust FILE [-o DIR] [[[-F | -f] [-d | -p] [-i]] | [-a] | [-c | -e]]
+  bust --version
+  bust -h | --help
 
 Options:
   -o DIR         Specify output directory. Overrides settings (either JSON dir, or specified project dir in JSON)
-  -f             Force overwrite of existing files except module top level VHDL file
-  -F             Force overwrite of ALL existing files
-  -u             Try to update top-level file - MAY OVERWRITE USER EDITS!
+  -f             Force overwrite of existing files (the top-level wrapper is a fixed, regenerated file)
+  -F             Alias for -f, kept for compatibility
   -d             Do not generate documentation (neither LaTeX nor PDF)
   -p             Do not generate PDF from LaTeX
-  -b             Do not generate the bus VHDL package file
-  -t             Do not generate the testbench VHDL file and the simulation scripts
   -i             Do not generate the include header files (.h, .hpp & .py)
-  -m             Do not generate the module VHDL files
   -a             Update register addresses and save JSON file
   -e             Edit the JSON file
   -c             Create a new JSON file
@@ -31,14 +27,15 @@ Arguments:
 from docopt import docopt
 import sys
 import logging
-
-from bust.utils import json_parser, write_string_to_file
-from bust.module import Module
-from bust.bus import Bus
-from bust.header import Header
-from bust.documentation import Documentation
+from typing import Dict, Union
+
+from bust.utils.json_utils import json_parser
+from bust.utils.file_utils import write_string_to_file
+from bust.core.module import Module
+from bust.core.bus import Bus
+from bust.generators.header_generator import Header
+from bust.generators.documentation_generator import Documentation
 from bust.settings import Settings
-from bust.testbench import Testbench
 from bust.generation import generate_output
 from bust.exceptions import (
     FormatError,
@@ -75,13 +72,25 @@ def main():
             json_file = args["FILE"]
 
             if args["-c"] and json_file is not None:
-                e = Editor(False, json_file)
-                e.show_menu()
+                try:
+                    e = Editor(False, json_file)
+                    e.show_menu()
+                except Exception as e:
+                    logger.error("Failed to create new JSON file: " + json_file)
+                    logger.error(f"{type(e).__name__}: {e}")
+                    logger.debug("Detailed traceback:", exc_info=True)
+                    exit(1)
                 exit()
 
             if args["-e"] and json_file is not None:
-                e = Editor(True, json_file)
-                e.show_menu()
+                try:
+                    editor = Editor(True, json_file)
+                    editor.show_menu()
+                except Exception as e:
+                    logger.error("Failed to open editor for " + json_file)
+                    logger.error(f"{type(e).__name__}: {e}")
+                    logger.debug("Detailed traceback:", exc_info=True)
+                    exit(1)
                 exit()
 
             logger.info("Parsing file: " + json_file + "...")
@@ -93,7 +102,6 @@ def main():
                 module = Module(json_dict["module"], bus, settings)
                 header = Header(module)
                 documentation = Documentation(module)
-                testbench = Testbench(module, bus.get_VHDL_generator(), settings)
 
             except (
                 FormatError,
@@ -104,15 +112,19 @@ def main():
                 NotImplementedError,
             ) as e:
                 logger.error(str(e))
+                if hasattr(e, "__cause__") and isinstance(e.__cause__, ValueError):
+                    logger.error(str(e.__cause__))
+                logger.debug("Detailed traceback:", exc_info=True)
                 exit(1)
 
             except Exception as e:
-                logger.error("\nERROR:\nAn unknown error has occurred...")
-                logger.debug(str(e))
+                logger.error("An unknown error has occurred...")
+                logger.error(f"{type(e).__name__}: {e}")
+                logger.debug("Detailed traceback:", exc_info=True)
                 exit(1)
 
             # File generation settings
-            gs = {}
+            gs: Dict[str, Union[bool, str]] = {}
 
             if args["-o"] is None:
                 gs["dir"] = settings.project_path
@@ -120,26 +132,7 @@ def main():
                 gs["dir"] = args["-o"]
 
             # Check if force overwrite is set
-            gs["force_ow"] = False
-            gs["force_ow_top"] = False
-            if args["-F"]:
-                gs["force_ow"] = True
-                gs["force_ow_top"] = True
-            elif args["-f"]:
-                gs["force_ow"] = True
-
-            # Check if top-level are to be updated
-            gs["update_top"] = False
-            if args["-u"]:
-                gs["update_top"] = True
-                gs["force_ow_top"] = True
-
-            if bus.bus_type == "axi":
-                gs["gen_bus"] = True
-            else:
-                gs["gen_bus"] = False
-            if args["-b"]:
-                gs["gen_bus"] = False
+            gs["force_ow"] = bool(args["-F"] or args["-f"])
 
             gs["gen_doc"] = True
             gs["gen_pdf"] = True
@@ -149,21 +142,15 @@ def main():
             elif args["-p"]:
                 gs["gen_pdf"] = False
 
-            gs["gen_tb"] = True
-            if args["-t"]:
-                gs["gen_tb"] = False
-
             gs["gen_header"] = True
             if args["-i"]:
                 gs["gen_header"] = False
 
-            gs["gen_mod"] = True
-            if args["-m"]:
-                gs["gen_mod"] = False
+            gs["gen_localbus"] = True
 
             if args["-a"]:
                 module.update_addresses()
-                json = module.return_JSON(True)
+                json = module.to_json(True)
                 try:
                     write_string_to_file(json, json_file, ".")
                 except Exception as e:
@@ -171,12 +158,17 @@ def main():
                     print(e)
                     return
             else:
-                generate_output(
-                    settings, bus, module, header, documentation, testbench, gs
-                )
+                try:
+                    generate_output(settings, bus, module, header, documentation, gs)
+                except Exception as e:
+                    logger.error("An error occurred during output generation...")
+                    logger.error(f"{type(e).__name__}: {e}")
+                    logger.debug("Detailed traceback:", exc_info=True)
+                    exit(1)
 
     except Exception:
         logger.exception("An unresolvable error has occurred...")
+        logger.debug("Detailed traceback:", exc_info=True)
         exit(1)
 
     sys.exit(0)

bust-1.0.0a0/bust/_version.py

@@ -0,0 +1 @@
+__VERSION__ = "1.0.0a0"

bust-1.0.0a0/bust/bus.py

@@ -0,0 +1,9 @@
+"""Bus module for bust.
+
+This module is a backward compatibility shim. Import from bust.core.bus instead.
+"""
+
+# Re-export from new location for backward compatibility
+from bust.core.bus import Bus
+
+__all__ = ["Bus"]

bust-1.0.0a0/bust/config_wrapper.py

@@ -0,0 +1,9 @@
+"""Configuration validation utilities for bust.
+
+This module is a backward compatibility shim. Import from bust.validation.config_validator instead.
+"""
+
+# Re-export from new location for backward compatibility
+from bust.validation.config_validator import ConfigWrapper
+
+__all__ = ["ConfigWrapper"]