bust 0.13.2__tar.gz → 0.14.0.dev0__tar.gz

{bust-0.13.2 → bust-0.14.0.dev0}/PKG-INFO

@@ -1,6 +1,6 @@
 Metadata-Version: 2.1
 Name: bust
-Version: 0.13.2
+Version: 0.14.0.dev0
 Summary: Utility for simply creating and modifying VHDL bus slave modules
 Home-page: http://github.com/olagrottvik/bust
 Author: Ola Groettvik

bust-0.14.0.dev0/bust/_version.py

@@ -0,0 +1 @@
+__VERSION__ = "0.14.0-dev"

{bust-0.13.2 → bust-0.14.0.dev0}/bust/bus_vhdl_gen.py

@@ -475,7 +475,7 @@ class BusVHDLGen:
                     par += sig_name + reg.name + " <= wdata;\n"
                 elif reg.sig_type == "slv":
                     par += sig_name + reg.name + " <= wdata("
-                    par += str(reg.length - 1) + " downto 0);\n"
+                    par += str(reg.width - 1) + " downto 0);\n"
                 elif reg.sig_type == "sl":
                     par += sig_name + reg.name + " <= wdata(0);\n"
 
@@ -679,7 +679,7 @@ class BusVHDLGen:
 
             elif reg.sig_type == "slv":
                 par += "reg_data_out("
-                par += str(reg.length - 1) + " downto 0) <= "
+                par += str(reg.width - 1) + " downto 0) <= "
                 if reg.mode == "rw":
                     par += "axi_rw_regs_i."
                 elif reg.mode == "ro":
@@ -862,7 +862,7 @@ class BusVHDLGen:
                     par += sig_name + reg.name + " <= ipb_in.ipb_wdata;\n"
                 elif reg.sig_type == "slv":
                     par += sig_name + reg.name + " <= ipb_in.ipb_wdata("
-                    par += str(reg.length - 1) + " downto 0);\n"
+                    par += str(reg.width - 1) + " downto 0);\n"
                 elif reg.sig_type == "sl":
                     par += sig_name + reg.name + " <= ipb_in.ipb_wdata(0);\n"
                 if reg.stall:
@@ -972,7 +972,7 @@ class BusVHDLGen:
 
             elif reg.sig_type == "slv":
                 par += "reg_data_out("
-                par += str(reg.length - 1) + " downto 0) <= "
+                par += str(reg.width - 1) + " downto 0) <= "
                 if reg.mode == "rw":
                     par += "ipb_rw_regs_i."
                 elif reg.mode == "ro":

{bust-0.13.2 → bust-0.14.0.dev0}/bust/documentation.py

@@ -45,7 +45,7 @@ class Documentation(object):
                 + "} & "
             )
             p += reg.sig_type.upper() + " & "
-            p += str(reg.length) + " & "
+            p += str(reg.width) + " & "
             p += r"\texttt{"
             p += "0x" + format(int(reg.reset, 16), "X") + "} \\\\\n"
             p += r"\hline" + "\n"
@@ -72,16 +72,16 @@ class Documentation(object):
             s += utf8tolatex(reg.description) + r" \regnewline" + "\n"
             s += indent_string(r"\label{" + reg.name + "}\n")
 
-            if reg.length < self.module.data_width:
+            if reg.width < self.module.data_width:
                 p = r"\regfield{unused}{"
-                p += str(self.module.data_width - reg.length) + "}{"
-                p += str(reg.length) + "}{-}\n"
+                p += str(self.module.data_width - reg.width) + "}{"
+                p += str(reg.width) + "}{-}\n"
                 s += indent_string(p)
 
             if reg.sig_type != "fields":
 
-                p = r"\regfield{}{" + str(reg.length) + "}{0}{"
-                if reg.length < 2:
+                p = r"\regfield{}{" + str(reg.width) + "}{0}{"
+                if reg.width < 2:
                     p += str(int(reg.reset, 16))
                 else:
                     p += "{0x" + format(int(reg.reset, 16), "X") + "}"
@@ -92,9 +92,9 @@ class Documentation(object):
             else:
                 for field in reversed(reg.fields):
                     p = r"\regfield{" + utf8tolatex(field.name) + "}{"
-                    p += str(field.length) + "}{"
+                    p += str(field.width) + "}{"
                     p += str(field.pos_low) + "}{"
-                    if field.length < 2:
+                    if field.width < 2:
                         p += str(int(field.reset, 16))
                     else:
                         p += "{0x" + format(int(field.reset, 16), "X") + "}"
@@ -106,7 +106,7 @@ class Documentation(object):
             if reg.sig_type == "fields":
 
                 p = r"\begin{regdesc}\begin{reglist}["
-                # Get the longest field name and indent the list based on that length
+                # Get the longest field name and indent the list based on that width
                 gen = [field.name for field in reg.fields]
                 longest = max(gen, key=len)
                 p += utf8tolatex(longest)
@@ -156,7 +156,7 @@ tex_table_top = r"""\begin{table}[h!]
     \label{tab:table1}
     \begin{tabularx}{\linewidth}{|l|X|l|l|l|c|l|}
       \hline
-      \textbf{\#} & \textbf{Name} & \textbf{Mode} & \textbf{Address} & \textbf{Type} & \textbf{Length} &
+      \textbf{\#} & \textbf{Name} & \textbf{Mode} & \textbf{Address} & \textbf{Type} & \textbf{Width} &
       \textbf{Reset} \\
       \hline"""
 

{bust-0.13.2 → bust-0.14.0.dev0}/bust/editor.py

@@ -110,7 +110,7 @@ class Editor(object):
                     "Mode",
                     "Address",
                     "Type",
-                    "Length",
+                    "Width",
                     "Reset",
                     "Description",
                 ]
@@ -122,7 +122,7 @@ class Editor(object):
                             reg.mode,
                             hex(reg.address),
                             reg.sig_type,
-                            reg.length,
+                            reg.width,
                             reg.reset,
                             add_line_breaks(reg.description, 25),
                         ]
@@ -160,7 +160,7 @@ class Editor(object):
                 "Name",
                 "Type",
                 "Position",
-                "Length",
+                "Width",
                 "Reset",
                 "Description",
             ]
@@ -172,7 +172,7 @@ class Editor(object):
                         field.name,
                         field.sig_type,
                         field.get_pos_str(),
-                        field.length,
+                        field.width,
                         field.reset,
                         add_line_breaks(field.description, 25),
                     ]
@@ -213,8 +213,8 @@ class Editor(object):
                     if field_dic["type"] == "slv":
                         max_width = self.mod.data_width - width_consumed
 
-                        field_dic["length"] = get_int(
-                            "Field length: ",
+                        field_dic["width"] = get_int(
+                            "Field width: ",
                             10,
                             1,
                             max_width,
@@ -224,13 +224,13 @@ class Editor(object):
                             + " consumed by other fields: "
                             + str(max_width),
                         )
-                        width_consumed += field_dic["length"]
+                        width_consumed += field_dic["width"]
 
                     else:
                         width_consumed += 1
-                        field_dic["length"] = 1
+                        field_dic["width"] = 1
 
-                    max_reset = 2 ** field_dic["length"] - 1
+                    max_reset = 2 ** field_dic["width"] - 1
                     field_dic["reset"] = hex(
                         get_int(
                             "Field reset in hex (default=0x0): ",
@@ -272,19 +272,19 @@ class Editor(object):
                     "Register type: ", Register.supported_types, None, 0
                 )
 
-            # Make sure reg length is set to help calculate max reset later
+            # Make sure reg width is set to help calculate max reset later
             # Registers of field type will get an auto reset based on the field resets
             if reg["type"] == "default":
-                reg["length"] = self.mod.data_width
+                reg["width"] = self.mod.data_width
             elif reg["type"] == "sl":
-                reg["length"] = 1
+                reg["width"] = 1
             elif reg["type"] == "slv":
                 while True:
                     try:
-                        reg["length"] = int(input("Length: "))
+                        reg["width"] = int(input("Width: "))
                         break
                     except Exception:
-                        print("That is not a valid length...")
+                        print("That is not a valid width...")
 
             if input("Auto-assign address? (Y/n): ").upper() == "N":
                 # Make sure the address is not out of range and that it is free
@@ -325,7 +325,7 @@ class Editor(object):
 
             if reg["type"] != "fields":
 
-                max_reset = 2 ** reg["length"] - 1
+                max_reset = 2 ** reg["width"] - 1
                 reg["reset"] = hex(
                     get_int(
                         "Register reset in hex (default=0x0): ",
@@ -347,7 +347,7 @@ class Editor(object):
                 "Mode",
                 "Address",
                 "Type",
-                "Length",
+                "Width",
                 "Reset",
                 "Description",
             ]
@@ -364,11 +364,11 @@ class Editor(object):
             table_type = reg["type"]
 
             if reg["type"] == "fields":
-                table_length = "auto"
-            elif "length" in reg:
-                table_length = reg["length"]
+                table_width = "auto"
+            elif "width" in reg:
+                table_width = reg["width"]
             else:
-                table_length = self.mod.bus.data_width
+                table_width = self.mod.bus.data_width
 
             if reg["type"] == "fields":
                 table_reset = "auto"
@@ -386,7 +386,7 @@ class Editor(object):
                     table_mode,
                     table_address,
                     table_type,
-                    table_length,
+                    table_width,
                     table_reset,
                     table_description,
                 ]
@@ -401,7 +401,7 @@ class Editor(object):
                     "#",
                     "Name",
                     "Type",
-                    "Length",
+                    "Width",
                     "Reset",
                     "Description",
                 ]
@@ -412,7 +412,7 @@ class Editor(object):
                             i,
                             field["name"],
                             field["type"],
-                            field["length"],
+                            field["width"],
                             field["reset"],
                             field["description"],
                         ]

{bust-0.13.2 → bust-0.14.0.dev0}/bust/exceptions.py

@@ -57,12 +57,12 @@ class InvalidResetMode(RuntimeError):
 class ModuleDataBitsExceeded(Exception):
     """! @brief Raised when the specified module data bits are exceeded."""
 
-    def __init__(self, register, reglength, mod_data_length):
-        msg = "Register length exceeded module data length by "
-        msg += str(reglength - mod_data_length)
+    def __init__(self, register, regwidth, mod_data_width):
+        msg = "Register width exceeded module data width by "
+        msg += str(regwidth - mod_data_width)
         msg += " in register " + register + "\n"
-        msg += "Module length: " + str(mod_data_length) + "\n"
-        msg += "Register length: " + str(reglength)
+        msg += "Module width: " + str(mod_data_width) + "\n"
+        msg += "Register width: " + str(regwidth)
 
         super().__init__(msg)
 

{bust-0.13.2 → bust-0.14.0.dev0}/bust/field.py

@@ -8,15 +8,15 @@ class Field(object):
 
     supported_types = ["slv", "sl"]
 
-    def __init__(self, name, sig_type, length, reset, description, pos_low):
+    def __init__(self, name, sig_type, width, reset, description, pos_low):
         self.name = name
         self.sig_type = sig_type
-        self.length = length
+        self.width = width
         self.reset = reset
         self.description = description
         self.description_with_breaks = add_line_breaks(description, 25)
         self.pos_low = pos_low
-        self.pos_high = pos_low + length - 1
+        self.pos_high = pos_low + width - 1
 
     def get_pos_str(self):
         if self.sig_type == "sl":
@@ -31,13 +31,13 @@ class Field(object):
             return str(self.pos_high) + " downto " + str(self.pos_low)
 
     def get_mask(self):
-        return pow(2, self.length) - 1 << self.pos_low
+        return pow(2, self.width) - 1 << self.pos_low
 
     def get_dictionary(self, reset, description):
         dict = OrderedDict()
         dict["name"] = self.name
         dict["type"] = self.sig_type
-        dict["length"] = self.length
+        dict["width"] = self.width
         if reset:
             dict["reset"] = self.reset
         if description:
@@ -50,7 +50,7 @@ class Field(object):
             self.name,
             self.sig_type,
             self.get_pos_str,
-            self.length,
+            self.width,
             self.reset,
             self.description,
         ]
@@ -61,7 +61,7 @@ class Field(object):
         dic["name"] = self.name
         dic["type"] = self.sig_type
         if self.sig_type == "slv":
-            dic["length"] = self.length
+            dic["width"] = self.width
         if self.reset != "0x0":
             dic["reset"] = self.reset
         if self.description != "":

{bust-0.13.2 → bust-0.14.0.dev0}/bust/header.py

@@ -17,14 +17,10 @@ class Header(object):
 
         for reg in self.module.registers:
             s += "/* Register: " + reg.name + " */\n"
-            s += (
-                "#define "
-                + reg.name.upper()
-                + "_OFFSET "
-                + str(hex(reg.address))
-                + "\n"
-            )
-            s += "#define " + reg.name.upper() + "_RESET " + reg.reset + "\n"
+            s += f'#define {reg.name.upper()}_MODE "{reg.mode}";\n'
+            s += f"#define {reg.name.upper()}_WIDTH {reg.width};\n"
+            s += f"#define {reg.name.upper()}_OFFSET {str(hex(reg.address))};\n"
+            s += f"#define {reg.name.upper()}_RESET {reg.reset};\n"
             s += "\n"
 
             if reg.sig_type == "fields":
@@ -45,7 +41,7 @@ class Header(object):
                         + field.name.upper()
                         + "_WIDTH "
                     )
-                    s += str(field.length) + "\n"
+                    s += str(field.width) + "\n"
                     s += (
                         "#define "
                         + reg.name.upper()
@@ -61,7 +57,7 @@ class Header(object):
                         + field.name.upper()
                         + "_MASK "
                     )
-                    s += str(hex(pow(2, field.length) - 1 << field.pos_low)) + "\n"
+                    s += str(hex(pow(2, field.width) - 1 << field.pos_low)) + "\n"
                     s += "\n"
 
         s += "#endif"
@@ -83,14 +79,12 @@ class Header(object):
 
         for reg in self.module.registers:
             s += "/* Register: " + reg.name + " */\n"
+            s += f'const uint32_t {reg.name.upper()}_MODE = "{reg.mode}";\n'
+            s += f"const uint32_t {reg.name.upper()}_WIDTH = {reg.width};\n"
             s += (
-                "const uint32_t "
-                + reg.name.upper()
-                + "_OFFSET = "
-                + str(hex(reg.address))
-                + ";\n"
+                f"const uint32_t {reg.name.upper()}_OFFSET = {str(hex(reg.address))};\n"
             )
-            s += "const uint32_t " + reg.name.upper() + "_RESET = " + reg.reset + ";\n"
+            s += f"const uint32_t {reg.name.upper()}_RESET = {reg.reset};\n"
             s += "\n"
 
             if reg.sig_type == "fields":
@@ -111,7 +105,7 @@ class Header(object):
                         + field.name.upper()
                         + "_WIDTH = "
                     )
-                    s += str(field.length) + ";\n"
+                    s += str(field.width) + ";\n"
                     s += (
                         "const uint32_t "
                         + reg.name.upper()
@@ -127,7 +121,7 @@ class Header(object):
                         + field.name.upper()
                         + "_MASK = "
                     )
-                    s += str(hex(pow(2, field.length) - 1 << field.pos_low)) + ";\n"
+                    s += str(hex(pow(2, field.width) - 1 << field.pos_low)) + ";\n"
                     s += "\n"
         s += "};\n\n"
 
@@ -144,10 +138,12 @@ class Header(object):
         for reg in self.module.registers:
             s += "\n"
             s += indent_string('"""Register: ' + reg.name + '"""\n', 2)
+            s += indent_string(f'{reg.name.upper()}_MODE = "{reg.mode}"\n', 2)
+            s += indent_string(f"{reg.name.upper()}_WIDTH = {reg.width}\n", 2)
             s += indent_string(
-                reg.name.upper() + "_OFFSET = " + str(hex(reg.address)) + "\n", 2
+                f"{reg.name.upper()}_OFFSET = {str(hex(reg.address))}\n", 2
             )
-            s += indent_string(reg.name.upper() + "_RESET = " + reg.reset + "\n", 2)
+            s += indent_string(f"{reg.name.upper()}_RESET = {reg.reset}\n", 2)
 
             if reg.sig_type == "fields":
                 for field in reg.fields:
@@ -160,7 +156,7 @@ class Header(object):
                     s += indent_string(
                         reg.name.upper() + "_" + field.name.upper() + "_WIDTH = ", 2
                     )
-                    s += str(field.length) + "\n"
+                    s += str(field.width) + "\n"
                     s += indent_string(
                         reg.name.upper() + "_" + field.name.upper() + "_RESET = ", 2
                     )
@@ -168,7 +164,7 @@ class Header(object):
                     s += indent_string(
                         reg.name.upper() + "_" + field.name.upper() + "_MASK = ", 2
                     )
-                    s += str(hex(pow(2, field.length) - 1 << field.pos_low))
+                    s += str(hex(pow(2, field.width) - 1 << field.pos_low))
                     s += "\n"
 
         return s

{bust-0.13.2 → bust-0.14.0.dev0}/bust/module.py

@@ -216,7 +216,7 @@ class Module:
                 and reg.sig_type != "fields"
                 and reg.sig_type != "sl"
             ):
-                reg_dic["length"] = reg.length
+                reg_dic["width"] = reg.width
 
             if reg.sig_type != "fields":
                 reg_dic["reset"] = reg.reset

{bust-0.13.2 → bust-0.14.0.dev0}/bust/module_vhdl_gen.py

@@ -65,11 +65,11 @@ class ModuleVHDLGen:
             if reg.mode == "pulse":
                 s += indent_string(reg.name, 2) + " : "
                 if reg.sig_type == "default" or (
-                    reg.sig_type == "slv" and reg.length == self.data_width
+                    reg.sig_type == "slv" and reg.width == self.data_width
                 ):
                     s += "t_" + self.name + "_data;\n"
                 elif reg.sig_type == "slv":
-                    s += "std_logic_vector(" + str(reg.length - 1) + " downto 0);\n"
+                    s += "std_logic_vector(" + str(reg.width - 1) + " downto 0);\n"
                 elif reg.sig_type == "sl":
                     s += "std_logic;\n"
                 elif reg.sig_type == "fields":
@@ -97,7 +97,7 @@ class ModuleVHDLGen:
                 for field in reg.fields:
                     s += indent_string(field.name, 2) + " : "
                     if field.sig_type == "slv":
-                        s += "std_logic_vector(" + str(field.length - 1)
+                        s += "std_logic_vector(" + str(field.width - 1)
                         s += " downto 0);\n"
                     elif field.sig_type == "sl":
                         s += "std_logic;\n"
@@ -110,11 +110,11 @@ class ModuleVHDLGen:
             if reg.mode == "ro":
                 s += indent_string(reg.name, 2) + " : "
                 if reg.sig_type == "default" or (
-                    reg.sig_type == "slv" and reg.length == self.data_width
+                    reg.sig_type == "slv" and reg.width == self.data_width
                 ):
                     s += "t_" + self.name + "_data;\n"
                 elif reg.sig_type == "slv":
-                    s += "std_logic_vector(" + str(reg.length - 1) + " downto 0);\n"
+                    s += "std_logic_vector(" + str(reg.width - 1) + " downto 0);\n"
                 elif reg.sig_type == "sl":
                     s += "std_logic;\n"
                 elif reg.sig_type == "fields":
@@ -150,7 +150,7 @@ class ModuleVHDLGen:
                 if field.reset == "0x0":
                     par += "(others => '0')"
                 else:
-                    par += str(field.length) + 'X"'
+                    par += str(field.width) + 'X"'
                     par += format(int(field.reset, 16), "X") + '"'
 
             elif field.sig_type == "sl":
@@ -173,11 +173,11 @@ class ModuleVHDLGen:
             if reg.mode == "rw":
                 s += indent_string(reg.name, 2) + " : "
                 if reg.sig_type == "default" or (
-                    reg.sig_type == "slv" and reg.length == self.data_width
+                    reg.sig_type == "slv" and reg.width == self.data_width
                 ):
                     s += "t_" + self.name + "_data;\n"
                 elif reg.sig_type == "slv":
-                    s += "std_logic_vector(" + str(reg.length - 1) + " downto 0);\n"
+                    s += "std_logic_vector(" + str(reg.width - 1) + " downto 0);\n"
                 elif reg.sig_type == "sl":
                     s += "std_logic;\n"
                 elif reg.sig_type == "fields":
@@ -205,7 +205,7 @@ class ModuleVHDLGen:
                 if reg.reset == "0x0":
                     par += "(others => '0')"
                 else:
-                    par += str(reg.length) + 'X"'
+                    par += str(reg.width) + 'X"'
                     par += format(int(reg.reset, 16), "X") + '"'
 
             elif reg.sig_type == "fields":
@@ -231,7 +231,7 @@ class ModuleVHDLGen:
         for field in reg.fields:
             s += indent_string(field.name, 2) + " : "
             if field.sig_type == "slv":
-                s += "std_logic_vector(" + str(field.length - 1)
+                s += "std_logic_vector(" + str(field.width - 1)
                 s += " downto 0);\n"
             elif field.sig_type == "sl":
                 s += "std_logic;\n"

{bust-0.13.2 → bust-0.14.0.dev0}/bust/register.py

@@ -17,7 +17,7 @@ class Register:
     supported_types = ["default", "slv", "sl"]
     supported_modes = ["RW", "RO", "PULSE"]
 
-    def __init__(self, reg, address, mod_data_length):
+    def __init__(self, reg, address, mod_data_width):
         self.name = reg["name"]
         self.mode = reg["mode"].lower()
         self.description = reg["description"]
@@ -39,32 +39,32 @@ class Register:
             self.stall_cycles = reg["stall_cycles"]
 
         self.reset = "0x0"
-        self.length = 0
+        self.width = 0
         self.fields = []
 
-        if "length" in reg:
-            tmp_length = reg["length"]
+        if "width" in reg:
+            tmp_width = reg["width"]
         else:
-            tmp_length = 1  # Setting to 1, in case std_logic
+            tmp_width = 1  # Setting to 1, in case std_logic
 
         if "type" in reg:
             self.sig_type = reg["type"]
         else:
             self.sig_type = "fields"
 
-        # Assign the reg type and register data length
+        # Assign the reg type and register data width
         if self.sig_type == "default":
-            self.length = mod_data_length
+            self.width = mod_data_width
 
         elif self.sig_type == "slv":
-            self.length = tmp_length
+            self.width = tmp_width
 
         elif self.sig_type == "sl":
             self.sig_type = "sl"
 
-            if tmp_length != 1:
-                raise UndefinedRegisterType("SL cannot have length other than 1")
-            self.length = tmp_length
+            if tmp_width != 1:
+                raise UndefinedRegisterType("SL cannot have width other than 1")
+            self.width = tmp_width
 
         elif self.sig_type == "fields" or "fields" in reg:
             if len(reg["fields"]) > 0:
@@ -83,9 +83,9 @@ class Register:
                     "Reset value is not allowed for record type register: " + self.name
                 )
             else:
-                # Check whether reset value matches register length
-                # maxvalue is given by 2^length
-                maxvalue = (2**self.length) - 1
+                # Check whether reset value matches register width
+                # maxvalue is given by 2^width
+                maxvalue = (2**self.width) - 1
                 if maxvalue < int(reg["reset"], 16):
                     raise InvalidRegisterFormat(
                         "Reset value does not match register: " + self.name
@@ -94,14 +94,14 @@ class Register:
                     self.reset = reg["reset"]
 
         # Perform check that data bits are not exceeded
-        self.check_register_data_length(mod_data_length)
+        self.check_register_data_width(mod_data_width)
 
     def __str__(self):
         string = "Name: " + self.name + "\n"
         string += "Address: " + hex(self.address) + "\n"
         string += "Mode: " + self.mode + "\n"
         string += "Type: " + self.sig_type + "\n"
-        string += "Length: " + str(self.length) + "\n"
+        string += "Width: " + str(self.width) + "\n"
         string += "Reset: " + self.reset
         if self.sig_type == "record":
 
@@ -112,8 +112,8 @@ class Register:
                     + i["name"]
                     + " Type: "
                     + i["type"]
-                    + " Length: "
-                    + str(i["length"])
+                    + " Width: "
+                    + str(i["width"])
                     + " Reset: "
                     + i["reset"]
                 )
@@ -134,24 +134,24 @@ class Register:
         is_unique(field["name"], field_names)
 
         if field["type"] == "slv":
-            if "length" not in field:
+            if "width" not in field:
                 raise InvalidFieldFormat(self.name)
-            length = field["length"]
+            width = field["width"]
 
         elif field["type"] == "sl":
-            length = 1
+            width = 1
 
         else:
             raise UndefinedFieldType(field["type"])
 
-        # Increment register length
-        self.length += length
+        # Increment register width
+        self.width += width
 
         if "reset" in field:
             reset = field["reset"]
-            # Check whether reset value matches field length
-            # maxvalue is given by 2^length
-            maxvalue = (2**length) - 1
+            # Check whether reset value matches field width
+            # maxvalue is given by 2^width
+            maxvalue = (2**width) - 1
             if maxvalue < int(field["reset"], 16):
                 raise InvalidFieldFormat(
                     "Reset value does not match field: "
@@ -169,7 +169,7 @@ class Register:
 
         next_low = self.get_next_pos_low()
         self.fields.append(
-            Field(field["name"], field["type"], length, reset, description, next_low)
+            Field(field["name"], field["type"], width, reset, description, next_low)
         )
 
         # Maintain the register reset value
@@ -178,13 +178,13 @@ class Register:
         reg_reset_int += field_reset_int << next_low
         self.reset = hex(reg_reset_int)
 
-    def check_register_data_length(self, module):
+    def check_register_data_width(self, module):
         """! @brief Controls that the combined data bits in fields does not
         exceed data bits of module
 
         """
-        if self.length > module:
-            raise ModuleDataBitsExceeded(self.name, self.length, module)
+        if self.width > module:
+            raise ModuleDataBitsExceeded(self.name, self.width, module)
 
     def get_next_pos_low(self):
         if len(self.fields) > 0:

{bust-0.13.2 → bust-0.14.0.dev0}/bust/testbench.py

@@ -397,7 +397,7 @@ class Testbench(object):
         signal = "{}_{}_regs.{}".format(self.bus.short_name, reg.mode, reg.name)
         if reg.sig_type in ["sl", "slv", "default"]:
             s += self.check_value(
-                signal, self.sig_value(reg.reset, reg.sig_type, reg.length), msg
+                signal, self.sig_value(reg.reset, reg.sig_type, reg.width), msg
             )
         elif reg.sig_type == "fields":
             for field in reg.fields:
@@ -405,13 +405,13 @@ class Testbench(object):
                 signal_field = "{}.{}".format(signal, field.name)
                 s += self.check_value(
                     signal_field,
-                    self.sig_value(field.reset, field.sig_type, field.length),
+                    self.sig_value(field.reset, field.sig_type, field.width),
                     msg_field,
                 )
 
         if reg.mode in ["rw", "ro"]:
             c_addr = "C_ADDR_{}".format(reg.name.upper())
-            exp_value = self.sig_value(reg.reset, "default", reg.length)
+            exp_value = self.sig_value(reg.reset, "default", reg.width)
             s += self.bus.uvvm_check(c_addr, exp_value, msg)
         elif reg.mode == "pulse":
             pass
@@ -430,14 +430,14 @@ class Testbench(object):
             s += self.bus.uvvm_write(c_addr, bus_val, msg)
 
             if reg.sig_type in ["sl", "slv", "default"]:
-                sig_val = self.sig_value("0", reg.sig_type, reg.length)
+                sig_val = self.sig_value("0", reg.sig_type, reg.width)
                 s += self.check_value(signal, sig_val, msg)
             elif reg.sig_type == "fields":
                 for field in reg.fields:
                     signal_field = "{}.{}".format(signal, field.name)
                     s += self.check_value(
                         signal_field,
-                        self.sig_value("0", field.sig_type, field.length),
+                        self.sig_value("0", field.sig_type, field.width),
                         msg,
                     )
             else:
@@ -448,7 +448,7 @@ class Testbench(object):
         elif reg.mode == "ro":
 
             if reg.sig_type in ["sl", "slv", "default"]:
-                sig_val = self.sig_value("0", reg.sig_type, reg.length)
+                sig_val = self.sig_value("0", reg.sig_type, reg.width)
                 s += "{} <= {};\n".format(signal, sig_val)
                 s += self.await_value(signal, sig_val, msg)
             elif reg.sig_type == "fields":
@@ -459,7 +459,7 @@ class Testbench(object):
                     )
                 for field in reg.fields:
                     signal_field = "{}.{}".format(signal, field.name)
-                    sig_val = self.sig_value("0", field.sig_type, field.length)
+                    sig_val = self.sig_value("0", field.sig_type, field.width)
                     s += self.await_value(signal_field, sig_val, msg)
 
             else:
@@ -478,15 +478,15 @@ class Testbench(object):
                 for field in reg.fields:
                     signal_field.append("{}.{}".format(signal, field.name))
                 for i, field in enumerate(reg.fields):
-                    sig_val = self.sig_value("0", field.sig_type, field.length)
+                    sig_val = self.sig_value("0", field.sig_type, field.width)
                     s += self.check_value(signal_field[i], sig_val, msg)
                 for i, field in enumerate(reg.fields):
                     s += self.await_stable(signal_field[i], reg.pulse_cycles, msg)
                 for i, field in enumerate(reg.fields):
-                    sig_val = self.sig_value("0", field.sig_type, field.length)
+                    sig_val = self.sig_value("0", field.sig_type, field.width)
                     s += self.check_value(signal_field[i], sig_val, msg)
                 for i, field in enumerate(reg.fields):
-                    sig_val = self.sig_value(field.reset, field.sig_type, field.length)
+                    sig_val = self.sig_value(field.reset, field.sig_type, field.width)
                     s += self.await_value(signal_field[i], sig_val, msg)
 
             else:
@@ -495,12 +495,12 @@ class Testbench(object):
         return s
 
     def set_check_zero_pulse(self, signal, reg, msg):
-        sig_val = self.sig_value("0", reg.sig_type, reg.length)
+        sig_val = self.sig_value("0", reg.sig_type, reg.width)
         s = self.check_value(signal, sig_val, msg)
         s += self.await_stable(signal, reg.pulse_cycles, msg)
         s += self.check_value(signal, sig_val, msg)
         s += self.await_value(
-            signal, self.sig_value(reg.reset, reg.sig_type, reg.length), msg
+            signal, self.sig_value(reg.reset, reg.sig_type, reg.width), msg
         )
         return s
 
@@ -591,18 +591,18 @@ class Testbench(object):
         return s
 
     def check_bit_ro_slv(self, c_addr, signal, reg, msg, offset=0):
-        s = "for i in 0 to {} loop\n".format(reg.length - 1)
+        s = "for i in 0 to {} loop\n".format(reg.width - 1)
         if offset > 0:
             offset = "+{}".format(offset)
         else:
             offset = ""
-        sig_val = "std_logic_vector(to_unsigned(1, {}) sll i)".format(reg.length)
+        sig_val = "std_logic_vector(to_unsigned(1, {}) sll i)".format(reg.width)
         bus_val = "std_logic_vector(to_unsigned(1, data_width) sll i{})".format(offset)
         par = "{} <= {};\n".format(signal, sig_val)
         par += self.await_value(signal, sig_val, msg)
         par += self.bus.uvvm_check(c_addr, bus_val, msg)
         par += "-- Return to zero\n"
-        sig_val = self.sig_value("0", "slv", reg.length)
+        sig_val = self.sig_value("0", "slv", reg.width)
         bus_val = self.sig_value("0", "default")
         par += "{} <= {};\n".format(signal, sig_val)
         par += self.await_value(signal, sig_val, msg)
@@ -612,18 +612,18 @@ class Testbench(object):
         return s
 
     def check_bit_rw_slv(self, c_addr, signal, reg, msg, offset=0):
-        s = "for i in 0 to {} loop\n".format(reg.length - 1)
+        s = "for i in 0 to {} loop\n".format(reg.width - 1)
         if offset > 0:
             offset = "+{}".format(offset)
         else:
             offset = ""
-        sig_val = "std_logic_vector(to_unsigned(1, {}) sll i)".format(reg.length)
+        sig_val = "std_logic_vector(to_unsigned(1, {}) sll i)".format(reg.width)
         bus_val = "std_logic_vector(to_unsigned(1, data_width) sll i{})".format(offset)
         par = self.bus.uvvm_write(c_addr, bus_val, msg)
         par += self.check_value(signal, sig_val, msg)
         par += self.bus.uvvm_check(c_addr, bus_val, msg)
         par += "-- Return to zero\n"
-        sig_val = self.sig_value("0", "slv", reg.length)
+        sig_val = self.sig_value("0", "slv", reg.width)
         bus_val = self.sig_value("0", "default")
         par += self.bus.uvvm_write(c_addr, bus_val, msg)
         par += self.check_value(signal, sig_val, msg)
@@ -636,18 +636,18 @@ class Testbench(object):
         if clk_cycles is None:
             clk_cycles = reg.pulse_cycles
         reset = reg.reset
-        s = "for i in 0 to {} loop\n".format(reg.length - 1)
+        s = "for i in 0 to {} loop\n".format(reg.width - 1)
         if offset > 0:
             offset = "+{}".format(offset)
         else:
             offset = ""
-        sig_val = "std_logic_vector(to_unsigned(1, {}) sll i)".format(reg.length)
+        sig_val = "std_logic_vector(to_unsigned(1, {}) sll i)".format(reg.width)
         bus_val = "std_logic_vector(to_unsigned(1, data_width) sll i{})".format(offset)
         par = self.bus.uvvm_write(c_addr, bus_val, msg)
         par += self.check_value(signal, sig_val, msg)
         par += self.await_stable(signal, clk_cycles, msg)
         par += self.check_value(signal, sig_val, msg)
-        sig_val = self.sig_value(reset, reg.sig_type, reg.length)
+        sig_val = self.sig_value(reset, reg.sig_type, reg.width)
         par += self.await_value(signal, sig_val, msg)
         s += indent_string(par)
         s += "end loop;\n"
@@ -699,7 +699,7 @@ class Testbench(object):
         if reg.sig_type == "sl":
             reg_type = "std_logic"
         elif reg.sig_type in ["slv", "default"]:
-            reg_type = "{} bit std_logic_vector".format(reg.length)
+            reg_type = "{} bit std_logic_vector".format(reg.width)
         elif reg.sig_type == "fields":
             reg_type = "fields"
         par = "Checking Register {} - {} {}".format(

{bust-0.13.2 → bust-0.14.0.dev0}/bust.egg-info/PKG-INFO

@@ -1,6 +1,6 @@
 Metadata-Version: 2.1
 Name: bust
-Version: 0.13.2
+Version: 0.14.0.dev0
 Summary: Utility for simply creating and modifying VHDL bus slave modules
 Home-page: http://github.com/olagrottvik/bust
 Author: Ola Groettvik

{bust-0.13.2 → bust-0.14.0.dev0}/setup.py

@@ -26,7 +26,7 @@ class clean(Command):
 
 setup(
     name="bust",
-    version="0.13.2",
+    version="0.14.0-dev",
     packages=find_packages(),
     license="MIT",
     install_requires=[

{bust-0.13.2 → bust-0.14.0.dev0}/tests/test_suite.py

@@ -218,7 +218,7 @@ class Test_Suite(unittest.TestCase):
                 ) as f:
                     string = f.read()
                 self.assertEqual(
-                    holder.doc.return_tex_documentation("0.9.4"),
+                    holder.doc.return_tex_documentation("0.14.0-dev"),
                     string,
                     "doc must match manual file",
                 )

bust-0.13.2/bust/_version.py

@@ -1 +0,0 @@
-__VERSION__ = "0.13.2"