boardwright 0.1.0__tar.gz

boardwright-0.1.0/.gitignore

@@ -0,0 +1,19 @@
+__pycache__/
+.venv/
+dist/
+.pytest_cache/
+.ruff_cache/
+.libmerge/
+*.solve.kicad_pcb
+*.kicad_prl
+*.lck
+.history/
+*-backups/
+fp-info-cache
+**/out/
+**/boardwright_out/
+*.dsn
+*.ses
+*.rules
+preview.svg
+*_preview.png

boardwright-0.1.0/CHANGELOG.md

@@ -0,0 +1,41 @@
+# Changelog
+
+All notable changes to this project are recorded here. The format follows
+[Keep a Changelog](https://keepachangelog.com/en/1.1.0/), and versions follow
+[Semantic Versioning](https://semver.org/) (before 1.0, a minor version may change
+the command line).
+
+## [Unreleased]
+
+## [0.1.0] - 2026-11-14
+
+First public release.
+
+### Added
+
+- `boardwright place | gen | check | verify | pads` for boards described in a
+  `board.py`: schematic generation, placement (fixed or by pad intent with
+  `pad_at`), hand copper (`TRACKS`, `VIAS`, `ZONES`, `KEEPOUTS`, `TEXT`),
+  Freerouting with a bottom-layer cost and plane layers closed to it, a
+  pad-to-pad completion pass, pours, and a KiCad gate (ERC, DRC at every
+  severity with schematic parity, netlist, gerbers, drill, BOM, placement,
+  PDF, plots).
+- An engineering review beyond DRC (`REVIEW`): pad distances, net and path
+  lengths, pair matching with vias counted, reference-plane runs, ground vias
+  beside signal vias, pour coverage and continuity, current capacity per
+  IPC-2221.
+- `boardwright existing` for boards the tool did not make: inspection and
+  preview of any size of board, review, DRC compared with a baseline, in-place
+  edits (move, rip-up, routes by intent, hand copper), and re-routing of named
+  nets that leaves every other net byte-identical.
+- `boardwright sch` for schematics: list parts, set fields, remove parts, add
+  a part by copying one with the same symbol, across hierarchical sheets;
+  `ercdiff` for ERC reports.
+- `boardwright live` for the board open in KiCad 10 through its IPC API
+  (optional `[live]` extra), and `boardwright edits` / `selection` for plain
+  edit lists and KiCad's selection text.
+- `boardwright impedance` (IPC-2141 closed form) and `doctor`.
+- Seven example boards and specs for KiCad's own demo projects.
+
+[Unreleased]: https://github.com/heibench/boardwright/compare/v0.1.0...HEAD
+[0.1.0]: https://github.com/heibench/boardwright/releases/tag/v0.1.0

boardwright-0.1.0/LICENSE

@@ -0,0 +1,201 @@
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boardwright-0.1.0/PKG-INFO

@@ -0,0 +1,163 @@
+Metadata-Version: 2.5
+Name: boardwright
+Version: 0.1.0
+Summary: Generate and edit KiCad boards and schematics from a short Python description, checked by KiCad itself.
+Project-URL: Homepage, https://github.com/heibench/boardwright
+Project-URL: Issues, https://github.com/heibench/boardwright/issues
+Project-URL: Changelog, https://github.com/heibench/boardwright/blob/main/CHANGELOG.md
+Author: heibench
+License-Expression: Apache-2.0
+License-File: LICENSE
+Keywords: autorouter,eda,electronics,kicad,pcb,schematic
+Classifier: Development Status :: 3 - Alpha
+Classifier: Environment :: Console
+Classifier: Intended Audience :: Manufacturing
+Classifier: Intended Audience :: Science/Research
+Classifier: Operating System :: OS Independent
+Classifier: Programming Language :: Python :: 3
+Classifier: Programming Language :: Python :: 3.12
+Classifier: Programming Language :: Python :: 3.13
+Classifier: Programming Language :: Python :: 3.14
+Classifier: Topic :: Scientific/Engineering :: Electronic Design Automation (EDA)
+Requires-Python: >=3.12
+Requires-Dist: kicad-netspec==0.9.0
+Requires-Dist: kicad-tools==0.29.0
+Requires-Dist: numpy>=1.24
+Requires-Dist: shapely>=2.0
+Provides-Extra: live
+Requires-Dist: kicad-python==0.8.0; extra == 'live'
+Description-Content-Type: text/markdown
+
+# boardwright
+
+**Generate and edit KiCad boards and schematics from a short Python description,
+checked by KiCad itself.**
+
+> **Status: alpha.** It makes real, routed, DRC-clean KiCad 10 projects and edits
+> existing ones in place. None of the example boards has been fabricated. The
+> command line is the stable surface; the Python modules will move.
+
+```sh
+pip install boardwright             # add [live] to edit the board open in KiCad
+boardwright doctor                  # what this machine has for each step
+```
+
+Needs KiCad 10 (its libraries and `kicad-cli`) and [Freerouting](https://github.com/freerouting/freerouting)
+for autorouting. `boardwright doctor` finds them in the usual install places, Flatpak
+included, and names the setting to use when it cannot.
+
+![RP2040 board generated by boardwright](https://raw.githubusercontent.com/heibench/boardwright/main/docs/img/rp2040_min.png)
+
+## What it does
+
+A board is a directory with a `board.py`: the circuit, where the parts go, and what
+matters about the layout.
+
+```python
+from boardwright.circuit import Circuit
+
+NAME, W, H = "ldo_breakout", 30, 20
+CIRCUIT = c = Circuit("LDO breakout")
+c.add("J1", "Connector_Generic:Conn_01x02", "VIN", "Connector_PinHeader_2.54mm:PinHeader_1x02_P2.54mm_Vertical", {1: "VIN", 2: "GND"})
+c.add("U1", "Regulator_Linear:AMS1117-3.3", "AMS1117-3.3", "Package_TO_SOT_SMD:SOT-223-3_TabPin2", {1: "GND", 2: "+3V3", 3: "VIN"})
+c.add("C1", "Device:C", "10u", "Capacitor_SMD:C_0805_2012Metric", {1: "VIN", 2: "GND"})
+# ...
+PLACE = {"J1": (3, 8.7, 0), "C1": (8.5, 10, 90), "U1": (15, 10, 270)}
+REVIEW = {"near": [("C1.1", "U1.3", 6.0)]}      # input capacitor within 6 mm of the input pin
+```
+
+```sh
+boardwright place examples/boards/ldo_breakout    # placement + ratsnest preview, ~5 s, no KiCad
+boardwright gen examples/boards/ldo_breakout      # schematic, board, routing, pours
+boardwright check examples/boards/ldo_breakout    # KiCad: ERC, DRC + parity, netlist, gerbers, plots
+boardwright verify examples/boards/ldo_breakout   # PASS / NOT DONE
+```
+
+`verify` passes only when KiCad reports **zero** ERC and DRC findings at every
+severity, schematic parity included, KiCad's netlist equals the declared circuit,
+the fab files exist, and the engineering review is clean.
+
+The review exists because a zero DRC is not a good board. An autorouter will run a
+signal through a power polygon and leave the halves joined by a thin trace, and KiCad
+accepts it. `REVIEW` checks what a reviewer would: decoupler-to-pin distance,
+routed path lengths and pair matching (vias counted), how far a signal runs with no
+ground on the adjacent layer, ground vias beside signal vias, pour coverage and
+whether each pour is still one piece, and current capacity per IPC-2221.
+
+**Boards that already exist** are edited in place and nothing is regenerated:
+
+```sh
+boardwright existing MYPROJ info              # layers, nets, pours, preview; any size of board
+boardwright existing MYPROJ review            # the same review, against a spec beside the board
+boardwright existing MYPROJ apply             # MOVE, RIPUP, ROUTES, TRACKS, VIAS, ZONES from the spec
+boardwright existing MYPROJ reroute /SDA      # re-route named nets; every other net stays byte-identical
+boardwright existing MYPROJ verify            # review + no DRC finding that is not in the baseline
+boardwright sch MYPROJ set R12 Value=4k7      # one block of the schematic replaced, the rest untouched
+boardwright live apply edit.py                # the same edits to the board open in KiCad, one undo step
+```
+
+## How it decides
+
+- **KiCad is the judge.** Nothing is "done" on the tool's own arithmetic. Every
+  generated board goes through `kicad-cli`, and edits to existing designs are compared
+  against a baseline that KiCad produced. Connectivity before and after an edit is
+  checked with [netspec](https://github.com/heibench/netspec), which this project uses
+  to find KiCad.
+- **Placement and hand copper are yours; the rest is routed.** Power loops, USB pairs and
+  anything sensitive are drawn in `board.py` (`TRACKS`, `VIAS`, `ZONES`). Parts can be
+  placed by intent: `pad_at(1, ("U1", 24), dy=-1.7)` puts a capacitor's pad 1.7 mm from
+  pin 24. Freerouting does the remaining small signals, and a pad-to-pad router finishes
+  what it leaves open.
+- **Edits are plain data.** An edit to an existing board is an ordered list of
+  operations in the board's own coordinates, checked against the board before it runs,
+  so the same file can be applied to the file on disk or to KiCad's open board.
+
+## Examples
+
+`examples/boards/` has seven boards made with it; all but the library fixture follow a vendor
+reference design:
+
+| Board | Layers | What it exercises |
+|---|---|---|
+| `ldo_breakout` | 2 | the loop itself |
+| `rp2040_min` | 2 | 0.4 mm QFN, USB-C, crystal, QSPI flash |
+| `tps54202_buck` | 2 | a switching regulator's current loops, hand-routed power |
+| `stm32f103_min` | 2 | 0.5 mm LQFP-48, bottom-side decoupling, USB pair |
+| `esp32c3_min` | 2 | RF module with antenna keep-out, USB on the bottom layer |
+| `stm32f103_4l` | 4 | inner ground planes, return-path and via review |
+| `customlib_test` | 2 | parts from a library outside KiCad's stock set |
+
+`examples/existing/` has specs for demo projects that ship with KiCad, for trying the
+existing-board and schematic commands. [`docs/devlog/`](docs/devlog/) records what each
+board broke in the tool and what was changed.
+
+## Documentation
+
+- [`docs/guide.md`](docs/guide.md): the full workflow, every `board.py` option, existing
+  boards and schematics, the live KiCad client, and what the tool does badly.
+- [`docs/devlog/gaps.md`](docs/devlog/gaps.md): known limits.
+
+## Known limits
+
+- Freerouting is not repeatable on dense boards; the pad-to-pad router does not push
+  other tracks aside, tune lengths or route pairs as pairs.
+- Schematic editing changes fields, removes parts, and adds a part by copying one with
+  the same symbol. It cannot add a symbol the sheet does not already use, and a
+  schematic change is pushed to the board in KiCad.
+- Generated schematics are one flat sheet.
+- Impedance figures are closed-form (IPC-2141, about +-10 %); confirm with your fab.
+- KiCad 10 only. The live client uses KiCad's IPC API, which is what KiCad 11 builds on.
+
+## Development
+
+```sh
+just setup     # uv sync --all-extras
+just check     # ruff
+just test      # pytest; the full KiCad pipeline test skips where KiCad is absent
+```
+
+## License
+
+Apache-2.0. The example boards are generated from KiCad's libraries, whose licence
+(CC-BY-SA 4.0 with an exception for designs that use them) places no restriction on
+the boards.

boardwright-0.1.0/README.md

@@ -0,0 +1,133 @@
+# boardwright
+
+**Generate and edit KiCad boards and schematics from a short Python description,
+checked by KiCad itself.**
+
+> **Status: alpha.** It makes real, routed, DRC-clean KiCad 10 projects and edits
+> existing ones in place. None of the example boards has been fabricated. The
+> command line is the stable surface; the Python modules will move.
+
+```sh
+pip install boardwright             # add [live] to edit the board open in KiCad
+boardwright doctor                  # what this machine has for each step
+```
+
+Needs KiCad 10 (its libraries and `kicad-cli`) and [Freerouting](https://github.com/freerouting/freerouting)
+for autorouting. `boardwright doctor` finds them in the usual install places, Flatpak
+included, and names the setting to use when it cannot.
+
+![RP2040 board generated by boardwright](https://raw.githubusercontent.com/heibench/boardwright/main/docs/img/rp2040_min.png)
+
+## What it does
+
+A board is a directory with a `board.py`: the circuit, where the parts go, and what
+matters about the layout.
+
+```python
+from boardwright.circuit import Circuit
+
+NAME, W, H = "ldo_breakout", 30, 20
+CIRCUIT = c = Circuit("LDO breakout")
+c.add("J1", "Connector_Generic:Conn_01x02", "VIN", "Connector_PinHeader_2.54mm:PinHeader_1x02_P2.54mm_Vertical", {1: "VIN", 2: "GND"})
+c.add("U1", "Regulator_Linear:AMS1117-3.3", "AMS1117-3.3", "Package_TO_SOT_SMD:SOT-223-3_TabPin2", {1: "GND", 2: "+3V3", 3: "VIN"})
+c.add("C1", "Device:C", "10u", "Capacitor_SMD:C_0805_2012Metric", {1: "VIN", 2: "GND"})
+# ...
+PLACE = {"J1": (3, 8.7, 0), "C1": (8.5, 10, 90), "U1": (15, 10, 270)}
+REVIEW = {"near": [("C1.1", "U1.3", 6.0)]}      # input capacitor within 6 mm of the input pin
+```
+
+```sh
+boardwright place examples/boards/ldo_breakout    # placement + ratsnest preview, ~5 s, no KiCad
+boardwright gen examples/boards/ldo_breakout      # schematic, board, routing, pours
+boardwright check examples/boards/ldo_breakout    # KiCad: ERC, DRC + parity, netlist, gerbers, plots
+boardwright verify examples/boards/ldo_breakout   # PASS / NOT DONE
+```
+
+`verify` passes only when KiCad reports **zero** ERC and DRC findings at every
+severity, schematic parity included, KiCad's netlist equals the declared circuit,
+the fab files exist, and the engineering review is clean.
+
+The review exists because a zero DRC is not a good board. An autorouter will run a
+signal through a power polygon and leave the halves joined by a thin trace, and KiCad
+accepts it. `REVIEW` checks what a reviewer would: decoupler-to-pin distance,
+routed path lengths and pair matching (vias counted), how far a signal runs with no
+ground on the adjacent layer, ground vias beside signal vias, pour coverage and
+whether each pour is still one piece, and current capacity per IPC-2221.
+
+**Boards that already exist** are edited in place and nothing is regenerated:
+
+```sh
+boardwright existing MYPROJ info              # layers, nets, pours, preview; any size of board
+boardwright existing MYPROJ review            # the same review, against a spec beside the board
+boardwright existing MYPROJ apply             # MOVE, RIPUP, ROUTES, TRACKS, VIAS, ZONES from the spec
+boardwright existing MYPROJ reroute /SDA      # re-route named nets; every other net stays byte-identical
+boardwright existing MYPROJ verify            # review + no DRC finding that is not in the baseline
+boardwright sch MYPROJ set R12 Value=4k7      # one block of the schematic replaced, the rest untouched
+boardwright live apply edit.py                # the same edits to the board open in KiCad, one undo step
+```
+
+## How it decides
+
+- **KiCad is the judge.** Nothing is "done" on the tool's own arithmetic. Every
+  generated board goes through `kicad-cli`, and edits to existing designs are compared
+  against a baseline that KiCad produced. Connectivity before and after an edit is
+  checked with [netspec](https://github.com/heibench/netspec), which this project uses
+  to find KiCad.
+- **Placement and hand copper are yours; the rest is routed.** Power loops, USB pairs and
+  anything sensitive are drawn in `board.py` (`TRACKS`, `VIAS`, `ZONES`). Parts can be
+  placed by intent: `pad_at(1, ("U1", 24), dy=-1.7)` puts a capacitor's pad 1.7 mm from
+  pin 24. Freerouting does the remaining small signals, and a pad-to-pad router finishes
+  what it leaves open.
+- **Edits are plain data.** An edit to an existing board is an ordered list of
+  operations in the board's own coordinates, checked against the board before it runs,
+  so the same file can be applied to the file on disk or to KiCad's open board.
+
+## Examples
+
+`examples/boards/` has seven boards made with it; all but the library fixture follow a vendor
+reference design:
+
+| Board | Layers | What it exercises |
+|---|---|---|
+| `ldo_breakout` | 2 | the loop itself |
+| `rp2040_min` | 2 | 0.4 mm QFN, USB-C, crystal, QSPI flash |
+| `tps54202_buck` | 2 | a switching regulator's current loops, hand-routed power |
+| `stm32f103_min` | 2 | 0.5 mm LQFP-48, bottom-side decoupling, USB pair |
+| `esp32c3_min` | 2 | RF module with antenna keep-out, USB on the bottom layer |
+| `stm32f103_4l` | 4 | inner ground planes, return-path and via review |
+| `customlib_test` | 2 | parts from a library outside KiCad's stock set |
+
+`examples/existing/` has specs for demo projects that ship with KiCad, for trying the
+existing-board and schematic commands. [`docs/devlog/`](docs/devlog/) records what each
+board broke in the tool and what was changed.
+
+## Documentation
+
+- [`docs/guide.md`](docs/guide.md): the full workflow, every `board.py` option, existing
+  boards and schematics, the live KiCad client, and what the tool does badly.
+- [`docs/devlog/gaps.md`](docs/devlog/gaps.md): known limits.
+
+## Known limits
+
+- Freerouting is not repeatable on dense boards; the pad-to-pad router does not push
+  other tracks aside, tune lengths or route pairs as pairs.
+- Schematic editing changes fields, removes parts, and adds a part by copying one with
+  the same symbol. It cannot add a symbol the sheet does not already use, and a
+  schematic change is pushed to the board in KiCad.
+- Generated schematics are one flat sheet.
+- Impedance figures are closed-form (IPC-2141, about +-10 %); confirm with your fab.
+- KiCad 10 only. The live client uses KiCad's IPC API, which is what KiCad 11 builds on.
+
+## Development
+
+```sh
+just setup     # uv sync --all-extras
+just check     # ruff
+just test      # pytest; the full KiCad pipeline test skips where KiCad is absent
+```
+
+## License
+
+Apache-2.0. The example boards are generated from KiCad's libraries, whose licence
+(CC-BY-SA 4.0 with an exception for designs that use them) places no restriction on
+the boards.

boardwright-0.1.0/docs/devlog/README.md

@@ -0,0 +1,44 @@
+# Development log
+
+How the tool was built: each example board and each piece of existing-board
+work, what broke, and what changed in the tool because of it. The entries were
+written as the work happened, before the project was named boardwright, so
+they use the paths and commands of the time (`boards/` is now
+`examples/boards/`, `dogfood/existing/` is `examples/existing/`,
+`boardwright build DIR STEP` is `boardwright STEP DIR`,
+`scripts/check.sh` is `boardwright check`, and netlist comparisons are now
+`netspec diff`).
+
+Every board built with this repo gets a numbered entry here. The point is to
+find where the process breaks on real reference designs and fix the tool, not
+the board. One file per board:
+
+- **Reference** -- the vendor document the circuit and layout rules come from,
+  and which values were read from it versus chosen here.
+- **Stresses** -- why this board was picked.
+- **What broke** -- in order, with the symptom as KiCad or the plot showed it.
+- **Tool changes** -- what changed in `boardwright/` because of it.
+- **Left open** -- what a real engineer would still fix or check.
+
+`gaps.md` is the running backlog of tool gaps, most painful first.
+
+| # | Board | Reference | Stresses | Gate |
+|---|-------|-----------|----------|------|
+| 01 | `ldo_breakout` | AMS1117 datasheet typical application | the loop itself | PASS |
+| 02 | `rp2040_min` | Raspberry Pi "Hardware design with RP2040" minimal design | 0.4 mm QFN, USB, crystal, QSPI | PASS (second pass) |
+| 03 | `tps54202_buck` | TI TPS54202 datasheet (SLVSD26C) Fig. 7-1 and layout 7.4 | power polygons, hand routing, current loops | PASS |
+| 04 | `stm32f103_min` | ST AN2586 and STM32F103x8 datasheet | 0.5 mm LQFP-48, bottom decoupling, crystal, USB pair | PASS |
+| 05 | `esp32c3_min` | Espressif ESP32-C3 hardware design guidelines | RF module, antenna keep-out, USB pair on the bottom | PASS |
+| 06 | `stm32f103_4l` | as 04, on signal / GND / GND / signal | four layers, inner planes, return path, placement by intent | PASS |
+| 07 | `existing/stickhub` | a KiCad demo project nobody here drew | an existing board: read, review, edit in place, selective re-route | PASS vs baseline |
+| 08 | `customlib_test` | none (fixture) | parts from a library outside KiCad's stock set | PASS |
+| 09 | `existing/schtest` | the StickHub demo's schematic | an existing schematic: change a value, add two parts | netlist diff is exactly the edit |
+| 10 | `existing/hier` and two read-only demos | KiCad's hierarchical, 6-layer and 9-layer demos | shared sub-sheets, routing with vias and inner layers, per-net rules | see entry |
+
+"Gate PASS" means: ERC 0, DRC 0 at every severity with schematic parity,
+KiCad's netlist equals the declared circuit, the `REVIEW` checks pass, fab
+files exported. It does not mean built or powered.
+
+All five were regenerated and gated with the tool as it stands at the last
+entry. Bottom GND pour coverage (share of board area): 01 92%, 02 78% in
+five pieces, 03 94%, 04 77%, 05 68%.

boardwright-0.1.0/examples/existing/README.md

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+# Existing-board examples
+
+Specs for working on boards boardwright did not make. The boards themselves
+are demo projects that ship with KiCad, under their own licences, so they are
+not copied here: copy each demo folder from your KiCad install next to the
+spec.
+
+KiCad keeps its demos in `share/kicad/demos/`:
+
+| System | Folder |
+|---|---|
+| Linux package | `/usr/share/kicad/demos/` |
+| Linux Flatpak | `/var/lib/flatpak/app/org.kicad.KiCad/current/active/files/share/kicad/demos/` |
+| macOS | `/Applications/KiCad/KiCad.app/Contents/SharedSupport/demos/` |
+| Windows | `C:\Program Files\KiCad\<version>\share\kicad\demos\` |
+
+| Here | KiCad demo | What the spec does |
+|---|---|---|
+| `stickhub/` | `stickhub` | `boardwright.py`: a `REVIEW` for the USB hub (pair matching, decoupling); `live_demo.py`: a harmless first edit (one ground via and track) for `boardwright live apply` |
+| `stickhub_schematic/` | `stickhub` | `add_demo.py`: add two parts to the existing schematic with `boardwright sch DIR add` |
+| `complex_hierarchy/` | `complex_hierarchy` | `add_demo.py`: add a part on the root sheet of a hierarchical schematic |
+
+For example:
+
+```sh
+cp -r /usr/share/kicad/demos/stickhub/* examples/existing/stickhub/
+boardwright existing examples/existing/stickhub info
+boardwright existing examples/existing/stickhub review
+```
+
+Then follow "First contact with a board you did not make" in
+[`docs/guide.md`](../../docs/guide.md).

boardwright-0.1.0/examples/libs/customlib/README.md

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+# Test library for `LIBS`
+
+A stand-in for a private part library: one symbol (`Custom:MYLDO-3.3`) and one
+footprint (`Custom:MY_SOT-23-5`), copied from KiCad's stock AP2112K-3.3 and
+SOT-23-5 and renamed, so nothing here exists under that name in the stock
+libraries. `boards/customlib_test` builds against it.