bayerlink-fpga 0.3.0__tar.gz

bayerlink_fpga-0.3.0/.github/workflows/ci.yml

@@ -0,0 +1,149 @@
+name: CI
+
+on:
+  push:
+    branches: [main]
+  pull_request:
+  workflow_dispatch:
+
+jobs:
+  test:
+    runs-on: ubuntu-24.04
+    strategy:
+      fail-fast: false
+      matrix:
+        python-version: ["3.11", "3.12", "3.13", "3.14"]
+    steps:
+      - uses: actions/checkout@v4
+      - uses: actions/setup-python@v5
+        with:
+          python-version: ${{ matrix.python-version }}
+      - name: Install iverilog
+        run: sudo apt-get update && sudo apt-get install -y iverilog
+      - name: Install Verilator
+        run: |
+          curl -fsSL -o /tmp/oss-cad.tgz \
+            https://github.com/YosysHQ/oss-cad-suite-build/releases/download/2026-08-08/oss-cad-suite-linux-x64-20260808.tgz
+          tar -xzf /tmp/oss-cad.tgz -C /opt
+          echo "/opt/oss-cad-suite/bin" >> "$GITHUB_PATH"
+          /opt/oss-cad-suite/bin/verilator --version
+      - run: |
+          python -m pip install --upgrade pip
+          pip install -e . pytest
+      - name: Every source file states this repository's licence
+        run: python scripts/checklicence.py
+      - name: Dependency licences are permissive
+        # An ALLOW-LIST, checked against the resolved environment. A deny-list
+        # only catches the licences somebody thought to name; the one that
+        # causes trouble is the one nobody anticipated, and an allow-list
+        # catches that by construction.
+        #
+        # A new dependency under an unlisted licence fails here. If the licence
+        # is genuinely permissive, add it to PERMITTED with a one-line reason.
+        # The full dependency audit lives in revela's docs/THIRD-PARTY.md,
+        # which covers this package transitively.
+        run: |
+          python - <<'PY'
+          import re, sys
+          from importlib.metadata import distributions
+
+          PERMITTED = {
+              "MIT", "MIT-0", "BSD-2-Clause", "BSD-3-Clause", "0BSD",
+              "Apache-2.0", "PSF-2.0", "ISC", "Zlib", "CC0-1.0", "HPND",
+              "Python-2.0", "Unlicense", "MPL-2.0",
+              "Apache-2.0 WITH SHL-2.1",       # bayerlink-fpga itself
+          }
+          # MPL-2.0 is permitted only where it appears: a build-time transitive
+          # of the build backend, never imported, never redistributed in the
+          # wheel.
+
+          def terms(expression):
+              """The identifiers an SPDX expression names.
+
+              Split on AND/OR only: `WITH` binds an exception to its licence
+              ("Apache-2.0 WITH SHL-2.1") and the pair is one identifier.
+              Every branch of an OR must be permitted, which is stricter than
+              SPDX requires and is the right way round for this check.
+              """
+              parts = re.split(r"\s+(?:AND|OR)\s+|[()]", expression)
+              return {p.strip() for p in parts if p.strip()}
+
+          # Three metadata generations are in the wild at once, so all three are
+          # read: the PEP 639 `License-Expression`, the `License ::` trove
+          # classifiers, and the legacy free-text `License` field. A package
+          # that declares its licence only in the oldest form is not an
+          # undeclared package, and reporting it as one would train everyone to
+          # ignore this check.
+          LEGACY = {
+              "mit": "MIT", "mit license": "MIT", "expat": "MIT",
+              "bsd": "BSD-3-Clause", "bsd license": "BSD-3-Clause",
+              "bsd-3-clause": "BSD-3-Clause", "bsd 3-clause": "BSD-3-Clause",
+              "bsd-2-clause": "BSD-2-Clause", "apache-2.0": "Apache-2.0",
+              "apache 2.0": "Apache-2.0", "apache software license": "Apache-2.0",
+              "isc": "ISC", "psf-2.0": "PSF-2.0", "mpl-2.0": "MPL-2.0",
+          }
+          CLASSIFIER = {
+              "MIT License": "MIT", "MIT No Attribution License (MIT-0)": "MIT-0",
+              "BSD License": "BSD-3-Clause",
+              "Apache Software License": "Apache-2.0",
+              "Python Software Foundation License": "PSF-2.0",
+              "Mozilla Public License 2.0 (MPL 2.0)": "MPL-2.0",
+              "ISC License (ISCL)": "ISC", "The Unlicense (Unlicense)": "Unlicense",
+              "Zope Public License": None,
+          }
+
+          def declared(dist):
+              """(identifiers, how it was declared) for one distribution."""
+              expression = (dist.metadata.get("License-Expression") or "").strip()
+              if expression:
+                  return terms(expression), expression
+              classifiers = [c for c in dist.metadata.get_all("Classifier") or []
+                             if c.startswith("License ::")]
+              if classifiers:
+                  names = [c.rsplit(" :: ", 1)[-1] for c in classifiers]
+                  return ({CLASSIFIER.get(n, n) for n in names},
+                          "classifier: " + "; ".join(names))
+              legacy = (dist.metadata.get("License") or "").strip()
+              if legacy and "\n" not in legacy and len(legacy) < 60:
+                  return ({LEGACY.get(legacy.lower(), legacy)},
+                          f"legacy License field: {legacy}")
+              return set(), "no declared licence"
+
+          # setuptools 78/79 dropped its `License ::` classifiers, and its
+          # metadata predates `License-Expression`, so it declares its licence
+          # in none of the three places read above. It is MIT; it is a build
+          # tool, never imported and never redistributed in a wheel; and pip
+          # brings it whether or not anything asked. Named here rather than
+          # waved through: anything ELSE that declares nothing still fails.
+          UNDECLARED_UPSTREAM = {"setuptools": "MIT"}
+
+          problems, checked = [], 0
+          for dist in distributions():
+              name = dist.metadata["Name"]
+              if not name:
+                  continue
+              identifiers, how = declared(dist)
+              if not identifiers and name.lower() in UNDECLARED_UPSTREAM:
+                  identifiers = {UNDECLARED_UPSTREAM[name.lower()]}
+                  how = "known upstream packaging gap"
+              checked += 1
+              if not identifiers:
+                  problems.append(f"{name} {dist.version}: no declared licence")
+                  continue
+              unlisted = identifiers - PERMITTED
+              if unlisted:
+                  problems.append(f"{name} {dist.version}: {how} "
+                                  f"-> not permitted: {sorted(unlisted)}")
+
+          print(f"checked {checked} distributions against the allow-list")
+          if problems:
+              print("\nNOT PERMITTED:")
+              for p in problems:
+                  print("  " + p)
+              print("\nA dependency whose licence is not on the allow-list "
+                    "cannot be added without a decision.")
+              sys.exit(1)
+          print("every dependency licence is on the allow-list")
+          PY
+
+      - run: pytest -q

bayerlink_fpga-0.3.0/.github/workflows/publish.yml

@@ -0,0 +1,73 @@
+# Publish bayerlink-fpga to PyPI via Trusted Publishing (OIDC) -- no stored token.
+#
+# One-time setup on PyPI:
+#   https://pypi.org/manage/account/publishing/ -> add a pending publisher
+#     PyPI project name : bayerlink-fpga
+#     Owner             : bayerlink
+#     Repository        : bayerlink-fpga
+#     Workflow          : publish.yml
+#     Environment       : pypi
+# Then in this repository: Settings -> Environments -> create `pypi`,
+# with a required reviewer so an accidental tag cannot publish.
+#
+# To release: bump version in pyproject.toml, tag vX.Y.Z, publish a GitHub
+# Release from the tag.
+name: Publish
+
+on:
+  release:
+    types: [published]
+  workflow_dispatch:
+
+permissions:
+  contents: read
+
+jobs:
+  build:
+    runs-on: ubuntu-24.04
+    steps:
+      - uses: actions/checkout@v4
+      - uses: actions/setup-python@v5
+        with:
+          python-version: "3.12"
+      - name: Build and check
+        run: |
+          python -m pip install --upgrade pip build twine packaging
+          python -m build
+          twine check --strict dist/*
+      - name: Verify the tag matches the declared version
+        if: github.event_name == 'release'
+        run: |
+          python - <<'PY'
+          import os, pathlib, sys, tomllib
+          from packaging.version import Version
+          declared = tomllib.loads(
+              pathlib.Path("pyproject.toml").read_text())["project"]["version"]
+          tag = os.environ["GITHUB_REF_NAME"].lstrip("v")
+          if Version(declared) != Version(tag):
+              sys.exit(f"tag {tag!r} != pyproject version {declared!r}")
+          print("tag and version agree:", declared)
+          PY
+      - name: Install the wheel into a clean environment
+        run: |
+          python -m venv /tmp/clean
+          /tmp/clean/bin/pip install dist/*.whl
+          /tmp/clean/bin/python -c "import bayerlink_fpga.receiver, bayerlink_fpga.ddc; print('bayerlink_fpga imports')"
+      - uses: actions/upload-artifact@v4
+        with:
+          name: distributions
+          path: dist/
+
+  pypi:
+    needs: build
+    if: github.event_name == 'release'
+    runs-on: ubuntu-24.04
+    environment: pypi
+    permissions:
+      id-token: write
+    steps:
+      - uses: actions/download-artifact@v4
+        with:
+          name: distributions
+          path: dist/
+      - uses: pypa/gh-action-pypi-publish@release/v1

bayerlink_fpga-0.3.0/.gitignore

@@ -0,0 +1,32 @@
+# GENERATED, and so not source. Every number in these is read from the
+# file that owns it -- the board, the design, or the ISP's own published
+# contract -- and build.sh regenerates all of them before Vivado starts.
+# Committed, they would be a second copy of facts that already have
+# owners, going stale in silence the first time someone edits an owner
+# and does not rebuild. That disagreement does not surface as an error:
+# a width mismatch in a block design is a CRITICAL WARNING and a quiet
+# connection of the low bits.
+hdl/generated/
+boards/*/generated/
+board-files
+vivado-library
+build/
+out/
+*.jou
+*.log
+*.bit
+*.hwh
+.Xil/
+NA/
+# dvi2rgb writes its timing tables beside the board while it elaborates
+# and removes them again. They exist only during a build, which is
+# exactly when someone is most likely to stage everything.
+boards/*/dgl_*.data
+clockInfo.txt
+tight_setup_hold_pins.txt
+.DS_Store
+__pycache__/
+
+# Packaging
+dist/
+*.egg-info/

bayerlink_fpga-0.3.0/CHANGELOG.md

@@ -0,0 +1,235 @@
+# Changelog
+
+Notable changes to bayerlink-fpga — the bayerlink receiver on real
+silicon: the receiver and its TMDS front ends. (Through 0.2.1 it also
+carried the PYNQ-Z2 board design: a generated ISP and a display raster.)
+
+Up to 0.2.1 this repository published no package: a tag said which
+**generator versions** the recorded bitstream was built from, because the
+claim was reproducibility. From the next release it publishes
+`bayerlink-fpga`, the receiver's package, and the board design lives in
+revela.
+
+## 0.3.0
+
+**An HDMI receiver of our own, `tmds_rx`** (`hdl/tmds_rx.v`), as a
+second implementation of `frontends/hdmi_rx`: an MMCM at five times the
+link into BUFIO and BUFR, an IDELAYE2 and an ISERDESE2 pair a lane, and
+an alignment made for links that blank every line. Every delay tap of
+every bit slip is watched for tens of lines, for whether it sees blanks
+at all and how many control tokens it misreads; a lane samples at the
+middle of the taps that see blanks -- the walls of its eye, not its
+error-free taps, which sit off the middle -- at the least delay, so every
+lock lands on the same taps, and a mode change costs ~150 ms where
+dvi2rgb's 50 ms per tap cost seconds. The lanes are bonded where their
+blanking ends, held bonded through a stray misread token, and a line's
+data is what two of the three lanes say; `locked` is the clock locked and
+the lanes delivering, falling at once when the cable is pulled. What it
+saw is the block's optional account of the link, as named ports: the
+bond, each lane's alignment, eye and bit slip, and a survey of every
+lane's misread tokens at every tap of every slip, an entry at a time.
+Proven in simulation against a DVI source skewed by bits and whole
+words, with stray bit errors in its blanking, through a cable pull, at
+148.5, 74.25 and 27 MHz links (`tests/test_tmds_rx_sim.py`), and on the
+PYNQ-Z2 at 148.5 MHz: twenty locks bit-exact, and a 1080p30 camera's
+stream for minutes without a dropped lock.
+
+**The EDID's range limits are its link mode's.** The monitor range
+descriptor stated 29-31 Hz and 30-40 kHz whatever the build advertised;
+it is derived from the container's own timing now, a step either side,
+with its pixel clock as the ceiling.
+
+**The board design moved to revela; this repository became the receiver's
+package.** It keeps what any FPGA receiving bayerlink needs, and nothing
+that belongs to one design:
+
+- `bayerlink_fpga`, importable, in two layers: the receiver
+  (`receiver.py`, `ddc.py`, `hdl/`) and front ends (`frontends/hdmi_rx`).
+  The receiver and the DDC slave are leaves a design names --
+  `bayerlink_fpga.receiver:bayerlink_in`, `bayerlink_fpga.ddc:ddc_slave`
+  -- and its build sets them from the design's settings. Nothing in
+  it knows a board: a
+  board's pins and its front-end configuration live in that board's
+  library.
+- Front ends are one block, `frontends/hdmi_rx`, described once with its
+  implementations; a design names the block, and a parameter chooses the
+  implementation. The lane map moved from the board to the front end: it
+  is a fact of the dvi2rgb implementation, following that IP's bus
+  order, so any board receiving through dvi2rgb inherits it, and the
+  receiver's lanes are assigned from it.
+- The PYNQ-Z2 design -- block design, datapath, ISP pipeline, raster,
+  tee, bench scripts, clocking notes -- is `revela/boards/pynq_z2` in
+  revela, and builds there. Its generated Verilog is byte-identical to
+  this repository's 0.2.1 flow on the same generators.
+
+**The judge finds registers through the build's address map.** revela's
+design now has its own register bus, which Vivado cannot see through, so
+the `.hwh` no longer lists the slaves; `scripts/judge.py` reads
+`address_map.json`, written beside the bitstream, instead of PYNQ's
+`ip_dict`. Judged 4/4 on that build.
+
+**The receiver is this package's Verilog.** It was generated by np2hw,
+which is a generic library; it is `bayerlink_fpga/hdl/bayerlink_in.v` now,
+beside the protocol it implements -- its structure fixed, its capacity,
+output depth, lane order and vsync polarity parameters, which
+`bayerlink_fpga.receiver` works out from a design's settings and its
+front end. The protocol's fourcc table and magic are generated from the
+reference codec as `bayerlink_formats`, so the file restates none of
+them. `tests/` proves it bit-exact against that codec and holds its
+published ports to the file. The `python3 -m bayerlink_fpga` step and
+`frontend.tcl` are gone: what dvi2rgb needs beside a batch run -- its
+EDID data files -- a run copies for every IP that has them.
+
+**The receiver is a library a design composes.** `modules.json` describes
+each hand-written module as a block in revela's composite format, by its
+sources, parameters and every port it has; the generated ones publish
+their ports themselves. Each module's clock names the streams it drives
+and its reset, so a block design need not guess either.
+`judge.py` reads the GPIO fields by name from the `gpio_layout.json` built
+beside the bitstream, and refuses a layout whose checksum, built into the
+fabric, does not read back. `vid_probe`, whose word no design read, is
+retired.
+
+**The EDID reads bayerlink's rasters.** The advertised timing is the link
+mode's raster from `bayerlink.rasters`, the table the source reads too,
+rather than np2hw's; the bytes are unchanged.
+
+## 0.2.1
+
+Built with `np2hw==0.6.1`, `bayerlink==0.5.0`, `revela==0.2.0`.
+
+**The pinned install line resolves again.** 0.2.0 pinned `np2hw==0.6.0`,
+which was withdrawn from PyPI before it was announced; a burned version
+does not come back, so the documented `pip install` could not complete
+and the reproducible build this repository promises was not reproducible
+by anyone.
+
+The same generator ships as np2hw 0.6.1. **The pin moved and the design
+did not**: generating this pipeline under 0.6.0 and under 0.6.1 produces
+a byte-identical pack — Verilog, register map, SystemRDL, FuseSoC core
+and build manifest all compare equal. Between the two releases the only
+code that changed is `ipxact.py`, which emits IP-XACT XML rather than
+Verilog, plus one docstring. So the bitstream measured for 0.2.0 is the
+bitstream this pin builds; nothing about the board result below is
+restated on weaker evidence.
+
+## 0.2.0
+
+Built with `np2hw==0.6.0`, `bayerlink==0.5.0`, `revela==0.2.0`.
+
+Measured on the board: **WNS +0.134 ns MET, WHS +0.050 ns**, TNS and THS
+zero — more margin on both than 0.1.0 had. `rx.bit` and `rx.hwh`
+written, the as-built audit passes on seven addressable slaves, and no
+critical-warning class appears that an earlier build's log did not.
+
+**And it ran.** Loaded on the PYNQ-Z2, the bridge restored fifty
+registers over the display cable, the link locked and genlocked, and the
+board produced a correct 1920x1080 picture from a live sensor — the
+first tagged build here proven on glass in the same pass that built it.
+
+### Line buffers moved behind a module boundary
+
+np2hw 0.6.0 emits each line buffer as its own module rather than an
+inline array, so an integrator targeting silicon can bind a memory macro
+to it by name. On this board it is inert, and that is the point:
+**block RAM 23.5 tiles (22 x RAMB36 + 3 x RAMB18), identical to the tile
+against the previous build**, with LUTs and flip-flops within twenty of
+where they were. A claim about inference that hardware could refute, and
+did not.
+
+### The RTL says what its ports are
+
+Every AXI4-Lite port and every elastic-stream port now names the bus it
+belongs to, and the block design is given the bus definition that makes
+those names resolvable. `gen/netlist.py` reads those declarations
+instead of matching port names with a regex — the grouping is stated by
+the module that owns the ports rather than inferred by everything
+downstream — and refuses a module that carries a handshake while
+declaring nothing.
+
+The six hand-written board modules that speak the protocol declare it
+now. The emitted wiring is unchanged: `netlist.tcl` is byte-identical
+across the whole change.
+
+### The build says how much of the part it used
+
+`report_utilization` runs after routing and lands beside the bitstream.
+For its whole history this build reported whether it met timing and
+never once how full the device was, which is not a question that can be
+answered later.
+
+### Known gaps
+
+Unchanged from 0.1.0: nothing runs `sim/`, and the link-judge capture
+path is off by default.
+
+## 0.1.0 — first tagged build
+
+Built with `np2hw==0.5.1`, `bayerlink==0.5.0`, `revela==0.2.0`.
+
+Measured on the board: **WNS +0.047 ns MET, WHS +0.013 ns**, TNS and THS
+zero, `rx.bit` and `rx.hwh` written, and no critical-warning class absent
+from an earlier build's log.
+
+### The design
+
+- **Three of the four sources are generated and none is committed** — the
+  receiver, the ISP and the display raster all come from their models.
+  There is no hand-edited Verilog to drift, which is why a build that
+  skips a generator fails on a missing file rather than quietly using a
+  stale one.
+
+- **The ISP is a description.** `gen/pipeline.json` says what the
+  pipeline is, independent of any board; `revela` builds it and publishes
+  what it traced. The last scripted pipeline is gone.
+
+- **The block design's numbers are generated from the files that own
+  them.** It used to learn them three ways — environment variables, Tcl
+  defaults beside them, and constants in the script — which agreed until
+  the depth moved and then did not. What a disagreement produces here is
+  not an error but a picture, because Vivado answers a width mismatch
+  with a CRITICAL WARNING and a silent connection of the low bits.
+
+  Three owners now: `gen/pipeline.json` (the design), `board.json` (the
+  target) and `<name>_build.json` (what the ISP actually traced, which
+  nobody may restate). `bd.tcl` reads no environment and declares no
+  defaults.
+
+- **The datapath is described, not scripted.** `design.json` names the
+  blocks, their widths and their connections; `gen/netlist.py` emits the
+  Tcl and checks every width against the modules' own ports first. Every
+  instance declares its clock domain, and an undeclared crossing is
+  refused.
+
+- **Two clock territories**: the cable's, quarantined because it stops
+  when the cable is pulled, and the board's. Nothing addressable lives on
+  a clock that can stop — a slave with no clock never answers, AXI has no
+  timeout, and the first software access after that takes the processor
+  with it.
+
+- **Display placement is a register**, taken in vertical blanking behind
+  an arm/ack handshake, so a frame is drawn with one coherent set or the
+  previous one. A window that does not fit is refused rather than
+  clipped.
+
+- **A line wider than the pack was built for is cropped, not
+  reinterpreted** — visibly, with a sticky `truncated`. A narrower
+  picture can be recognised and tuned; a refused one is a black screen
+  indistinguishable from a dead cable.
+
+### Checks that run before Vivado does
+
+`checkbd`, `checklicence` and `checknets` run in seconds, against twenty
+minutes of synthesis. `checknets` compares every wire drawn between our
+own blocks against the widths those blocks actually have — every bug of
+that shape this repository has had lived in exactly that gap. `checkhwh`
+then audits the design **as built**, because the intent and the
+automation's result are different documents.
+
+### Known gaps
+
+- Nothing runs `sim/`: the four testbenches are launched by hand from a
+  `// Run:` comment in each. Two had rotted unnoticed before this
+  release and are fixed here.
+- The link-judge capture path is off by default (`capture: false`); it is
+  an episodic instrument, not a daily tax.

bayerlink_fpga-0.3.0/LICENSE

@@ -0,0 +1,45 @@
+SOLDERPAD HARDWARE LICENSE VERSION 2.1
+
+This license operates as a wraparound license to the Apache License Version 2.0 (the "Apache License") and incorporates the terms and conditions of the Apache License (which can be found here: http://apache.org/licenses/LICENSE-2.0), with the following additions and modifications. It must be read in conjunction with the Apache License. Section 1 below modifies definitions and terminology in the Apache License and Section 2 below replaces Section 2 of the Apache License. The Appendix replaces the Appendix in the Apache License. You may, at your option, choose to treat any Work released under this license as released under the Apache License (thus ignoring all sections written below entirely).
+
+1.	Terminology in the Apache License is supplemented or modified as follows:
+
+"Authorship": any reference to 'authorship' shall be taken to read "authorship or design".
+
+"Copyright owner": any reference to 'copyright owner' shall be taken to read "Rights owner".
+
+"Copyright statement": the reference to 'copyright statement' shall be taken to read 'copyright or other statement pertaining to Rights'
+
+The following new definition shall be added to the Definitions section of the Apache License:
+
+"Rights" means copyright and any similar right including design right (whether registered or unregistered), rights in semiconductor topographies (mask works) and database rights (but excluding Patents and Trademarks).
+
+The following definitions shall replace the corresponding definitions in the Apache License:
+
+"License" shall mean this Solderpad Hardware License version 2.1, being the terms and conditions for use, manufacture, instantiation, adaptation, reproduction, and distribution as defined by Sections 1 through 9 of this document.
+
+"Licensor" shall mean the Rights owner or entity authorized by the Rights owner that is granting the License.
+ 
+"Derivative Works" shall mean any work, whether in Source or Object form, that is based on (or derived from) the Work and for which the editorial revisions, annotations, elaborations, or other modifications represent, as a whole, an original work of authorship or design. For the purposes of this License, Derivative Works shall not include works that remain reversibly separable from, or merely link (or bind by name) or physically connect to or interoperate with the Work and Derivative Works thereof.
+
+"Object" form shall mean any form resulting from mechanical transformation or translation of a Source form or the application of a Source form to physical material, including but not limited to compiled object code, generated documentation, the instantiation of a hardware design or physical object or material and conversions to other media types, including intermediate forms such as bytecodes, FPGA bitstreams, moulds, artwork and semiconductor topographies (mask works).
+
+"Source" form shall mean the preferred form for making modifications, including but not limited to source code, net lists, board layouts, CAD files, documentation source, and configuration files.
+
+"Work" shall mean the work of authorship or design, whether in Source or Object form, made available under the License, as indicated by a notice relating to Rights that is included in or attached to the work (an example is provided in the Appendix below).
+
+2.	Grant of License. Subject to the terms and conditions of this License, each Contributor hereby grants to You a perpetual, worldwide, non-exclusive, no-charge, royalty-free, irrevocable license under the Rights to reproduce, prepare Derivative Works of, make, adapt, repair, publicly display, publicly perform, sublicense, and distribute the Work and such Derivative Works in Source or Object form and do anything in relation to the Work as if the Rights did not exist.
+
+
+APPENDIX
+
+Copyright [yyyy] [name of copyright owner]
+SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+
+Licensed under the Solderpad Hardware License v 2.1 (the "License"); you may not use this file except in compliance with the License, or, at your option, the Apache License version 2.0.
+You may obtain a copy of the License at
+
+https://solderpad.org/licenses/SHL-2.1/
+   
+Unless required by applicable law or agreed to in writing, any work distributed under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+See the License for the specific language governing permissions and limitations under the License.