avl-spi 0.1.0__tar.gz
This diff represents the content of publicly available package versions that have been released to one of the supported registries. The information contained in this diff is provided for informational purposes only and reflects changes between package versions as they appear in their respective public registries.
- avl_spi-0.1.0/LICENSE +21 -0
- avl_spi-0.1.0/PKG-INFO +189 -0
- avl_spi-0.1.0/README.md +143 -0
- avl_spi-0.1.0/avl_spi/__init__.py +29 -0
- avl_spi-0.1.0/avl_spi/_agent.py +119 -0
- avl_spi-0.1.0/avl_spi/_agent_cfg.py +36 -0
- avl_spi-0.1.0/avl_spi/_bandwidth.py +91 -0
- avl_spi-0.1.0/avl_spi/_coverage.py +74 -0
- avl_spi-0.1.0/avl_spi/_driver.py +111 -0
- avl_spi-0.1.0/avl_spi/_interface.py +201 -0
- avl_spi-0.1.0/avl_spi/_item.py +101 -0
- avl_spi-0.1.0/avl_spi/_mdriver.py +160 -0
- avl_spi-0.1.0/avl_spi/_monitor.py +110 -0
- avl_spi-0.1.0/avl_spi/_msequence.py +203 -0
- avl_spi-0.1.0/avl_spi/_sdriver.py +299 -0
- avl_spi-0.1.0/avl_spi/_ssequence.py +83 -0
- avl_spi-0.1.0/avl_spi/_tools.py +17 -0
- avl_spi-0.1.0/avl_spi/rtl/avl_spi.sv +96 -0
- avl_spi-0.1.0/pyproject.toml +58 -0
avl_spi-0.1.0/LICENSE
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MIT License
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Copyright (c) [2025] [avl@projectapheleia.net]
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to deal
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in the Software without restriction, including without limitation the rights
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to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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copies of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in all
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copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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SOFTWARE.
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avl_spi-0.1.0/PKG-INFO
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Metadata-Version: 2.4
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Name: avl-spi
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Version: 0.1.0
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Summary: Apheleia Verification Library - Serial Peripheral Interface verification component.
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License: MIT License
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Copyright (c) [2025] [avl@projectapheleia.net]
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to deal
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in the Software without restriction, including without limitation the rights
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to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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copies of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in all
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copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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SOFTWARE.
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License-File: LICENSE
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Author: avl
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Author-email: avl@projectapheleia.net
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Maintainer: avl
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Maintainer-email: avl@projectapheleia.net
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Requires-Python: >=3.10
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Classifier: Development Status :: 4 - Beta
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Classifier: Programming Language :: Python
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Provides-Extra: dev
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Requires-Dist: avl-core (>=1.1.0)
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Requires-Dist: black (>=22.3.0) ; extra == "dev"
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Requires-Dist: cocotb (>=2.1.0)
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Requires-Dist: matplotlib (>=3.10.0)
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Requires-Dist: mypy (>=0.910) ; extra == "dev"
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Requires-Dist: pytest (>=7.0) ; extra == "dev"
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Requires-Dist: ruff (>=0.11.0) ; extra == "dev"
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Requires-Dist: sphinx (>=8.1.3) ; extra == "dev"
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Requires-Dist: sphinx_rtd_theme (>=3.0.2) ; extra == "dev"
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Description-Content-Type: text/markdown
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# AVL-SPI - Apheleia Verification Library SPI Verification Component
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[](LICENSE)
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[](https://www.python.org/)
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AVL-SPI has been developed by experienced, industry professional verification engineers to provide a simple, \
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extensible verification component for the [Serial Peripheral Interface](https://en.wikipedia.org/wiki/Serial_Peripheral_Interface) \
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developed in [Python](https://www.python.org/) and the [AVL](https://avl-core.readthedocs.io/en/latest/index.html) library.
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AVL is built on the [CocoTB](https://docs.cocotb.org/en/stable/) framework, but aims to combine the best elements of \
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[UVM](https://accellera.org/community/uvm) in a more engineer friendly and efficient way.
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## CocoTB 2.0
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AVL-SPI supports [CocoTB 2.0](https://docs.cocotb.org/en/development/upgrade-2.0.html) and requires CocoTB 2.1 or later.
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## Protocol Features
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| Signal Name | Description | Driven By |
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|-------------|-------------|-----------|
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| SCLK | Serial clock. Idles at CPOL. | Master |
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| CS | Chip select; one per slave. Polarity configurable per slave. | Master |
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| MOSI | Master out, slave in serial data. | Master |
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| MISO | Master in, slave out serial data. | Slave |
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> **Note:** At present only single bit, uni-directional SPI is supported. Each SCLK cycle transfers one bit on MOSI (master to slave) and one bit on MISO (slave to master). Bi-directional (3-wire), dual, quad and QPI modes are not supported.
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## Component Features
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- Simple RTL interface to interact with HDL and define parameter and configuration options
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- Multiple chip selects with individual polarity
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- Clock polarity and individual drive and sample edges for master and slave (all 4 SPI modes and beyond)
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- Variable transfer length, MSB or LSB first
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- Chip select onehot0, setup, hold and inter-frame gap checks in the RTL interface
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- Master sequence, sequencer and driver with rate limiter, SCLK frequency and chip select timing control
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- Slave sequence, sequencer and driver with vanilla, random and memory response patterns
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- Monitor
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- Bandwidth monitor generating bus activity plots over user defined windows during simulation
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- Functional coverage
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- Searchable trace file generation
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---
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## 📦 Installation
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### Using `pip`
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```sh
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# Standard build
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pip install avl-spi
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# Development build
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pip install avl-spi[dev]
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```
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### Install from Source
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```sh
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git clone https://github.com/projectapheleia/avl-spi.git
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cd avl-spi
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# Standard build
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pip install .
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# Development build
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pip install .[dev]
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```
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Alternatively if you want to create a [virtual environment](https://docs.python.org/3/library/venv.html) rather than install globally a script is provided. This will install, with edit privileges to local virtual environment.
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This script assumes you have [Graphviz](https://graphviz.org/download/) and appropriate simulator installed, so all examples and documentation will build out of the box.
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```sh
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git clone https://github.com/projectapheleia/avl-spi.git
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cd avl-spi
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source avl-spi.sh
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```
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## 📖 Documentation
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In order to build the documentation you must have installed the development build.
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### Build from Source
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```sh
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cd doc
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make html
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<browser> build/html/index.html
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```
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## 🏃 Examples
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In order to run all the examples you must have installed the development build.
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To run all examples:
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```sh
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cd examples
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# To run
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make -j 8 sim
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# To clean
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make -j 8 clean
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```
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To run an individual example:
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```sh
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cd examples/THE EXAMPLE YOU WANT
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# To run
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make sim
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# To clean
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make clean
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```
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The examples use the [CocoTB Makefile](https://docs.cocotb.org/en/stable/building.html) and default to [Verilator](https://www.veripool.org/verilator/) with all waveforms generated. This can be modified using the standard CocoTB build system.
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---
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## 🧹 Code Style & Linting
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This project uses [**Ruff**](https://docs.astral.sh/ruff/) for linting and formatting.
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Check code for issues:
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```sh
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ruff check .
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```
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Automatically fix common issues:
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```sh
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ruff check . --fix
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```
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## 📧 Contact
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- Email: avl@projectapheleia.net
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- GitHub: [projectapheleia](https://github.com/projectapheleia)
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avl_spi-0.1.0/README.md
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# AVL-SPI - Apheleia Verification Library SPI Verification Component
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[](LICENSE)
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[](https://www.python.org/)
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AVL-SPI has been developed by experienced, industry professional verification engineers to provide a simple, \
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extensible verification component for the [Serial Peripheral Interface](https://en.wikipedia.org/wiki/Serial_Peripheral_Interface) \
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developed in [Python](https://www.python.org/) and the [AVL](https://avl-core.readthedocs.io/en/latest/index.html) library.
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AVL is built on the [CocoTB](https://docs.cocotb.org/en/stable/) framework, but aims to combine the best elements of \
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[UVM](https://accellera.org/community/uvm) in a more engineer friendly and efficient way.
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## CocoTB 2.0
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AVL-SPI supports [CocoTB 2.0](https://docs.cocotb.org/en/development/upgrade-2.0.html) and requires CocoTB 2.1 or later.
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## Protocol Features
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| Signal Name | Description | Driven By |
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|-------------|-------------|-----------|
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| SCLK | Serial clock. Idles at CPOL. | Master |
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| CS | Chip select; one per slave. Polarity configurable per slave. | Master |
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| MOSI | Master out, slave in serial data. | Master |
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| MISO | Master in, slave out serial data. | Slave |
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> **Note:** At present only single bit, uni-directional SPI is supported. Each SCLK cycle transfers one bit on MOSI (master to slave) and one bit on MISO (slave to master). Bi-directional (3-wire), dual, quad and QPI modes are not supported.
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## Component Features
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|
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31
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- Simple RTL interface to interact with HDL and define parameter and configuration options
|
|
32
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+
- Multiple chip selects with individual polarity
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33
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+
- Clock polarity and individual drive and sample edges for master and slave (all 4 SPI modes and beyond)
|
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34
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- Variable transfer length, MSB or LSB first
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35
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+
- Chip select onehot0, setup, hold and inter-frame gap checks in the RTL interface
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36
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- Master sequence, sequencer and driver with rate limiter, SCLK frequency and chip select timing control
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- Slave sequence, sequencer and driver with vanilla, random and memory response patterns
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38
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- Monitor
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- Bandwidth monitor generating bus activity plots over user defined windows during simulation
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- Functional coverage
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- Searchable trace file generation
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---
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## 📦 Installation
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### Using `pip`
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```sh
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# Standard build
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pip install avl-spi
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# Development build
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pip install avl-spi[dev]
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```
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### Install from Source
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```sh
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git clone https://github.com/projectapheleia/avl-spi.git
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cd avl-spi
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# Standard build
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pip install .
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# Development build
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pip install .[dev]
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```
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Alternatively if you want to create a [virtual environment](https://docs.python.org/3/library/venv.html) rather than install globally a script is provided. This will install, with edit privileges to local virtual environment.
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69
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This script assumes you have [Graphviz](https://graphviz.org/download/) and appropriate simulator installed, so all examples and documentation will build out of the box.
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```sh
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git clone https://github.com/projectapheleia/avl-spi.git
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cd avl-spi
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source avl-spi.sh
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```
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## 📖 Documentation
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In order to build the documentation you must have installed the development build.
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### Build from Source
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```sh
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cd doc
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make html
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<browser> build/html/index.html
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```
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## 🏃 Examples
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In order to run all the examples you must have installed the development build.
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To run all examples:
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```sh
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cd examples
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# To run
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make -j 8 sim
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# To clean
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make -j 8 clean
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```
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To run an individual example:
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```sh
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cd examples/THE EXAMPLE YOU WANT
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# To run
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make sim
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# To clean
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make clean
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```
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The examples use the [CocoTB Makefile](https://docs.cocotb.org/en/stable/building.html) and default to [Verilator](https://www.veripool.org/verilator/) with all waveforms generated. This can be modified using the standard CocoTB build system.
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---
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## 🧹 Code Style & Linting
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This project uses [**Ruff**](https://docs.astral.sh/ruff/) for linting and formatting.
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Check code for issues:
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```sh
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ruff check .
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```
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Automatically fix common issues:
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+
```sh
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ruff check . --fix
|
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+
```
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## 📧 Contact
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- Email: avl@projectapheleia.net
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- GitHub: [projectapheleia](https://github.com/projectapheleia)
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@@ -0,0 +1,29 @@
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from ._agent import Agent
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from ._agent_cfg import AgentCfg
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from ._bandwidth import Bandwidth
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from ._coverage import Coverage
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from ._item import SequenceItem
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from ._mdriver import MstDriver
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from ._monitor import Monitor
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from ._msequence import MstMemorySequence, MstSequence
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from ._sdriver import SlvDriver, SlvMemoryDriver, SlvRandomDriver
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from ._ssequence import SlvSequence
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# Add version
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__version__: str = "0.1.0"
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__all__ = [
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"Agent",
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"AgentCfg",
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"Bandwidth",
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"Coverage",
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"SequenceItem",
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"Monitor",
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"MstDriver",
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"MstSequence",
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"MstMemorySequence",
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"SlvDriver",
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"SlvRandomDriver",
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"SlvMemoryDriver",
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"SlvSequence",
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]
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# Copyright 2026 Apheleia
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#
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# Description:
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# Apheleia Verification Library Agent
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+
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import avl
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import cocotb
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8
|
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from cocotb.handle import HierarchyObject
|
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9
|
+
from cocotb.triggers import NextTimeStep, RisingEdge
|
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10
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+
|
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11
|
+
from ._agent_cfg import AgentCfg
|
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|
+
from ._bandwidth import Bandwidth
|
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+
from ._coverage import Coverage
|
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from ._interface import Interface
|
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|
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from ._mdriver import MstDriver
|
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from ._monitor import Monitor
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+
from ._msequence import MstSequence
|
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from ._sdriver import SlvDriver
|
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|
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from ._ssequence import SlvSequence
|
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+
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+
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class Agent(avl.Agent):
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def __init__(self, name: str, parent: avl.Component) -> None:
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"""
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|
+
Initialize the avl-spi Agent
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+
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:param name: Name of the agent instance
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:type name: str
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:param parent: Parent component
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:type parent: Component
|
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+
"""
|
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+
super().__init__(name, parent)
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|
+
|
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34
|
+
# Create configuration and export to children
|
|
35
|
+
self.cfg = avl.Factory.get_variable(f"{self.get_full_name()}.cfg", AgentCfg("cfg", self))
|
|
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|
+
avl.Factory.set_variable(f"{self.get_full_name()}.*.cfg", self.cfg)
|
|
37
|
+
|
|
38
|
+
# Bind HDL to establish parameters and configuration
|
|
39
|
+
self._bind_(avl.Factory.get_variable(f"{self.get_full_name()}.hdl", None))
|
|
40
|
+
|
|
41
|
+
# Create sequencer and driver if master is enabled
|
|
42
|
+
if self.cfg.has_master:
|
|
43
|
+
self.msqr = avl.Sequencer("msqr", self)
|
|
44
|
+
self.mseq = MstSequence("mseq", self.msqr)
|
|
45
|
+
self.mdrv = MstDriver("mdrv", self)
|
|
46
|
+
self.msqr.seq_item_export.connect(self.mdrv.seq_item_port)
|
|
47
|
+
|
|
48
|
+
# Create sequencer, sequence and driver for each slave
|
|
49
|
+
if self.cfg.num_slave > 1:
|
|
50
|
+
self.ssqr, self.sseq, self.sdrv = [], [], []
|
|
51
|
+
for i in range(self.cfg.num_slave):
|
|
52
|
+
avl.Factory.set_variable(f"{self.get_full_name()}.sdrv_{i}.idx", i)
|
|
53
|
+
self.ssqr.append(avl.Sequencer(f"ssqr_{i}", self))
|
|
54
|
+
self.sseq.append(SlvSequence("sseq", self.ssqr[i]))
|
|
55
|
+
self.sdrv.append(SlvDriver(f"sdrv_{i}", self))
|
|
56
|
+
self.ssqr[i].seq_item_export.connect(self.sdrv[i].seq_item_port)
|
|
57
|
+
elif self.cfg.num_slave == 1:
|
|
58
|
+
self.ssqr = avl.Sequencer("ssqr", self)
|
|
59
|
+
self.sseq = SlvSequence("sseq", self.ssqr)
|
|
60
|
+
self.sdrv = SlvDriver("sdrv", self)
|
|
61
|
+
self.ssqr.seq_item_export.connect(self.sdrv.seq_item_port)
|
|
62
|
+
|
|
63
|
+
# Create monitor if enabled
|
|
64
|
+
if self.cfg.has_monitor:
|
|
65
|
+
self.monitor = Monitor("monitor", self)
|
|
66
|
+
|
|
67
|
+
if self.cfg.has_coverage:
|
|
68
|
+
self.coverage = Coverage("coverage", self)
|
|
69
|
+
self.monitor.item_export.connect(self.coverage.item_port)
|
|
70
|
+
|
|
71
|
+
if self.cfg.has_bandwidth:
|
|
72
|
+
self.bandwidth = Bandwidth("bandwidth", self)
|
|
73
|
+
self.monitor.item_export.connect(self.bandwidth.item_port)
|
|
74
|
+
|
|
75
|
+
if self.cfg.has_trace:
|
|
76
|
+
self.trace = avl.Trace("trace", self)
|
|
77
|
+
self.monitor.item_export.connect(self.trace.item_port)
|
|
78
|
+
|
|
79
|
+
def _bind_(self, hdl) -> None:
|
|
80
|
+
"""
|
|
81
|
+
Bind the agent to a hardware description language (HDL) interface.
|
|
82
|
+
This method is used to associate the agent with a specific HDL interface,
|
|
83
|
+
allowing it to interact with the hardware model.
|
|
84
|
+
|
|
85
|
+
:param hdl: The HDL interface to bind to the agent
|
|
86
|
+
:type hdl: HierarchyObject
|
|
87
|
+
:raises TypeError: If `hdl` is not an instance of HierarchyObject
|
|
88
|
+
"""
|
|
89
|
+
if not isinstance(hdl, HierarchyObject):
|
|
90
|
+
raise TypeError(f"Expected HierarchyObject, got {type(hdl)}")
|
|
91
|
+
|
|
92
|
+
# Assign Interface
|
|
93
|
+
self.i_f = Interface(hdl)
|
|
94
|
+
avl.Factory.set_variable(f"{self.get_full_name()}.*.i_f", self.i_f)
|
|
95
|
+
|
|
96
|
+
async def run_phase(self) -> None:
|
|
97
|
+
"""
|
|
98
|
+
Run the agent's phase. This method is called to start the agent's operation.
|
|
99
|
+
It starts the slave sequences, and the master sequence if the master is enabled.
|
|
100
|
+
Slave sequences are not awaited, as they depend on transfers from the master.
|
|
101
|
+
"""
|
|
102
|
+
|
|
103
|
+
self.raise_objection()
|
|
104
|
+
await NextTimeStep()
|
|
105
|
+
|
|
106
|
+
if self.cfg.num_slave > 0:
|
|
107
|
+
for s in (self.sseq if isinstance(self.sseq, list) else [self.sseq]):
|
|
108
|
+
cocotb.start_soon(s.start())
|
|
109
|
+
|
|
110
|
+
if self.cfg.has_master:
|
|
111
|
+
await self.mseq.start()
|
|
112
|
+
|
|
113
|
+
# Run-off
|
|
114
|
+
for _ in range(10):
|
|
115
|
+
await RisingEdge(self.i_f.clk)
|
|
116
|
+
|
|
117
|
+
self.drop_objection()
|
|
118
|
+
|
|
119
|
+
__all__ = ["Agent"]
|
|
@@ -0,0 +1,36 @@
|
|
|
1
|
+
# Copyright 2026 Apheleia
|
|
2
|
+
#
|
|
3
|
+
# Description:
|
|
4
|
+
# Apheleia Verification Library Agent Configuration
|
|
5
|
+
|
|
6
|
+
import avl
|
|
7
|
+
|
|
8
|
+
|
|
9
|
+
class AgentCfg(avl.Object):
|
|
10
|
+
|
|
11
|
+
def __init__(self, name: str, parent: avl.Component) -> None:
|
|
12
|
+
"""
|
|
13
|
+
Initialize the avl-spi Agent Configuration
|
|
14
|
+
|
|
15
|
+
:param name: Name of the agent instance
|
|
16
|
+
:type name: str
|
|
17
|
+
:param parent: Parent component
|
|
18
|
+
:type parent: Component
|
|
19
|
+
"""
|
|
20
|
+
super().__init__(name, parent)
|
|
21
|
+
|
|
22
|
+
# Agent Attributes
|
|
23
|
+
self.has_master = avl.Factory.get_variable(f"{self.get_full_name()}.has_master", False)
|
|
24
|
+
"""Has Master Driver"""
|
|
25
|
+
self.num_slave = avl.Factory.get_variable(f"{self.get_full_name()}.num_slave", 0)
|
|
26
|
+
"""Number of Slave Drivers"""
|
|
27
|
+
self.has_monitor = avl.Factory.get_variable(f"{self.get_full_name()}.has_monitor", False)
|
|
28
|
+
"""Has Monitor"""
|
|
29
|
+
self.has_coverage = avl.Factory.get_variable(f"{self.get_full_name()}.has_coverage", False)
|
|
30
|
+
"""Has Functional Coverage"""
|
|
31
|
+
self.has_bandwidth = avl.Factory.get_variable(f"{self.get_full_name()}.has_bandwidth", False)
|
|
32
|
+
"""Has Bandwidth Monitor"""
|
|
33
|
+
self.has_trace = avl.Factory.get_variable(f"{self.get_full_name()}.has_trace", False)
|
|
34
|
+
"""Has Trace Generator"""
|
|
35
|
+
|
|
36
|
+
__all__ = ["AgentCfg"]
|
|
@@ -0,0 +1,91 @@
|
|
|
1
|
+
# Copyright 2026 Apheleia
|
|
2
|
+
#
|
|
3
|
+
# Description:
|
|
4
|
+
# Apheleia Verification Library Bandwidth Monitor
|
|
5
|
+
|
|
6
|
+
import avl
|
|
7
|
+
import cocotb
|
|
8
|
+
from avl._core._lazy import lazy_import
|
|
9
|
+
from cocotb.triggers import Timer
|
|
10
|
+
from cocotb.utils import get_sim_time
|
|
11
|
+
|
|
12
|
+
# Deferred until the report phase
|
|
13
|
+
plt = lazy_import("matplotlib.pyplot")
|
|
14
|
+
np = lazy_import("numpy")
|
|
15
|
+
|
|
16
|
+
|
|
17
|
+
class Bandwidth(avl.Component):
|
|
18
|
+
|
|
19
|
+
def __init__(self, name: str, parent: avl.Component) -> None:
|
|
20
|
+
"""
|
|
21
|
+
Initialize Bandwidth Monitor
|
|
22
|
+
|
|
23
|
+
Class contains variable window_ns which defines the time window in nanoseconds. This
|
|
24
|
+
is configurable via the factory.
|
|
25
|
+
|
|
26
|
+
:param name: Name of the bandwidth monitor.
|
|
27
|
+
:type name: str
|
|
28
|
+
:param parent: Parent component.
|
|
29
|
+
:type parent: Component
|
|
30
|
+
"""
|
|
31
|
+
super().__init__(name, parent)
|
|
32
|
+
self.i_f = avl.Factory.get_variable(f"{self.get_full_name()}.i_f", None)
|
|
33
|
+
|
|
34
|
+
self.window_ns = avl.Factory.get_variable(f"{self.get_full_name()}.window_ns", 1000)
|
|
35
|
+
""" Rolling time window in nanoseconds for bandwidth calculation. Default is 1000 ns. """
|
|
36
|
+
|
|
37
|
+
self.item_port = avl.List()
|
|
38
|
+
self.bandwidth = {}
|
|
39
|
+
|
|
40
|
+
async def run_phase(self) -> None:
|
|
41
|
+
"""
|
|
42
|
+
Run phase for the bandwidth component.
|
|
43
|
+
|
|
44
|
+
"""
|
|
45
|
+
async def counter():
|
|
46
|
+
while True:
|
|
47
|
+
self.item = await self.item_port.blocking_get()
|
|
48
|
+
self.bandwidth[t] += int(self.item.get("length"))
|
|
49
|
+
|
|
50
|
+
cocotb.start_soon(counter())
|
|
51
|
+
|
|
52
|
+
while True:
|
|
53
|
+
t = get_sim_time(unit="ns")
|
|
54
|
+
self.bandwidth[t] = 0
|
|
55
|
+
|
|
56
|
+
self.raise_objection()
|
|
57
|
+
await Timer(self.window_ns, unit="ns")
|
|
58
|
+
self.drop_objection()
|
|
59
|
+
|
|
60
|
+
async def report_phase(self) -> None:
|
|
61
|
+
"""
|
|
62
|
+
Report phase for the bandwidth component.
|
|
63
|
+
|
|
64
|
+
Generate plot of bits on bus over time windows
|
|
65
|
+
|
|
66
|
+
"""
|
|
67
|
+
times = list(self.bandwidth.keys())
|
|
68
|
+
counts = list(self.bandwidth.values())
|
|
69
|
+
|
|
70
|
+
if len(times) > 1:
|
|
71
|
+
# For unevenly spaced data, calculate individual widths
|
|
72
|
+
# This uses the minimum spacing to avoid overlapping bars
|
|
73
|
+
spacings = np.diff(times)
|
|
74
|
+
bar_width = np.min(spacings)
|
|
75
|
+
else:
|
|
76
|
+
# For single bar, use a default width
|
|
77
|
+
bar_width = 1
|
|
78
|
+
|
|
79
|
+
# Create plot
|
|
80
|
+
plt.figure(figsize=(8, 4))
|
|
81
|
+
plt.bar(times, counts, width=bar_width, align='center')
|
|
82
|
+
plt.title("Bus Bandwidth (Bits over Time)")
|
|
83
|
+
plt.xlabel("Time (ns)")
|
|
84
|
+
plt.ylabel("Bit Count")
|
|
85
|
+
plt.grid(True)
|
|
86
|
+
|
|
87
|
+
# Export to PNG
|
|
88
|
+
plt.savefig(f"{self.get_full_name()}.png")
|
|
89
|
+
plt.close()
|
|
90
|
+
|
|
91
|
+
__all__ = ["Bandwidth"]
|