atopile 0.3.7.dev0__tar.gz → 0.3.8.dev0__tar.gz

{atopile-0.3.7.dev0 → atopile-0.3.8.dev0}/PKG-INFO

@@ -1,6 +1,6 @@
 Metadata-Version: 2.4
 Name: atopile
-Version: 0.3.7.dev0
+Version: 0.3.8.dev0
 Summary: A toolchain bringing the best of software development to the real-world!
 Project-URL: Homepage, https://github.com/atopile/atopile
 Project-URL: Bug Tracker, https://github.com/atopile/atopile/issues

atopile-0.3.8.dev0/docs/CNAME

@@ -0,0 +1 @@
+docs.atopile.io

{atopile-0.3.7.dev0 → atopile-0.3.8.dev0}/src/atopile/cli/build.py

@@ -92,7 +92,7 @@ def build(
                 lcsc.BUILD_FOLDER = build_ctx.paths.build
                 lcsc.LIB_FOLDER = build_ctx.paths.component_lib
                 lcsc.LIB_FOLDER.mkdir(exist_ok=True, parents=True)
-                # lcsc.MODEL_PATH = None  # TODO: assign to something to download the 3d models # noqa: E501  # pre-existing
+                lcsc.KICAD_PROJECT_PATH = build_ctx.paths.kicad_project.parent
 
                 # TODO: add a mechanism to override the following with custom build machinery # noqa: E501  # pre-existing
                 buildutil.build(build_ctx, app)

{atopile-0.3.7.dev0 → atopile-0.3.8.dev0}/src/faebryk/exporters/pcb/kicad/pcb.py

@@ -26,9 +26,11 @@ from faebryk.libs.sexp.dataclass_sexp import get_parent
 from faebryk.libs.util import (
     KeyErrorNotFound,
     dataclass_as_kwargs,
+    duplicates,
     find,
     find_or,
     not_none,
+    yield_missing,
 )
 
 logger = logging.getLogger(__name__)
@@ -283,22 +285,23 @@ class PCB:
 
         # Add new nets -----------------------------------------------------------------
         logger.debug(f"New nets: {nets_added}")
+        existing_net_numbers = {net.number for net in pcb.kicad_pcb.nets}
+        net_numbers = iter(yield_missing(existing_net_numbers))
+
         for net_name in nets_added:
-            # nl_net = nl_nets[net_name]
-            if removed_net_numbers:
-                net_number = removed_net_numbers.pop()
-            else:
-                net_number = len(pcb.kicad_pcb.nets)
+            # Find the first unused net number
+            net_number = next(net_numbers)
+
             pcb_net = C_kicad_pcb_file.C_kicad_pcb.C_net(
                 name=net_name,
                 number=net_number,
             )
             pcb.kicad_pcb.nets.append(pcb_net)
             pcb_nets[net_name] = (pcb_net, [])
+
         pcb.kicad_pcb.nets.sort(key=lambda x: x.number)
         # Check that net numbers are unique
-        # FIXME: this is broken by conflicting net numbers on the loaded PCB
-        assert len(pcb.kicad_pcb.nets) == len(set(n.number for n in pcb.kicad_pcb.nets))
+        assert not duplicates(pcb.kicad_pcb.nets, lambda x: x.number)
 
         # Components ===================================================================
         pcb_comps = {
@@ -431,12 +434,13 @@ class PCB:
                             )
                             if p.name in pads
                             else None,
-                            # rest of fields
-                            **dataclass_as_kwargs(p),
+                            **{
+                                **dataclass_as_kwargs(p),
+                                "at": C_xyr(x=p.at.x, y=p.at.y, r=p.at.r + at.r),
+                            },
                         )
                         for p in footprint.pads
                     ],
-                    #
                     name=footprint_identifier,
                     layer=footprint.layer,
                     propertys=footprint.propertys,

{atopile-0.3.7.dev0 → atopile-0.3.8.dev0}/src/faebryk/library/CH342F.py

@@ -25,13 +25,13 @@ class CH342F(F.CH342):
         ...
 
         @assert_once
-        def enable_tnow_mode(self):
+        def enable_tnow_mode(self, owner: Module):
             """
             Set TNOW mode for specified UART for use with RS485 tranceivers.
             The TNOW pin can be connected to the tx_enable and rx_enable
             pins of the RS485 tranceiver for automatic half-duplex control.
             """
-            self.uart.dtr.set_weak(on=False)
+            self.uart.dtr.set_weak(on=False, owner=owner)
             self.uart.dtr.connect(self.tnow)
 
     # ----------------------------------------

{atopile-0.3.7.dev0 → atopile-0.3.8.dev0}/src/faebryk/library/CH344.py

@@ -70,9 +70,6 @@ class CH344(Module):
         self.gpio[14].connect(self.uart[0].dsr)
         self.gpio[15].connect(self.uart[1].dcd)
 
-        # FIXME
-        # self.test.set_weak(on=False)
-
         # ------------------------------------
         #          parametrization
         # ------------------------------------

{atopile-0.3.7.dev0 → atopile-0.3.8.dev0}/src/faebryk/library/CH344Q_ReferenceDesign.py

@@ -111,6 +111,8 @@ class CH344Q_ReferenceDesign(Module):
         # TODO: already done by lowpass filter
         # self.usb_uart_converter.reset.pulled.pull(up=True)
 
+        self.usb_uart_converter.test.set_weak(on=False, owner=self)
+
         self.ldo.enable_output()
 
         # ------------------------------------

{atopile-0.3.7.dev0 → atopile-0.3.8.dev0}/src/faebryk/library/EnablePin.py

@@ -2,6 +2,7 @@
 # SPDX-License-Identifier: MIT
 
 import faebryk.library._F as F
+from faebryk.core.module import Module
 from faebryk.core.moduleinterface import ModuleInterface
 from faebryk.libs.library import L
 
@@ -17,8 +18,8 @@ class EnablePin(ModuleInterface):
         self.add(F.is_optional_defined(not value, self._handle_optional))
         self.enable.set(value)
 
-    def set_weak(self, value: bool):
-        self.enable.set_weak(value)
+    def set_weak(self, value: bool, owner: Module):
+        self.enable.set_weak(value, owner=owner)
 
     @L.rt_field
     def has_single_electric_reference(self):

{atopile-0.3.7.dev0 → atopile-0.3.8.dev0}/src/faebryk/library/WCHJiangsu_Qin_Heng_CH224K.py

@@ -24,6 +24,7 @@ class WCHJiangsu_Qin_Heng_CH224K(Module):
     @assert_once
     def config_voltage(
         self,
+        owner: Module,
         voltage: Literal["5V", "9V", "12V", "15V", "20V"],
         mode: Literal["Resistor", "LogicLevel"] = "LogicLevel",
     ):
@@ -47,7 +48,7 @@ class WCHJiangsu_Qin_Heng_CH224K(Module):
             elif voltage == "20V":
                 return  # no resistor connected
 
-            self.cfg[0].set_weak(on=False).resistance.constrain_subset(
+            self.cfg[0].set_weak(on=False, owner=owner).resistance.constrain_subset(
                 connection_matrix[voltage][0]
             )
         elif mode == "LogicLevel":

{atopile-0.3.7.dev0 → atopile-0.3.8.dev0}/src/faebryk/library/WCHJiangsu_Qin_Heng_CH224K_ReferenceDesign.py

@@ -39,7 +39,7 @@ class WCHJiangsu_Qin_Heng_CH224K_ReferenceDesign(Module):
         # ------------------------------------
         self.controller.vbus_detect.set_weak(
             on=True, owner=self
-        ).resistance.constrain_subset(L.Range.from_center_rel(1 * P.kohm, 0.01))
+        ).resistance.constrain_subset(L.Range.from_center_rel(10 * P.kohm, 0.01))
         self.controller.vbus_detect.reference.connect(self.vbus)
 
         self.controller.power.hv.connect_via(self.vdd_resistor, self.vbus.hv)
@@ -60,5 +60,5 @@ class WCHJiangsu_Qin_Heng_CH224K_ReferenceDesign(Module):
         )
 
         self.vdd_resistor.resistance.constrain_subset(
-            L.Range.from_center_rel(10 * P.kohm, 0.01)
+            L.Range.from_center_rel(1 * P.kohm, 0.01)
         )

{atopile-0.3.7.dev0 → atopile-0.3.8.dev0}/src/faebryk/libs/picker/lcsc.py

@@ -34,7 +34,8 @@ CRAWL_DATASHEET = ConfigFlag(
 # TODO dont hardcode relative paths
 BUILD_FOLDER = Path("./build")
 LIB_FOLDER = Path("./src/kicad/libs")
-MODEL_PATH: str | None = "${KIPRJMOD}/../libs/"
+KICAD_PROJECT_PATH: Path | None = None
+MODEL_PATH: str | None = None
 
 EXPORT_NON_EXISTING_MODELS = False
 
@@ -172,6 +173,11 @@ def download_easyeda_info(lcsc_id: str, get_model: bool = True):
         kicad_model_path = (
             f"{MODEL_PATH}/3dmodels/lcsc.3dshapes"
             if MODEL_PATH
+            else str(
+                "${KIPRJMOD}"
+                / model_base_path_full.relative_to(KICAD_PROJECT_PATH, walk_up=True)
+            )
+            if KICAD_PROJECT_PATH
             else str(model_base_path_full.resolve())
         )
         ki_footprint.export(

{atopile-0.3.7.dev0 → atopile-0.3.8.dev0}/src/faebryk/libs/util.py

@@ -33,6 +33,7 @@ from typing import (
     Any,
     Callable,
     Concatenate,
+    Container,
     Generator,
     Hashable,
     Iterable,
@@ -1813,6 +1814,14 @@ def robustly_rm_dir(path: os.PathLike) -> None:
     shutil.rmtree(path, onexc=remove_readonly)
 
 
+def yield_missing(existing: Container, candidates: Iterable | None = None):
+    if candidates is None:
+        candidates = range(10000)  # Prevent counting to infinity by default
+    for c in candidates:
+        if c not in existing:
+            yield c
+
+
 def try_relative_to(
     target: os.PathLike, root: os.PathLike | None = None, walk_up: bool = False
 ) -> Path:

atopile-0.3.8.dev0/test/libs/util/test_yield_missing.py

@@ -0,0 +1,29 @@
+import pytest
+
+from faebryk.libs.util import yield_missing
+
+
+def test_basic():
+    existing = {1, 2, 3}
+    candidates = [1, 2, 3, 4, 5]
+    assert list(yield_missing(existing, candidates)) == [4, 5]
+
+
+def test_no_candidates():
+    existing = {0, 1, 3}
+    missing = iter(yield_missing(existing))
+    assert next(missing) == 2
+    assert next(missing) == 4
+    assert next(missing) == 5
+    assert next(missing) == 6
+
+
+def test_max_range():
+    existing = {1, 2, 3}
+    missing = iter(yield_missing(existing, range(7)))
+    assert next(missing) == 0
+    assert next(missing) == 4
+    assert next(missing) == 5
+    assert next(missing) == 6
+    with pytest.raises(StopIteration):
+        next(missing)

atopile-0.3.7.dev0/docs/CNAME

@@ -1 +0,0 @@
-atopile.io