SimplHDL 0.8.2__tar.gz → 0.10.1__tar.gz

{simplhdl-0.8.2/src/SimplHDL.egg-info → simplhdl-0.10.1}/PKG-INFO

@@ -1,6 +1,6 @@
 Metadata-Version: 2.4
-Name: SimplHDL
-Version: 0.8.2
+Name: simplhdl
+Version: 0.10.1
 Summary: A framework for simulating and implementing HDL designs
 Author-email: Rasmus Grøndahl Olsen <simplhdl@gmail.com>
 Maintainer-email: Rasmus Grøndahl Olsen <simplhdl@gmail.com>
@@ -26,12 +26,15 @@ License: MIT License
         OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
         SOFTWARE.
         
-Project-URL: Homepage, https://github.com/SimplHDL
 Project-URL: Documentation, https://simplhdl.readthedocs.io/en/latest/
-Project-URL: Repository, https://github.com/SimplHDL/simplhdl.git
+Project-URL: Homepage, https://github.com/SimplHDL
 Project-URL: Issues, https://github.com/SimplHDL/simplhdl/issues
+Project-URL: Repository, https://github.com/SimplHDL/simplhdl.git
 Classifier: Development Status :: 4 - Beta
-Classifier: Programming Language :: Python :: 3
+Classifier: Intended Audience :: Developers
+Classifier: License :: OSI Approved :: MIT License
+Classifier: Operating System :: OS Independent
+Classifier: Programming Language :: Python :: 3 :: Only
 Classifier: Programming Language :: Python :: 3.8
 Classifier: Programming Language :: Python :: 3.9
 Classifier: Programming Language :: Python :: 3.10
@@ -39,92 +42,93 @@ Classifier: Programming Language :: Python :: 3.11
 Classifier: Programming Language :: Python :: 3.12
 Classifier: Programming Language :: Python :: 3.13
 Classifier: Programming Language :: Python :: 3.14
-Classifier: Intended Audience :: Developers
-Classifier: License :: OSI Approved :: MIT License
-Classifier: Operating System :: OS Independent
 Requires-Python: >=3.8
 Description-Content-Type: text/markdown
 License-File: LICENSE
-Requires-Dist: importlib-resources; python_version < "3.9"
-Requires-Dist: pySVModel==0.3.5
-Requires-Dist: pyEDAA.ProjectModel==0.4.3
-Requires-Dist: pyyaml
-Requires-Dist: types-PyYAML
 Requires-Dist: argcomplete
-Requires-Dist: jinja2
-Requires-Dist: GitPython
-Requires-Dist: rich
-Requires-Dist: vsg
-Requires-Dist: flake8
 Requires-Dist: black
-Requires-Dist: systemrdl-compiler
+Requires-Dist: flake8
+Requires-Dist: gitpython
+Requires-Dist: importlib-resources; python_version < "3.9"
+Requires-Dist: jinja2
+Requires-Dist: matplotlib
+Requires-Dist: networkx
 Requires-Dist: peakrdl-html
-Requires-Dist: peakrdl-regblock>=1.2.0
 Requires-Dist: peakrdl-pyuvm
+Requires-Dist: peakrdl-regblock>=1.2
+Requires-Dist: pyyaml
+Requires-Dist: rich
+Requires-Dist: singleton-decorator
+Requires-Dist: systemrdl-compiler
+Requires-Dist: types-pyyaml
+Requires-Dist: vsg
+Provides-Extra: dev
+Requires-Dist: flake8; extra == "dev"
+Requires-Dist: mypy; extra == "dev"
+Requires-Dist: robotframework; extra == "dev"
+Requires-Dist: tox; extra == "dev"
+Provides-Extra: docs
+Requires-Dist: furo; extra == "docs"
+Requires-Dist: sphinx; extra == "docs"
+Requires-Dist: sphinx-pyproject; extra == "docs"
 Dynamic: license-file
 
 ## Introduction
 
-SimplHDL is a plugin-based command-line application for simplifying FPGA and
-ASIC development regardless of EDA tools and flows.
+SimplHDL is a plugin-based command-line application for simplifying FPGA and ASIC development regardless of EDA tools
+and flows.
 
-The goal is to embrase structured and reusable designs by creating a generic
-project model that can be used in any hdl development flow regardless of
-project structure and EDA tool requirements.
+The goal is to embrase structured and reusable designs by creating a generic project model that can be used in any hdl
+development flow regardless of project structure and EDA tool requirements.
 
-The plugin based architecture allows for SimplHDL to be migrated into any
-existing project, replacing ad-hoc simulation and implmentation scripts while
-providing a intuitive command-line interface for HDL design and verification
-engineers.
+The plugin based architecture allows for SimplHDL to be migrated into any existing project, replacing ad-hoc simulation
+and implementation scripts while providing a intuitive command-line interface for HDL design and verification engineers.
 
-I wide vararity of languges, standards and tools are supported.
+I wide vararity of languages, standards and tools are supported.
 
 ### HDL languages
 
-* Verilog / System Verilog
-* VHDL
-* Chisel
-* SystemRDL
-* IPXact
-* Vivado IP containters (.xci, .xcix)
-* Quartus IP containers (.ip)
+- Verilog / System Verilog
+- VHDL
+- Chisel
+- SystemRDL
+- IPXact
+- Vivado IP containers (.xci, .xcix)
+- Quartus IP containers (.ip)
 
 ### Methodologies
 
-* UVM
-* OSVMM
-* UVVM
-* Cocotb
-* pyuvm
+- UVM
+- OSVMM
+- UVVM
+- Cocotb
+- pyuvm
 
 ### EDA Tools
 
-* Vivado
-* Quartus
-* Modelsim
-* Questasim
-* Xsim
-* Vcs
-* Riviera Pro
-* Xcelium (coming)
-* Verilator (coming)
-* Icarus (coming)
-* GHDL (coming)
+- Vivado
+- Quartus
+- Modelsim
+- Questasim
+- Xsim
+- Vcs
+- Riviera Pro
+- Xcelium (coming)
+- Verilator (coming)
+- Icarus (coming)
+- GHDL (coming)
 
 ## Getting Started
 
-SimplHDL currently works on Linux and Windows WSL. It is written in Python and can
-be installed with *pip*. To run SimplHDL Python 3.8 or later is required. The
-tools for the flows you wish to run also need to be installed and set up
-correctly in the shell environment. SimplHDL can be installed on your system's
-Python installation, but it is highly recommended to install and run SimplHDL
-in a Python virtual environment or a Conda environment.
+SimplHDL currently works on Linux and Windows WSL. It is written in Python and can be installed with _pip_. To run
+SimplHDL Python 3.8 or later is required. The tools for the flows you wish to run also need to be installed and set up
+correctly in the shell environment. SimplHDL can be installed on your system's Python installation, but it is highly
+recommended to install and run SimplHDL in a Python virtual environment or a Conda environment.
 
 ## Example
 
-To quickly try out SimplHDL follow these steps. In this example, we will use
-Vivado and QuestaSim. The prerequisites are that SimplHDL install installed and
-Vivado and QuestaSim are correctly set up in your shell environment.
+To quickly try out SimplHDL follow these steps. In this example, we will use Vivado and QuestaSim. The prerequisites are
+that SimplHDL install installed and Vivado and QuestaSim are correctly set up in your shell environment.
 
 1. Clone Git repository from GitHub
 
@@ -165,13 +169,12 @@ simpl vivado
 simpl vivado --gui
 ```
 
-In this example, the project specification is written in Yaml. This format is
-only meant as a demonstration. To integrate SimplHDL into your project, you have
-to write a parser plugin for your specific project specification format.
+In this example, the project specification is written in Yaml. This format is only meant as a demonstration. To
+integrate SimplHDL into your project, you have to write a parser plugin for your specific project specification format.
 See the documentation and plugin examples for more information.
 
 ## Links
 
-* Homepage:
-* Source: <https://github.com/SimplHDL/simplhdl>
-* Tracker: <https://github.com/SimplHDL/simplhdl/issues>
+- Homepage:
+- Source: <https://github.com/SimplHDL/simplhdl>
+- Tracker: <https://github.com/SimplHDL/simplhdl/issues>

simplhdl-0.10.1/README.md

@@ -0,0 +1,105 @@
+## Introduction
+
+SimplHDL is a plugin-based command-line application for simplifying FPGA and ASIC development regardless of EDA tools
+and flows.
+
+The goal is to embrase structured and reusable designs by creating a generic project model that can be used in any hdl
+development flow regardless of project structure and EDA tool requirements.
+
+The plugin based architecture allows for SimplHDL to be migrated into any existing project, replacing ad-hoc simulation
+and implementation scripts while providing a intuitive command-line interface for HDL design and verification engineers.
+
+I wide vararity of languages, standards and tools are supported.
+
+### HDL languages
+
+- Verilog / System Verilog
+- VHDL
+- Chisel
+- SystemRDL
+- IPXact
+- Vivado IP containers (.xci, .xcix)
+- Quartus IP containers (.ip)
+
+### Methodologies
+
+- UVM
+- OSVMM
+- UVVM
+- Cocotb
+- pyuvm
+
+### EDA Tools
+
+- Vivado
+- Quartus
+- Modelsim
+- Questasim
+- Xsim
+- Vcs
+- Riviera Pro
+- Xcelium (coming)
+- Verilator (coming)
+- Icarus (coming)
+- GHDL (coming)
+
+## Getting Started
+
+SimplHDL currently works on Linux and Windows WSL. It is written in Python and can be installed with _pip_. To run
+SimplHDL Python 3.8 or later is required. The tools for the flows you wish to run also need to be installed and set up
+correctly in the shell environment. SimplHDL can be installed on your system's Python installation, but it is highly
+recommended to install and run SimplHDL in a Python virtual environment or a Conda environment.
+
+## Example
+
+To quickly try out SimplHDL follow these steps. In this example, we will use Vivado and QuestaSim. The prerequisites are
+that SimplHDL install installed and Vivado and QuestaSim are correctly set up in your shell environment.
+
+1. Clone Git repository from GitHub
+
+```console
+git clone https://github.com/SimplHDL/simplhdl.git
+```
+
+2. install SimplHDL from source
+
+```console
+pip install ./simplhdl
+```
+
+3. Run simulation
+
+```console
+cd simplhdl/examples/hdl/alu/sim
+simpl questasim
+```
+
+4. Run simulation interactively in Gui.
+
+```console
+cd simplhdl/examples/hdl/alu/sim
+simpl questasim --gui
+```
+
+5. Run implementation
+
+```console
+cd ../syn
+simpl vivado
+```
+
+6. Run implementation interactively in Gui.
+
+```console
+simpl vivado --gui
+```
+
+In this example, the project specification is written in Yaml. This format is only meant as a demonstration. To
+integrate SimplHDL into your project, you have to write a parser plugin for your specific project specification format.
+See the documentation and plugin examples for more information.
+
+## Links
+
+- Homepage:
+- Source: <https://github.com/SimplHDL/simplhdl>
+- Tracker: <https://github.com/SimplHDL/simplhdl/issues>

simplhdl-0.10.1/pyproject.toml

@@ -0,0 +1,128 @@
+[build-system]
+build-backend = "setuptools.build_meta"
+requires = [
+  "setuptools>=64",
+  "wheel",
+]
+
+[project]
+name = "simplhdl"
+description = "A framework for simulating and implementing HDL designs"
+readme = "README.md"
+license = { file = "LICENSE" }
+maintainers = [
+  { name = "Rasmus Grøndahl Olsen", email = "simplhdl@gmail.com" },
+]
+authors = [
+  { name = "Rasmus Grøndahl Olsen", email = "simplhdl@gmail.com" },
+]
+requires-python = ">=3.8"
+classifiers = [
+  "Development Status :: 4 - Beta",
+  "Intended Audience :: Developers",
+  "License :: OSI Approved :: MIT License",
+  "Operating System :: OS Independent",
+  "Programming Language :: Python :: 3 :: Only",
+  "Programming Language :: Python :: 3.8",
+  "Programming Language :: Python :: 3.9",
+  "Programming Language :: Python :: 3.10",
+  "Programming Language :: Python :: 3.11",
+  "Programming Language :: Python :: 3.12",
+  "Programming Language :: Python :: 3.13",
+  "Programming Language :: Python :: 3.14",
+]
+
+dynamic = [ "version" ]
+dependencies = [
+  "argcomplete",
+  "black",
+  "flake8",
+  "gitpython",
+  "importlib-resources; python_version<'3.9'",
+  "jinja2",
+  "matplotlib",
+  "networkx",
+  "peakrdl-html",
+  "peakrdl-pyuvm",
+  "peakrdl-regblock>=1.2",
+  "pyyaml",
+  "rich",
+  "singleton-decorator",
+  "systemrdl-compiler",
+  "types-pyyaml",
+  "vsg",
+]
+
+optional-dependencies.dev = [
+  "flake8",
+  "mypy",
+  "robotframework",
+  "tox",
+]
+optional-dependencies.docs = [
+  "furo",
+  "sphinx",
+  "sphinx-pyproject",
+]
+urls.Documentation = "https://simplhdl.readthedocs.io/en/latest/"
+urls.Homepage = "https://github.com/SimplHDL"
+urls.Issues = "https://github.com/SimplHDL/simplhdl/issues"
+urls.Repository = "https://github.com/SimplHDL/simplhdl.git"
+scripts.simpl = "simplhdl.__main__:main"
+entry-points."simplhdl.plugins".chisel_generator = "simplhdl_chisel.chisel:ChiselGenerator"
+entry-points."simplhdl.plugins".encrypt = "simplhdl_encrypt.encrypt.encryptflow:EncryptFlow"
+entry-points."simplhdl.plugins".fusersoc_parser = "simplhdl_fusesocparser.fusesocparser:FuseSocParser"
+entry-points."simplhdl.plugins".lint = "simplhdl_lint.lint.lintflow:LintFlow"
+entry-points."simplhdl.plugins".modelsim = "simplhdl_modelsim.modelsim.modelsimflow:ModelSimFlow"
+entry-points."simplhdl.plugins".peakrdl_generator = "simplhdl_peakrdl.systemrdl:PeakRdlGenerator"
+entry-points."simplhdl.plugins".quartus = "simplhdl_quartus.quartusflow:QuartusFlow"
+entry-points."simplhdl.plugins".quartus-dse = "simplhdl_quartus.quartusdse.quartusdseflow:QuartusDseFlow"
+entry-points."simplhdl.plugins".quartus-export = "simplhdl_quartus.quartusexport.quartusexportflow:QuartusExportFlow"
+entry-points."simplhdl.plugins".quartus_generator = "simplhdl_quartus.spd:QuartusGenerator"
+entry-points."simplhdl.plugins".questasim = "simplhdl_questasim.questasim.questasimflow:QuestaSimFlow"
+entry-points."simplhdl.plugins".rivierapro = "simplhdl_rivierapro.rivierapro.rivieraproflow:RivieraProFlow"
+entry-points."simplhdl.plugins".simplhdl_parser = "simplhdl_parser.simplhdlparser:SimplHdlParser"
+entry-points."simplhdl.plugins".vcs = "simplhdl_vcs.vcs.vcsflow:VcsFlow"
+entry-points."simplhdl.plugins".vivado = "simplhdl_vivado.vivadoflow:VivadoFlow"
+entry-points."simplhdl.plugins".vivado_generator = "simplhdl_vivado.ipxact:VivadoGenerator"
+entry-points."simplhdl.plugins".xsim = "simplhdl_vivado.xsim.xsimflow:XsimFlow"
+
+[tool.setuptools.dynamic]
+version = { attr = "simplhdl.__version__" }
+
+[tool.setuptools.package-data]
+"*" = [ "*.j2" ]
+
+[tool.ruff]
+line-length = 120
+fix = true
+lint.per-file-ignores."__init__.py" = [
+  "F401", # don't care about unused imports
+  "F403", # don't care about 'from module import *'
+]
+lint.isort = { known-first-party = [
+  "simplhdl",
+  "simplhdl_chisel",
+  "simplhdl_encrypt",
+  "simplhdl_fusesocparser",
+  "simplhdl_lint",
+  "simplhdl_modelsim",
+  "simplhdl_parser",
+  "simplhdl_peakrdl",
+  "simplhdl_quartus",
+  "simplhdl_questasim",
+  "simplhdl_rivierapro",
+  "simplhdl_vcs",
+  "simplhdl_vivado",
+  "tests",
+], required-imports = [
+  "from __future__ import annotations",
+] }
+lint.preview = true
+
+[tool.codespell]
+ignore-words-list = "synopsys, edn"
+
+[[tool.mypy.overrides]]
+module = "networkx.*"
+ignore_missing_imports = true

simplhdl-0.10.1/src/simplhdl/__init__.py

@@ -0,0 +1,6 @@
+__version__ = "0.10.1"
+
+from .__main__ import parse_arguments
+from .project.project import *
+from .project.fileset import *
+from .project.design import *

simplhdl-0.10.1/src/simplhdl/__main__.py

@@ -0,0 +1,52 @@
+import logging
+import sys
+import traceback
+
+from rich.logging import RichHandler
+
+from .cli.arguments import parse_arguments
+from .project.project import ProjectError
+from .plugin.flow import FlowError
+from .plugin.generator import GeneratorError
+from .plugin.loader import load_plugins
+from .plugin.parser import ParserError
+from .simplhdl import Simplhdl
+from .utils import CalledShError
+
+logger = logging.getLogger(__name__)
+
+
+def main():
+    try:
+        load_plugins()
+        args = parse_arguments()
+        levels = [logging.INFO, logging.DEBUG, logging.NOTSET]
+        level = levels[min(args.verbose, len(levels) - 1)]
+        if level < logging.INFO:
+            show_path = True
+        else:
+            show_path = False
+
+        FORMAT = "[simplhdl.%(module)s] - %(message)s"
+        console = RichHandler(level=level, show_time=False, rich_tracebacks=True, show_path=show_path)
+        logging.basicConfig(level=5, format=FORMAT, handlers=[console])
+        simpl = Simplhdl(args)
+        simpl.run()
+    except (
+        NotImplementedError,
+        FileNotFoundError,
+        CalledShError,
+        ParserError,
+        FlowError,
+        GeneratorError,
+        ProjectError,
+    ) as e:
+        logger.debug(traceback.format_exc())
+        logger.error(e)
+        return 1
+    except SystemError:
+        return 1
+
+
+if __name__ == "__main__":
+    sys.exit(main())

simplhdl-0.10.1/src/simplhdl/cli/arguments.py

@@ -0,0 +1,38 @@
+from __future__ import annotations
+
+import argparse
+from pathlib import Path
+from typing import Sequence
+
+import argcomplete
+
+from .. import __version__
+from ..plugin.flow import FlowFactory
+
+
+def parse_arguments(args: Sequence[str] = None, namespace: None = None) -> argparse.Namespace:
+    parser = argparse.ArgumentParser(
+        prog="simpl",
+        description="Simple framework for simulation and implementation of HDL designs",
+    )
+    parser.add_argument("--projectspec", type=Path, help="Project specification file")
+    parser.add_argument("--version", action="version", version=f"SimplHDL version {__version__}")
+    parser.add_argument("-v", "--verbose", action="count", default=0, help="Increase verbosity")
+    parser.add_argument(
+        "-o",
+        "--outputdir",
+        default="_build",
+        type=Path,
+        help="output directory for build files",
+    )
+    subparsers = parser.add_subparsers(
+        title="Flows",
+        description="""Different work flows for simulation and implementation
+                       of HDL designs""",
+        dest="flow",
+    )
+    for flow_class in FlowFactory.get_flows().values():
+        flow_class.parse_args(subparsers)
+
+    argcomplete.autocomplete(parser)
+    return parser.parse_args(args=args, namespace=namespace)