SimplHDL 0.7.0__tar.gz → 0.7.1__tar.gz
This diff represents the content of publicly available package versions that have been released to one of the supported registries. The information contained in this diff is provided for informational purposes only and reflects changes between package versions as they appear in their respective public registries.
- {simplhdl-0.7.0 → simplhdl-0.7.1}/PKG-INFO +3 -2
- {simplhdl-0.7.0 → simplhdl-0.7.1}/pyproject.toml +2 -1
- {simplhdl-0.7.0 → simplhdl-0.7.1}/src/SimplHDL.egg-info/PKG-INFO +3 -2
- {simplhdl-0.7.0 → simplhdl-0.7.1}/src/SimplHDL.egg-info/requires.txt +1 -1
- simplhdl-0.7.1/src/simplhdl/__init__.py +1 -0
- {simplhdl-0.7.0 → simplhdl-0.7.1}/src/simplhdl/generators/systemrdl.py +26 -8
- {simplhdl-0.7.0 → simplhdl-0.7.1}/src/simplhdl/resources/templates/vcs/cocotb.mk.j2 +3 -1
- simplhdl-0.7.0/src/simplhdl/__init__.py +0 -1
- {simplhdl-0.7.0 → simplhdl-0.7.1}/.github/workflows/publish.yml +0 -0
- {simplhdl-0.7.0 → simplhdl-0.7.1}/.gitignore +0 -0
- {simplhdl-0.7.0 → simplhdl-0.7.1}/.readthedocs.yaml +0 -0
- {simplhdl-0.7.0 → simplhdl-0.7.1}/LICENSE +0 -0
- {simplhdl-0.7.0 → simplhdl-0.7.1}/README.md +0 -0
- {simplhdl-0.7.0 → simplhdl-0.7.1}/docs/_static/simplhdl_dark.png +0 -0
- {simplhdl-0.7.0 → simplhdl-0.7.1}/docs/_static/simplhdl_light.png +0 -0
- {simplhdl-0.7.0 → simplhdl-0.7.1}/docs/_static/simplhdl_light_1.png +0 -0
- {simplhdl-0.7.0 → simplhdl-0.7.1}/docs/conf.py +0 -0
- {simplhdl-0.7.0 → simplhdl-0.7.1}/docs/drawing.svg +0 -0
- {simplhdl-0.7.0 → simplhdl-0.7.1}/docs/flows/ghdl.rst +0 -0
- {simplhdl-0.7.0 → simplhdl-0.7.1}/docs/flows/icarus.rst +0 -0
- {simplhdl-0.7.0 → simplhdl-0.7.1}/docs/flows/quartus.rst +0 -0
- {simplhdl-0.7.0 → simplhdl-0.7.1}/docs/flows/questasim.rst +0 -0
- {simplhdl-0.7.0 → simplhdl-0.7.1}/docs/flows/vcs.rst +0 -0
- {simplhdl-0.7.0 → simplhdl-0.7.1}/docs/flows/vivado.rst +0 -0
- {simplhdl-0.7.0 → simplhdl-0.7.1}/docs/flows/xsim.rst +0 -0
- {simplhdl-0.7.0 → simplhdl-0.7.1}/docs/flows.rst +0 -0
- {simplhdl-0.7.0 → simplhdl-0.7.1}/docs/index.rst +0 -0
- {simplhdl-0.7.0 → simplhdl-0.7.1}/docs/intel-ips.md +0 -0
- {simplhdl-0.7.0 → simplhdl-0.7.1}/docs/introduction.rst +0 -0
- {simplhdl-0.7.0 → simplhdl-0.7.1}/docs/plugins.rst +0 -0
- {simplhdl-0.7.0 → simplhdl-0.7.1}/docs/requirements.txt +0 -0
- {simplhdl-0.7.0 → simplhdl-0.7.1}/examples/hdl/adder/adder.yml +0 -0
- {simplhdl-0.7.0 → simplhdl-0.7.1}/examples/hdl/adder/hdl/adder.sv +0 -0
- {simplhdl-0.7.0 → simplhdl-0.7.1}/examples/hdl/adder/sim/testbench.sv +0 -0
- {simplhdl-0.7.0 → simplhdl-0.7.1}/examples/hdl/adder/sim/testbench.yml +0 -0
- {simplhdl-0.7.0 → simplhdl-0.7.1}/examples/hdl/adder/syn/build.yml +0 -0
- {simplhdl-0.7.0 → simplhdl-0.7.1}/examples/hdl/adder/syn/placement.xdc +0 -0
- {simplhdl-0.7.0 → simplhdl-0.7.1}/examples/hdl/adder/syn/timing.xdc +0 -0
- {simplhdl-0.7.0 → simplhdl-0.7.1}/examples/hdl/adder/syn/top.sv +0 -0
- {simplhdl-0.7.0 → simplhdl-0.7.1}/examples/hdl/alu/alu.yml +0 -0
- {simplhdl-0.7.0 → simplhdl-0.7.1}/examples/hdl/alu/hdl/add.sv +0 -0
- {simplhdl-0.7.0 → simplhdl-0.7.1}/examples/hdl/alu/hdl/alu.sv +0 -0
- {simplhdl-0.7.0 → simplhdl-0.7.1}/examples/hdl/alu/hdl/mul.sv +0 -0
- {simplhdl-0.7.0 → simplhdl-0.7.1}/examples/hdl/alu/hdl/sub.sv +0 -0
- {simplhdl-0.7.0 → simplhdl-0.7.1}/examples/hdl/alu/sim/pyuvm/alu_vip/__init__.py +0 -0
- {simplhdl-0.7.0 → simplhdl-0.7.1}/examples/hdl/alu/sim/pyuvm/alu_vip/agent.py +0 -0
- {simplhdl-0.7.0 → simplhdl-0.7.1}/examples/hdl/alu/sim/pyuvm/alu_vip/aluif.py +0 -0
- {simplhdl-0.7.0 → simplhdl-0.7.1}/examples/hdl/alu/sim/pyuvm/alu_vip/driver.py +0 -0
- {simplhdl-0.7.0 → simplhdl-0.7.1}/examples/hdl/alu/sim/pyuvm/alu_vip/monitor.py +0 -0
- {simplhdl-0.7.0 → simplhdl-0.7.1}/examples/hdl/alu/sim/pyuvm/alu_vip/sequenceitem.py +0 -0
- {simplhdl-0.7.0 → simplhdl-0.7.1}/examples/hdl/alu/sim/pyuvm/alu_vip/sequencer.py +0 -0
- {simplhdl-0.7.0 → simplhdl-0.7.1}/examples/hdl/alu/sim/pyuvm/clock_vip/__init__.py +0 -0
- {simplhdl-0.7.0 → simplhdl-0.7.1}/examples/hdl/alu/sim/pyuvm/clock_vip/agent.py +0 -0
- {simplhdl-0.7.0 → simplhdl-0.7.1}/examples/hdl/alu/sim/pyuvm/clock_vip/clockif.py +0 -0
- {simplhdl-0.7.0 → simplhdl-0.7.1}/examples/hdl/alu/sim/pyuvm/pyuvm.yml +0 -0
- {simplhdl-0.7.0 → simplhdl-0.7.1}/examples/hdl/alu/sim/pyuvm/test/__init__.py +0 -0
- {simplhdl-0.7.0 → simplhdl-0.7.1}/examples/hdl/alu/sim/pyuvm/test/env.py +0 -0
- {simplhdl-0.7.0 → simplhdl-0.7.1}/examples/hdl/alu/sim/pyuvm/test/seq_lib.py +0 -0
- {simplhdl-0.7.0 → simplhdl-0.7.1}/examples/hdl/alu/sim/pyuvm/test/test.py +0 -0
- {simplhdl-0.7.0 → simplhdl-0.7.1}/examples/hdl/alu/sim/pyuvm/testbench.py +0 -0
- {simplhdl-0.7.0 → simplhdl-0.7.1}/examples/hdl/alu/sim/uvm/alu_vip/agent.svh +0 -0
- {simplhdl-0.7.0 → simplhdl-0.7.1}/examples/hdl/alu/sim/uvm/alu_vip/alu_vip.sv +0 -0
- {simplhdl-0.7.0 → simplhdl-0.7.1}/examples/hdl/alu/sim/uvm/alu_vip/alu_vip.yml +0 -0
- {simplhdl-0.7.0 → simplhdl-0.7.1}/examples/hdl/alu/sim/uvm/alu_vip/driver.svh +0 -0
- {simplhdl-0.7.0 → simplhdl-0.7.1}/examples/hdl/alu/sim/uvm/alu_vip/env.svh +0 -0
- {simplhdl-0.7.0 → simplhdl-0.7.1}/examples/hdl/alu/sim/uvm/alu_vip/monitor.svh +0 -0
- {simplhdl-0.7.0 → simplhdl-0.7.1}/examples/hdl/alu/sim/uvm/alu_vip/sequence_item.svh +0 -0
- {simplhdl-0.7.0 → simplhdl-0.7.1}/examples/hdl/alu/sim/uvm/tb_env/seq_lib/add_seq.svh +0 -0
- {simplhdl-0.7.0 → simplhdl-0.7.1}/examples/hdl/alu/sim/uvm/tb_env/seq_lib/base_seq.svh +0 -0
- {simplhdl-0.7.0 → simplhdl-0.7.1}/examples/hdl/alu/sim/uvm/tb_env/tb_env.sv +0 -0
- {simplhdl-0.7.0 → simplhdl-0.7.1}/examples/hdl/alu/sim/uvm/tb_env/tb_env.yml +0 -0
- {simplhdl-0.7.0 → simplhdl-0.7.1}/examples/hdl/alu/sim/uvm/tb_env/test/base_test.svh +0 -0
- {simplhdl-0.7.0 → simplhdl-0.7.1}/examples/hdl/alu/sim/uvm/tb_env/test/test_add.svh +0 -0
- {simplhdl-0.7.0 → simplhdl-0.7.1}/examples/hdl/alu/sim/uvm/testbench/alu_if.sv +0 -0
- {simplhdl-0.7.0 → simplhdl-0.7.1}/examples/hdl/alu/sim/uvm/testbench/testbench.sv +0 -0
- {simplhdl-0.7.0 → simplhdl-0.7.1}/examples/hdl/alu/sim/uvm/testbench/testbench.yml +0 -0
- {simplhdl-0.7.0 → simplhdl-0.7.1}/examples/hdl/alu/sim/uvm/testcases/test_add/test_add.yml +0 -0
- {simplhdl-0.7.0 → simplhdl-0.7.1}/examples/hdl/alu/syn/build.yml +0 -0
- {simplhdl-0.7.0 → simplhdl-0.7.1}/examples/hdl/alu/syn/placement.xdc +0 -0
- {simplhdl-0.7.0 → simplhdl-0.7.1}/examples/hdl/alu/syn/timing.xdc +0 -0
- {simplhdl-0.7.0 → simplhdl-0.7.1}/examples/hdl/hello/build.sbt +0 -0
- {simplhdl-0.7.0 → simplhdl-0.7.1}/examples/hdl/hello/hello.yml +0 -0
- {simplhdl-0.7.0 → simplhdl-0.7.1}/examples/hdl/hello/src/main/scala/Hello.scala +0 -0
- {simplhdl-0.7.0 → simplhdl-0.7.1}/examples/hdl/hello/syn/build.yml +0 -0
- {simplhdl-0.7.0 → simplhdl-0.7.1}/examples/plugins/simple_parser/setup.py +0 -0
- {simplhdl-0.7.0 → simplhdl-0.7.1}/examples/plugins/simple_parser/src/simple_parser/__init__.py +0 -0
- {simplhdl-0.7.0 → simplhdl-0.7.1}/examples/plugins/simple_parser/src/simple_parser/simple_parser.py +0 -0
- {simplhdl-0.7.0 → simplhdl-0.7.1}/setup.cfg +0 -0
- {simplhdl-0.7.0 → simplhdl-0.7.1}/src/SimplHDL.egg-info/SOURCES.txt +0 -0
- {simplhdl-0.7.0 → simplhdl-0.7.1}/src/SimplHDL.egg-info/dependency_links.txt +0 -0
- {simplhdl-0.7.0 → simplhdl-0.7.1}/src/SimplHDL.egg-info/entry_points.txt +0 -0
- {simplhdl-0.7.0 → simplhdl-0.7.1}/src/SimplHDL.egg-info/top_level.txt +0 -0
- {simplhdl-0.7.0 → simplhdl-0.7.1}/src/simplhdl/__main__.py +0 -0
- {simplhdl-0.7.0 → simplhdl-0.7.1}/src/simplhdl/cocotb.py +0 -0
- {simplhdl-0.7.0 → simplhdl-0.7.1}/src/simplhdl/flow.py +0 -0
- {simplhdl-0.7.0 → simplhdl-0.7.1}/src/simplhdl/flows/__init__.py +0 -0
- {simplhdl-0.7.0 → simplhdl-0.7.1}/src/simplhdl/flows/encrypt/__init__.py +0 -0
- {simplhdl-0.7.0 → simplhdl-0.7.1}/src/simplhdl/flows/encrypt/encryptflow.py +0 -0
- {simplhdl-0.7.0 → simplhdl-0.7.1}/src/simplhdl/flows/flake8/flake8flow.py +0 -0
- {simplhdl-0.7.0 → simplhdl-0.7.1}/src/simplhdl/flows/implementationflow.py +0 -0
- {simplhdl-0.7.0 → simplhdl-0.7.1}/src/simplhdl/flows/lint/lintflow.py +0 -0
- {simplhdl-0.7.0 → simplhdl-0.7.1}/src/simplhdl/flows/modelsim/__init__.py +0 -0
- {simplhdl-0.7.0 → simplhdl-0.7.1}/src/simplhdl/flows/modelsim/modelsimflow.py +0 -0
- {simplhdl-0.7.0 → simplhdl-0.7.1}/src/simplhdl/flows/quartusdse/__init__.py +0 -0
- {simplhdl-0.7.0 → simplhdl-0.7.1}/src/simplhdl/flows/quartusdse/quartusdseflow.py +0 -0
- {simplhdl-0.7.0 → simplhdl-0.7.1}/src/simplhdl/flows/quartusexport/__init__.py +0 -0
- {simplhdl-0.7.0 → simplhdl-0.7.1}/src/simplhdl/flows/quartusexport/quartusexportflow.py +0 -0
- {simplhdl-0.7.0 → simplhdl-0.7.1}/src/simplhdl/flows/quartusflow.py +0 -0
- {simplhdl-0.7.0 → simplhdl-0.7.1}/src/simplhdl/flows/questasim/__init__.py +0 -0
- {simplhdl-0.7.0 → simplhdl-0.7.1}/src/simplhdl/flows/questasim/questasimflow.py +0 -0
- {simplhdl-0.7.0 → simplhdl-0.7.1}/src/simplhdl/flows/rivierapro/__init__.py +0 -0
- {simplhdl-0.7.0 → simplhdl-0.7.1}/src/simplhdl/flows/rivierapro/rivieraproflow.py +0 -0
- {simplhdl-0.7.0 → simplhdl-0.7.1}/src/simplhdl/flows/simulationflow.py +0 -0
- {simplhdl-0.7.0 → simplhdl-0.7.1}/src/simplhdl/flows/vcs/__init__.py +0 -0
- {simplhdl-0.7.0 → simplhdl-0.7.1}/src/simplhdl/flows/vcs/vcsflow.py +0 -0
- {simplhdl-0.7.0 → simplhdl-0.7.1}/src/simplhdl/flows/verible/__init__.py +0 -0
- {simplhdl-0.7.0 → simplhdl-0.7.1}/src/simplhdl/flows/verible/veribleflow.py +0 -0
- {simplhdl-0.7.0 → simplhdl-0.7.1}/src/simplhdl/flows/vivadoflow.py +0 -0
- {simplhdl-0.7.0 → simplhdl-0.7.1}/src/simplhdl/flows/vsg/__init__.py +0 -0
- {simplhdl-0.7.0 → simplhdl-0.7.1}/src/simplhdl/flows/vsg/vsgflow.py +0 -0
- {simplhdl-0.7.0 → simplhdl-0.7.1}/src/simplhdl/flows/xsim/__init__.py +0 -0
- {simplhdl-0.7.0 → simplhdl-0.7.1}/src/simplhdl/flows/xsim/xsimflow.py +0 -0
- {simplhdl-0.7.0 → simplhdl-0.7.1}/src/simplhdl/generator.py +0 -0
- {simplhdl-0.7.0 → simplhdl-0.7.1}/src/simplhdl/generators/__init__.py +0 -0
- {simplhdl-0.7.0 → simplhdl-0.7.1}/src/simplhdl/generators/chisel.py +0 -0
- {simplhdl-0.7.0 → simplhdl-0.7.1}/src/simplhdl/generators/ipxact.py +0 -0
- {simplhdl-0.7.0 → simplhdl-0.7.1}/src/simplhdl/generators/spd.py +0 -0
- {simplhdl-0.7.0 → simplhdl-0.7.1}/src/simplhdl/info.py +0 -0
- {simplhdl-0.7.0 → simplhdl-0.7.1}/src/simplhdl/parser.py +0 -0
- {simplhdl-0.7.0 → simplhdl-0.7.1}/src/simplhdl/parsers/__init__.py +0 -0
- {simplhdl-0.7.0 → simplhdl-0.7.1}/src/simplhdl/parsers/fusesocparser.py +0 -0
- {simplhdl-0.7.0 → simplhdl-0.7.1}/src/simplhdl/parsers/simplhdlparser.py +0 -0
- {simplhdl-0.7.0 → simplhdl-0.7.1}/src/simplhdl/plugins.py +0 -0
- {simplhdl-0.7.0 → simplhdl-0.7.1}/src/simplhdl/pyedaa/__init__.py +0 -0
- {simplhdl-0.7.0 → simplhdl-0.7.1}/src/simplhdl/pyedaa/attributes.py +0 -0
- {simplhdl-0.7.0 → simplhdl-0.7.1}/src/simplhdl/pyedaa/design.py +0 -0
- {simplhdl-0.7.0 → simplhdl-0.7.1}/src/simplhdl/pyedaa/fileset.py +0 -0
- {simplhdl-0.7.0 → simplhdl-0.7.1}/src/simplhdl/pyedaa/filetypes.py +0 -0
- {simplhdl-0.7.0 → simplhdl-0.7.1}/src/simplhdl/pyedaa/project.py +0 -0
- {simplhdl-0.7.0 → simplhdl-0.7.1}/src/simplhdl/pyedaa/target.py +0 -0
- {simplhdl-0.7.0 → simplhdl-0.7.1}/src/simplhdl/pyedaa/vhdllibrary.py +0 -0
- {simplhdl-0.7.0 → simplhdl-0.7.1}/src/simplhdl/repo.py +0 -0
- {simplhdl-0.7.0 → simplhdl-0.7.1}/src/simplhdl/resources/__init__.py +0 -0
- {simplhdl-0.7.0 → simplhdl-0.7.1}/src/simplhdl/resources/templates/__init__.py +0 -0
- {simplhdl-0.7.0 → simplhdl-0.7.1}/src/simplhdl/resources/templates/flake8/__init__.py +0 -0
- {simplhdl-0.7.0 → simplhdl-0.7.1}/src/simplhdl/resources/templates/flake8/setup.cfg.j2 +0 -0
- {simplhdl-0.7.0 → simplhdl-0.7.1}/src/simplhdl/resources/templates/modelsim/Makefile.j2 +0 -0
- {simplhdl-0.7.0 → simplhdl-0.7.1}/src/simplhdl/resources/templates/modelsim/__init__.py +0 -0
- {simplhdl-0.7.0 → simplhdl-0.7.1}/src/simplhdl/resources/templates/modelsim/cocotb.mk.j2 +0 -0
- {simplhdl-0.7.0 → simplhdl-0.7.1}/src/simplhdl/resources/templates/modelsim/dependencies.mk.j2 +0 -0
- {simplhdl-0.7.0 → simplhdl-0.7.1}/src/simplhdl/resources/templates/modelsim/files.j2 +0 -0
- {simplhdl-0.7.0 → simplhdl-0.7.1}/src/simplhdl/resources/templates/modelsim/fileset.j2 +0 -0
- {simplhdl-0.7.0 → simplhdl-0.7.1}/src/simplhdl/resources/templates/modelsim/modelsim.tcl.j2 +0 -0
- {simplhdl-0.7.0 → simplhdl-0.7.1}/src/simplhdl/resources/templates/modelsim/project.mk.j2 +0 -0
- {simplhdl-0.7.0 → simplhdl-0.7.1}/src/simplhdl/resources/templates/modelsim/run.do.j2 +0 -0
- {simplhdl-0.7.0 → simplhdl-0.7.1}/src/simplhdl/resources/templates/quartus/__init__.py +0 -0
- {simplhdl-0.7.0 → simplhdl-0.7.1}/src/simplhdl/resources/templates/quartus/project.tcl.j2 +0 -0
- {simplhdl-0.7.0 → simplhdl-0.7.1}/src/simplhdl/resources/templates/quartus/run.tcl.j2 +0 -0
- {simplhdl-0.7.0 → simplhdl-0.7.1}/src/simplhdl/resources/templates/questasim/__init__.py +0 -0
- {simplhdl-0.7.0 → simplhdl-0.7.1}/src/simplhdl/resources/templates/questasim/modelsim.tcl.j2 +0 -0
- {simplhdl-0.7.0 → simplhdl-0.7.1}/src/simplhdl/resources/templates/questasim/project.qrun.j2 +0 -0
- {simplhdl-0.7.0 → simplhdl-0.7.1}/src/simplhdl/resources/templates/questasim/visualizer.tcl.j2 +0 -0
- {simplhdl-0.7.0 → simplhdl-0.7.1}/src/simplhdl/resources/templates/questasim/vsim-run.do.j2 +0 -0
- {simplhdl-0.7.0 → simplhdl-0.7.1}/src/simplhdl/resources/templates/rivierapro/Makefile.j2 +0 -0
- {simplhdl-0.7.0 → simplhdl-0.7.1}/src/simplhdl/resources/templates/rivierapro/__init__.py +0 -0
- {simplhdl-0.7.0 → simplhdl-0.7.1}/src/simplhdl/resources/templates/rivierapro/cocotb.mk.j2 +0 -0
- {simplhdl-0.7.0 → simplhdl-0.7.1}/src/simplhdl/resources/templates/rivierapro/dependencies.mk.j2 +0 -0
- {simplhdl-0.7.0 → simplhdl-0.7.1}/src/simplhdl/resources/templates/rivierapro/files.j2 +0 -0
- {simplhdl-0.7.0 → simplhdl-0.7.1}/src/simplhdl/resources/templates/rivierapro/fileset.j2 +0 -0
- {simplhdl-0.7.0 → simplhdl-0.7.1}/src/simplhdl/resources/templates/rivierapro/project.mk.j2 +0 -0
- {simplhdl-0.7.0 → simplhdl-0.7.1}/src/simplhdl/resources/templates/vcs/Makefile.j2 +0 -0
- {simplhdl-0.7.0 → simplhdl-0.7.1}/src/simplhdl/resources/templates/vcs/__init__.py +0 -0
- {simplhdl-0.7.0 → simplhdl-0.7.1}/src/simplhdl/resources/templates/vcs/dependencies.mk.j2 +0 -0
- {simplhdl-0.7.0 → simplhdl-0.7.1}/src/simplhdl/resources/templates/vcs/files.j2 +0 -0
- {simplhdl-0.7.0 → simplhdl-0.7.1}/src/simplhdl/resources/templates/vcs/fileset.j2 +0 -0
- {simplhdl-0.7.0 → simplhdl-0.7.1}/src/simplhdl/resources/templates/vcs/pli.tab.j2 +0 -0
- {simplhdl-0.7.0 → simplhdl-0.7.1}/src/simplhdl/resources/templates/vcs/project.mk.j2 +0 -0
- {simplhdl-0.7.0 → simplhdl-0.7.1}/src/simplhdl/resources/templates/vcs/simv-run.do.j2 +0 -0
- {simplhdl-0.7.0 → simplhdl-0.7.1}/src/simplhdl/resources/templates/vcs/synopsys_sim.setup.j2 +0 -0
- {simplhdl-0.7.0 → simplhdl-0.7.1}/src/simplhdl/resources/templates/vcs/vcs.parameters.j2 +0 -0
- {simplhdl-0.7.0 → simplhdl-0.7.1}/src/simplhdl/resources/templates/verible/__init__.py +0 -0
- {simplhdl-0.7.0 → simplhdl-0.7.1}/src/simplhdl/resources/templates/verible/rules.cfg.j2 +0 -0
- {simplhdl-0.7.0 → simplhdl-0.7.1}/src/simplhdl/resources/templates/vivado/__init__.py +0 -0
- {simplhdl-0.7.0 → simplhdl-0.7.1}/src/simplhdl/resources/templates/vivado/launch_run.sh.j2 +0 -0
- {simplhdl-0.7.0 → simplhdl-0.7.1}/src/simplhdl/resources/templates/vivado/project.tcl.j2 +0 -0
- {simplhdl-0.7.0 → simplhdl-0.7.1}/src/simplhdl/resources/templates/vivado/run.tcl.j2 +0 -0
- {simplhdl-0.7.0 → simplhdl-0.7.1}/src/simplhdl/resources/templates/vivado/steps.tcl.j2 +0 -0
- {simplhdl-0.7.0 → simplhdl-0.7.1}/src/simplhdl/resources/templates/vsg/__init__.py +0 -0
- {simplhdl-0.7.0 → simplhdl-0.7.1}/src/simplhdl/resources/templates/vsg/files.json.j2 +0 -0
- {simplhdl-0.7.0 → simplhdl-0.7.1}/src/simplhdl/resources/templates/vsg/rules.yml.j2 +0 -0
- {simplhdl-0.7.0 → simplhdl-0.7.1}/src/simplhdl/resources/templates/xsim/Makefile.j2 +0 -0
- {simplhdl-0.7.0 → simplhdl-0.7.1}/src/simplhdl/resources/templates/xsim/__init__.py +0 -0
- {simplhdl-0.7.0 → simplhdl-0.7.1}/src/simplhdl/resources/templates/xsim/cocotb.mk.j2 +0 -0
- {simplhdl-0.7.0 → simplhdl-0.7.1}/src/simplhdl/resources/templates/xsim/dependencies.mk.j2 +0 -0
- {simplhdl-0.7.0 → simplhdl-0.7.1}/src/simplhdl/resources/templates/xsim/files.j2 +0 -0
- {simplhdl-0.7.0 → simplhdl-0.7.1}/src/simplhdl/resources/templates/xsim/fileset.j2 +0 -0
- {simplhdl-0.7.0 → simplhdl-0.7.1}/src/simplhdl/resources/templates/xsim/project.mk.j2 +0 -0
- {simplhdl-0.7.0 → simplhdl-0.7.1}/src/simplhdl/run.py +0 -0
- {simplhdl-0.7.0 → simplhdl-0.7.1}/src/simplhdl/simplhdl.py +0 -0
- {simplhdl-0.7.0 → simplhdl-0.7.1}/src/simplhdl/tools.py +0 -0
- {simplhdl-0.7.0 → simplhdl-0.7.1}/src/simplhdl/utils.py +0 -0
- {simplhdl-0.7.0 → simplhdl-0.7.1}/tests/test_dummy.py +0 -0
- {simplhdl-0.7.0 → simplhdl-0.7.1}/tox.ini +0 -0
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@@ -1,6 +1,6 @@
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Metadata-Version: 2.4
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Name: SimplHDL
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Version: 0.7.
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Version: 0.7.1
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Summary: A framework for simulating and implementing HDL designs
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Author-email: Rasmus Grøndahl Olsen <simplhdl@gmail.com>
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Maintainer-email: Rasmus Grøndahl Olsen <simplhdl@gmail.com>
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@@ -38,6 +38,7 @@ Classifier: Programming Language :: Python :: 3.10
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Classifier: Programming Language :: Python :: 3.11
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Classifier: Programming Language :: Python :: 3.12
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Classifier: Programming Language :: Python :: 3.13
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Classifier: Programming Language :: Python :: 3.14
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Classifier: Intended Audience :: Developers
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Classifier: License :: OSI Approved :: MIT License
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Classifier: Operating System :: OS Independent
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@@ -58,7 +59,7 @@ Requires-Dist: flake8
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Requires-Dist: systemrdl-compiler
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Requires-Dist: peakrdl-html
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Requires-Dist: peakrdl-regblock>=1.2.0
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@@ -26,7 +26,7 @@ dependencies = [
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"black",
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"systemrdl-compiler",
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"peakrdl-html",
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"peakrdl-regblock",
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"peakrdl-regblock>=1.2.0",
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"peakrdl-pyuvm",
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]
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requires-python = ">=3.8"
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"Programming Language :: Python :: 3.11",
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"Programming Language :: Python :: 3.12",
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"Programming Language :: Python :: 3.13",
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"Programming Language :: Python :: 3.14",
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"Intended Audience :: Developers",
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"License :: OSI Approved :: MIT License",
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"Operating System :: OS Independent",
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@@ -1,6 +1,6 @@
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Metadata-Version: 2.4
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Name: SimplHDL
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-
Version: 0.7.
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+
Version: 0.7.1
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Summary: A framework for simulating and implementing HDL designs
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Author-email: Rasmus Grøndahl Olsen <simplhdl@gmail.com>
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Maintainer-email: Rasmus Grøndahl Olsen <simplhdl@gmail.com>
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@@ -38,6 +38,7 @@ Classifier: Programming Language :: Python :: 3.10
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Classifier: Programming Language :: Python :: 3.11
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Classifier: Programming Language :: Python :: 3.12
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Classifier: Programming Language :: Python :: 3.13
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Classifier: Programming Language :: Python :: 3.14
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Classifier: Intended Audience :: Developers
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Classifier: License :: OSI Approved :: MIT License
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Classifier: Operating System :: OS Independent
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@@ -58,7 +59,7 @@ Requires-Dist: flake8
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Requires-Dist: black
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Requires-Dist: systemrdl-compiler
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Requires-Dist: peakrdl-html
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Requires-Dist: peakrdl-regblock
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Requires-Dist: peakrdl-regblock>=1.2.0
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Requires-Dist: peakrdl-pyuvm
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Dynamic: license-file
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__version__ = "0.7.1"
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import os
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import logging
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import jinja2
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import tomllib
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from typing import List
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from pathlib import Path
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@@ -189,16 +190,17 @@ class SystemRDL(GeneratorBase):
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if outputfile.suffix == '.v':
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fileset.InsertFileAfter(rdlfile, VerilogSourceFile(outputfile))
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def
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+
def peakrdl_regmodel(self, node, outputdir, config) -> None:
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RegblockExporter().export(
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node=node,
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output_dir=str(outputdir.absolute()),
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cpuif_cls=AXI4Lite_Cpuif_flattened,
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module_name=f'{node.type_name}_addrmap',
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package_name=f'{node.type_name}_pkg',
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address_width=32,
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default_reset_activelow=True
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module_name=config.get('module_name', f'{node.type_name}_addrmap'),
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package_name=config.get('package_name', f'{node.type_name}_pkg'),
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address_width=config.get('address_width', 32),
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default_reset_activelow=config.get('default_reset_activelow', True),
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err_if_bad_addr=config.get('err_if_bad_addr', False),
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err_if_bad_rw=config.get('err_if_bad_rw', False)
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)
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modulefile: Path = outputdir.joinpath(f'{node.type_name}_pkg.sv').absolute()
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packetfile: Path = outputdir.joinpath(f'{node.type_name}_addrmap.sv').absolute()
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def run(self, flow: FlowBase):
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rdlfiles = list(self.project.DefaultDesign.DefaultFileSet.Files(fileType=SystemRDLSourceFile))
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output_dir = self.builddir.joinpath('systemrdl')
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config = dict()
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if os.getenv('SIMPLHDL_CONFIG'):
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tomlfile = Path(os.getenv('SIMPLHDL_CONFIG'))
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try:
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with tomlfile.open('rb') as f:
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config = tomllib.load(f)
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except FileNotFoundError:
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raise FileNotFoundError(f"SimplHDL config file set by environment 'SIMPLHDL_CONFIG={tomlfile}' does not exist")
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pearkdl_config = config.get('peakrdl', {})
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html_config = pearkdl_config.get('html', {})
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regblock_config = pearkdl_config.get('regblock', {})
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return
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template = env.find_template('registermap')
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for node in leafnodetypes:
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self.render_template(template=template, node=node, outputdir=sub_dir)
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self.
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self.peakrdl_regmodel(node=node, outputdir=output_dir.joinpath('hdl'), config=regblock_config)
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fileset.InsertFileAfter(rdlfile, CocotbPythonFile(output))
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logger.info("Generate HTML Documentation")
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HTMLExporter().export(
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HTMLExporter().export(
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root,
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output_dir.joinpath('docs'),
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+
skip_not_present=html_config.get('skip_not_present', False),
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)
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@@ -9,6 +9,8 @@ export LIBPYTHON_LOC := $(shell cocotb-config --libpython)
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VCS_FLAGS += +warn=noVPI-CT-NS +vpi -P pli.tab -load $(shell cocotb-config --lib-name-path vpi vcs)
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VCS_FLAGS += -debug_access+r+w+nomemcbk -debug_region+cell+encrypt -debug_acc+pp+f+dmptf
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export PYGPI_PYTHON_BIN := $(shell cocotb-config --python-bin)
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export COCOTB_TEST_MODULES := {{cocotbtop}}
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|
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export COCOTB_TOPLEVEL := {{cocotbdut}}
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export MODULE := {{cocotbtop}}
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export TOPLEVEL := {{cocotbdut}}
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-
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