SimplHDL 0.6.0__tar.gz → 0.7.0__tar.gz

{simplhdl-0.6.0 → simplhdl-0.7.0}/PKG-INFO

@@ -1,6 +1,6 @@
 Metadata-Version: 2.4
 Name: SimplHDL
-Version: 0.6.0
+Version: 0.7.0
 Summary: A framework for simulating and implementing HDL designs
 Author-email: Rasmus Grøndahl Olsen <simplhdl@gmail.com>
 Maintainer-email: Rasmus Grøndahl Olsen <simplhdl@gmail.com>
@@ -58,6 +58,8 @@ Requires-Dist: flake8
 Requires-Dist: black
 Requires-Dist: systemrdl-compiler
 Requires-Dist: peakrdl-html
+Requires-Dist: peakrdl-regblock
+Requires-Dist: peakrdl-pyuvm
 Dynamic: license-file
 
 ## Introduction

{simplhdl-0.6.0 → simplhdl-0.7.0}/pyproject.toml

@@ -26,6 +26,8 @@ dependencies = [
     "black",
     "systemrdl-compiler",
     "peakrdl-html",
+    "peakrdl-regblock",
+    "peakrdl-pyuvm",
 ]
 requires-python = ">=3.8"
 authors = [

{simplhdl-0.6.0 → simplhdl-0.7.0}/src/SimplHDL.egg-info/PKG-INFO

@@ -1,6 +1,6 @@
 Metadata-Version: 2.4
 Name: SimplHDL
-Version: 0.6.0
+Version: 0.7.0
 Summary: A framework for simulating and implementing HDL designs
 Author-email: Rasmus Grøndahl Olsen <simplhdl@gmail.com>
 Maintainer-email: Rasmus Grøndahl Olsen <simplhdl@gmail.com>
@@ -58,6 +58,8 @@ Requires-Dist: flake8
 Requires-Dist: black
 Requires-Dist: systemrdl-compiler
 Requires-Dist: peakrdl-html
+Requires-Dist: peakrdl-regblock
+Requires-Dist: peakrdl-pyuvm
 Dynamic: license-file
 
 ## Introduction

{simplhdl-0.6.0 → simplhdl-0.7.0}/src/SimplHDL.egg-info/requires.txt

@@ -11,6 +11,8 @@ flake8
 black
 systemrdl-compiler
 peakrdl-html
+peakrdl-regblock
+peakrdl-pyuvm
 
 [:python_version < "3.9"]
 importlib-resources

simplhdl-0.7.0/src/simplhdl/__init__.py

@@ -0,0 +1 @@
+__version__ = "0.7.0"

{simplhdl-0.6.0 → simplhdl-0.7.0}/src/simplhdl/cocotb.py

@@ -2,6 +2,8 @@ import logging
 import re
 import os
 
+from packaging.version import Version
+from pkg_resources import get_distribution
 from pathlib import Path
 from typing import Optional, Dict
 
@@ -15,8 +17,9 @@ logger = logging.getLogger(__name__)
 
 class Cocotb:
 
-    def __init__(self, project: Project) -> None:
+    def __init__(self, project: Project, seed: int) -> None:
         self.project = project
+        self.seed = seed
         self.top = self.module()
         self.dut = self.get_dut()
         self.toplevels = self.hdltoplevels()
@@ -36,6 +39,13 @@ class Cocotb:
             raise FileNotFoundError(f"{path}: not found")
         return path
 
+    def pythonbin(self) -> str:
+        output = sh(['cocotb-config', '--python-bin'])
+        path = Path(output)
+        if not path.exists():
+            raise FileNotFoundError(f"{path}: not found")
+        return path
+
     def module(self) -> Optional[str]:
         if not self.enabled:
             return None
@@ -140,9 +150,16 @@ class Cocotb:
             return f'-pli {lib_name_path}'
 
     def env(self) -> Dict[str, str]:
+        cocotb_version = Version(get_distribution('cocotb').version)
         e = os.environ.copy()
-        e['MODULE'] = self.top
-        e['TOPLEVEL'] = self.dut
+        if cocotb_version >= Version('2.0.0'):
+            e['COCOTB_TEST_MODULES'] = self.top
+            e['COCOTB_TOPLEVEL'] = self.dut
+            e['PYGPI_PYTHON_BIN'] = self.pythonbin()
+            e['COCOTB_RANDOM_SEED'] = str(self.seed)
+        else:
+            e['MODULE'] = self.top
+            e['TOPLEVEL'] = self.dut
         e['PYTHONPYCACHEPREFIX'] = './pycache'
         e['LIBPYTHON_LOC'] = self.libpython()
         if self.duttype == VHDLSourceFile:

{simplhdl-0.6.0 → simplhdl-0.7.0}/src/simplhdl/flows/quartusflow.py

@@ -34,7 +34,7 @@ from ..pyedaa import (
     QuartusSourceTCLFile
 )
 from ..pyedaa.project import Project
-from ..pyedaa.attributes import UsedIn
+from ..pyedaa.attributes import UsedIn, Scope
 
 logger = logging.getLogger(__name__)
 
@@ -130,7 +130,8 @@ class QuartusFlow(ImplementationFlow):
             QuartusIniFile=QuartusIniFile,
             MemoryInitFile=MemoryInitFile,
             project=self.project,
-            UsedIn=UsedIn)
+            UsedIn=UsedIn,
+            Scope=Scope)
         template = environment.get_template('run.tcl.j2')
         generate_from_template(template, self.builddir,
                                project=self.project)

{simplhdl-0.6.0 → simplhdl-0.7.0}/src/simplhdl/flows/questasim/questasimflow.py

@@ -362,6 +362,7 @@ class QuestaSimFlow(SimulationFlow):
                 shutil.copy(file.Path.absolute(), self.builddir.absolute())
 
     def generate(self):
+        self.check_external_libraries()
         templatedir = resources_files(self.templates)
         env = Environment(
             loader=FileSystemLoader(templatedir),

{simplhdl-0.6.0 → simplhdl-0.7.0}/src/simplhdl/flows/simulationflow.py

@@ -35,7 +35,7 @@ class SimulationFlow(FlowBase):
         self.hashfile = self.builddir.joinpath('filesets.hash')
 
     def run(self) -> None:
-        self.cocotb = Cocotb(self.project)
+        self.cocotb = Cocotb(self.project, self.args.seed)
         self.validate()
         self.configure()
         self.generate()
@@ -52,8 +52,6 @@ class SimulationFlow(FlowBase):
         os.makedirs(self.builddir, exist_ok=True)
         self.is_tool_setup()
         os.environ['RANDOM_SEED'] = str(self.args.seed)
-        if self.cocotb.enabled:
-            os.environ['MODULE'] = self.cocotb.module()
 
     def get_globals(self) -> Dict[str, Any]:
         incdirs = self.project.DefaultDesign.DefaultFileSet.IncludeDirs(usedin='simulation', isrecursive=True)
@@ -76,7 +74,14 @@ class SimulationFlow(FlowBase):
         globals['isinstance'] = isinstance
         return globals
 
+    def check_external_libraries(self):
+        for library in self.project.DefaultDesign.ExternalVHDLLibraries.values():
+            print(f"{library.Name}: {library.Path}")
+            if not library.Path.exists():
+                raise FlowError(f"External library {library.Name} doesn't exist at {library.Path.absolute()}")
+
     def generate(self):
+        self.check_external_libraries()
         templatedir = resources_files(self.templates)
         env = Environment(
             loader=FileSystemLoader(templatedir),

{simplhdl-0.6.0 → simplhdl-0.7.0}/src/simplhdl/flows/vivadoflow.py

@@ -16,7 +16,7 @@ from ..pyedaa import (VivadoIPSpecificationFile, VerilogIncludeFile, VerilogSour
                       SystemVerilogSourceFile, VHDLSourceFile, ConstraintFile,
                       EDIFNetlistFile, NetlistFile, VivadoBDTclFile, VivadoProjectStepFile)
 from ..pyedaa.project import Project
-from ..pyedaa.attributes import UsedIn
+from ..pyedaa.attributes import UsedIn, Scope
 
 logger = logging.getLogger(__name__)
 
@@ -118,7 +118,8 @@ class VivadoFlow(FlowBase):
                                EDIFNetlistFile=EDIFNetlistFile,
                                NetlistFile=NetlistFile,
                                project=self.project,
-                               UsedIn=UsedIn)
+                               UsedIn=UsedIn,
+                               Scope=Scope)
         template = environment.get_template('run.tcl.j2')
         generate_from_template(template, self.builddir,
                                project=self.project)

{simplhdl-0.6.0 → simplhdl-0.7.0}/src/simplhdl/generators/systemrdl.py

@@ -8,17 +8,25 @@ from systemrdl import RDLCompiler, RDLCompileError, RDLListener, RDLWalker
 from systemrdl.node import AddrmapNode
 from systemrdl.rdltypes import AccessType, OnReadType, OnWriteType
 from peakrdl_html import HTMLExporter
+from peakrdl_regblock.exporter import RegblockExporter
+from peakrdl_regblock.cpuif.axi4lite import AXI4Lite_Cpuif_flattened
+from peakrdl_regblock.udps import ALL_UDPS
+from peakrdl_pyuvm.exporter import PyUVMExporter
 
+from ..pyedaa.fileset import FileSet
 from ..generator import GeneratorFactory, GeneratorBase
-from ..pyedaa import SystemRDLSourceFile, SystemVerilogSourceFile, VerilogSourceFile
-from ..flow import FlowBase
+from ..pyedaa import SystemRDLSourceFile, SystemVerilogSourceFile, VerilogSourceFile, CocotbPythonFile
+from ..flow import FlowBase, FlowCategory
 
 
 logger = logging.getLogger(__name__)
 
-seennodes: List[AddrmapNode] = []
-addrmapnodes: List[AddrmapNode] = []
-hierachymapnodes: List[AddrmapNode] = []
+seennodetypes: List[AddrmapNode] = []
+leafnodetypes: List[AddrmapNode] = []
+hierachynodetypes: List[AddrmapNode] = []
+leafnodes: List[AddrmapNode] = []
+hierachynodes: List[AddrmapNode] = []
+nodes: List[AddrmapNode] = []
 
 
 class Environment(jinja2.Environment):
@@ -33,13 +41,18 @@ class Environment(jinja2.Environment):
 
 class Listener(RDLListener):
     def exit_Addrmap(self, node: AddrmapNode):
-        seen = [n for n in seennodes if n.type_name == node.type_name]
+        nodes.append(node)
+        if is_leaf(node):
+            leafnodes.append(node)
+        else:
+            hierachynodes.append(node)
+        seen = [n for n in seennodetypes if n.type_name == node.type_name]
         if not seen:
-            seennodes.append(node)
-            if AddrmapNode not in [type(c) for c in node.children()]:
-                addrmapnodes.append(node)
+            seennodetypes.append(node)
+            if is_leaf(node):
+                leafnodetypes.append(node)
             else:
-                hierachymapnodes.append(node)
+                hierachynodetypes.append(node)
 
 
 def get_template_dirs() -> List[Path]:
@@ -143,10 +156,27 @@ def get_field_access(field) -> str:  # noqa: C901
         return "NOACCESS"
 
 
+def is_leaf(node):
+    """
+    Check if node is leaf, meaning it has no children address maps
+    """
+    if AddrmapNode not in [type(c) for c in node.children()]:
+        return True
+    else:
+        return False
+
+
+def mask(node):
+    m = ~(node.size - 1) & 0xFFFFFFFF
+    return m
+
+
 @GeneratorFactory.register('SystemRDL')
 class SystemRDL(GeneratorBase):
 
-    def render_template(self, template, node, outputdir) -> Path:
+    def render_template(self, template: jinja2.Template, node, outputdir) -> Path:
+        if not template.filename.endswith('.j2'):
+            return
         context = template.render(node=node)
         outputdir.mkdir(parents=True, exist_ok=True)
         outputfile: Path = outputdir.joinpath(f'{node.type_name}__{Path(template.filename).name[:-3]}').absolute()
@@ -159,6 +189,26 @@ class SystemRDL(GeneratorBase):
         if outputfile.suffix == '.v':
             fileset.InsertFileAfter(rdlfile, VerilogSourceFile(outputfile))
 
+    def peakrdl_template(self, node, outputdir) -> None:
+        RegblockExporter().export(
+            node=node,
+            output_dir=str(outputdir.absolute()),
+            cpuif_cls=AXI4Lite_Cpuif_flattened,
+            module_name=f'{node.type_name}_addrmap',
+            package_name=f'{node.type_name}_pkg',
+            address_width=32,
+            default_reset_activelow=True
+
+        )
+        modulefile: Path = outputdir.joinpath(f'{node.type_name}_pkg.sv').absolute()
+        packetfile: Path = outputdir.joinpath(f'{node.type_name}_addrmap.sv').absolute()
+        rdlfile = self.project.DefaultDesign.GetFile(node.inst.def_src_ref.path)
+        parent_fileset = rdlfile.FileSet
+        fileset = FileSet(name=rdlfile.Path, vhdlLibrary=parent_fileset.VHDLLibrary)
+        fileset.AddFile(SystemVerilogSourceFile(modulefile))
+        fileset.AddFile(SystemVerilogSourceFile(packetfile))
+        parent_fileset.AddFileSet(fileset)
+
     def run(self, flow: FlowBase):
         rdlfiles = list(self.project.DefaultDesign.DefaultFileSet.Files(fileType=SystemRDLSourceFile))
         output_dir = self.builddir.joinpath('systemrdl')
@@ -167,6 +217,10 @@ class SystemRDL(GeneratorBase):
             return
 
         rdlc = RDLCompiler()
+
+        for udp in ALL_UDPS:
+            rdlc.register_udp(udp)
+
         try:
             for rdlfile in rdlfiles:
                 rdlc.compile_file(rdlfile.Path, defines=self.project.Defines)
@@ -188,15 +242,30 @@ class SystemRDL(GeneratorBase):
                 loader=jinja2.FileSystemLoader(templatedir),
                 trim_blocks=True)
             env.globals['hex'] = hex
+            env.globals['len'] = len
             env.globals['get_field_access'] = get_field_access
             env.globals['get_reg_access'] = get_reg_access
+            env.globals['nodes'] = nodes
+            env.globals['leafnodes'] = leafnodes
+            env.globals['hierachynodes'] = hierachynodes
+            env.globals['is_leaf'] = is_leaf
+            env.globals['mask'] = mask
             template = env.find_template('registermap')
-            for node in addrmapnodes:
+            for node in leafnodetypes:
                 self.render_template(template=template, node=node, outputdir=sub_dir)
+                self.peakrdl_template(node=node, outputdir=output_dir.joinpath('hdl'))
 
             template = env.find_template('hierachymap')
-            for node in hierachymapnodes:
+            for node in hierachynodetypes:
                 self.render_template(template=template, node=node, outputdir=sub_dir)
 
+        if flow.category == FlowCategory.SIMULATION:
+            logger.info("Generate PyUVM Register Model")
+            output = output_dir.joinpath('pyuvm', 'ralmodel.py')
+            output.parent.mkdir(parents=True, exist_ok=True)
+            PyUVMExporter().export(root, str(output))
+            fileset = rdlfiles[-1].FileSet
+            fileset.InsertFileAfter(rdlfile, CocotbPythonFile(output))
+
         logger.info("Generate HTML Documentation")
-        _ = HTMLExporter().export(root, output_dir.joinpath('docs'))
+        HTMLExporter().export(root, output_dir.joinpath('docs'))

{simplhdl-0.6.0 → simplhdl-0.7.0}/src/simplhdl/pyedaa/__init__.py

@@ -3,7 +3,7 @@ import pyEDAA.ProjectModel as pm
 from pathlib import Path
 from typing import Optional
 from pyTooling.MetaClasses import ExtendedType
-from .attributes import Encrypt, UsedIn, SIMULATION, IMPLEMENTATION
+from .attributes import Encrypt, UsedIn, SIMULATION, IMPLEMENTATION, Scope
 
 
 class FileMixIn(metaclass=ExtendedType, mixin=True):
@@ -176,6 +176,7 @@ class ConstraintFile(pm.ConstraintFile, FileMixIn):
         super()._registerAttributes()
         FileMixIn._registerAttributes(self)
         self[UsedIn] = {IMPLEMENTATION}
+        self[Scope] = None
 
 
 class QuartusSignalTapFile(File):

{simplhdl-0.6.0 → simplhdl-0.7.0}/src/simplhdl/pyedaa/attributes.py

@@ -14,3 +14,8 @@ class UsedIn(pm.Attribute):
 class Encrypt(pm.Attribute):
     NAME: 'Encrypt'
     VALUE_TYPE: bool
+
+
+class Scope(pm.Attribute):
+    NAME: 'Scope'
+    VALUE_TYPE: str

{simplhdl-0.6.0 → simplhdl-0.7.0}/src/simplhdl/pyedaa/vhdllibrary.py

@@ -1,3 +1,4 @@
+import logging
 import pyEDAA.ProjectModel as pm
 
 from typing import Optional
@@ -5,6 +6,9 @@ from pathlib import Path
 from pyVHDLModel import VHDLVersion  # type: ignore
 
 
+logger = logging.getLogger(__name__)
+
+
 class VHDLLibrary(pm.VHDLLibrary):
 
     _path: Optional[Path]
@@ -18,9 +22,9 @@ class VHDLLibrary(pm.VHDLLibrary):
     ):
         super().__init__(name, project, design, vhdlVersion)
         if path is None:
-            self._path = name
+            self.Path = Path(name)
         else:
-            self._path = path
+            self.Path = path
 
     @property
     def Path(self) -> Optional[Path]:
@@ -28,4 +32,9 @@ class VHDLLibrary(pm.VHDLLibrary):
 
     @Path.setter
     def Path(self, path: Path) -> None:
-        self._path = path
+        if isinstance(path, str):
+            filename, lineno, funcname, info = logger.findCaller(stacklevel=3)
+            logger.debug(f"The VHDL library path is a string in {filename}:{lineno}")
+            self._path = Path(path)
+        else:
+            self._path = path

{simplhdl-0.6.0 → simplhdl-0.7.0}/src/simplhdl/resources/templates/quartus/project.tcl.j2

@@ -25,7 +25,11 @@ set_global_assignment -library {{file.Library}} -name VERILOG_FILE "{{file.Path}
 {% elif file.FileType == VHDLSourceFile %}
 set_global_assignment -library {{file.Library}} -name VHDL_FILE "{{file.Path}}"
 {% elif file.FileType == ConstraintFile %}
+{% if file[Scope] is not none %}
+set_global_assignment -name SDC_ENTITY_FILE "{{file.Path}}" -entity "{{file[Scope]}}"
+{% else %}
 set_global_assignment -name SDC_FILE "{{file.Path}}"
+{% endif %}
 {% elif file.FileType == TCLSourceFile %}
 set_global_assignment -name TCL_SCRIPT_FILE "{{file.Path}}"
 {% elif file.FileType == QuartusSourceTCLFile %}

{simplhdl-0.6.0 → simplhdl-0.7.0}/src/simplhdl/resources/templates/questasim/project.qrun.j2

@@ -11,18 +11,18 @@
 +incdir+{{incdir}}
 {% endfor %}
 {% for library in external_libraries %}
--makelib {{library.Path}}:{{library.Name}} -endlib
+-makelib "{{library.Path}}":{{library.Name}} -endlib
 -reflib {{library.Name}}
 {% endfor %}
 {% for library in libraries %}
 -reflib {{library.Name}}
 {% endfor %}
 {% for fileset in filesets %}
--makelib {{fileset.VHDLLibrary.Name}}:{{fileset.VHDLLibrary.Path}}
+-makelib {{fileset.VHDLLibrary.Name}}:"{{fileset.VHDLLibrary.Path}}"
 {% for file in fileset.GetFiles() %}
 
 {% if isinstance(file, (SystemVerilogSourceFile, VerilogSourceFile, VHDLSourceFile)) and 'simulation' in file[UsedIn] %}
-	{{file.Path}}
+	"{{file.Path}}"
 {% endif %}
 {% endfor %}
 -endlib

{simplhdl-0.6.0 → simplhdl-0.7.0}/src/simplhdl/resources/templates/vivado/project.tcl.j2

@@ -11,12 +11,23 @@ proc source_bd_script {filename} {
     # Fail if bd script return an error code or a non zero value
     if {[catch {source -notrace $filename} err]} {
         return -code 1
-    } elseif {$err != 0} {
+    } elseif {$err != ""} {
         return -code 1
     }
 }
 
 
+proc import_bd_file {filename} {
+    set_msg_config -suppress -id {BD 41-2576}
+    set_msg_config -suppress -id {BD 41-1663}
+    set bd [import_files $filename]
+    # generate_target all $bd
+    # export_ip_user_files -of_objects $bd -no_script -sync -force -quiet
+    # reset_msg_config -suppress -id {BD 41-2576}
+    reset_msg_config -suppress -id {BD 41-1663}
+}
+
+
 proc source_step_script {filename} {
     # NOTE: make get_files fail if not files are found
     set_msg_config -id {Vivado 12-818} -new_severity {ERROR}
@@ -76,6 +87,7 @@ proc add_filesets {} {
 
 
 create_project -force -part {{project.Part}} {{project.Name}} [pwd]
+set_msg_config -suppress -id {Board 49-26}
 add_filesets
 {% if project.Parameters or project.Generics %}
 foreach fileset [get_filesets -filter {FILESET_TYPE =~ *Srcs}] {
@@ -97,9 +109,15 @@ read_verilog "{{file.Path|replace('\\', '/')}}"
 {% elif file.FileType == VHDLSourceFile %}
 read_vhdl -vhdl2008 -library {{file.Library}} "{{file.Path|replace('\\', '/')}}"
 {% elif file.FileType == ConstraintFile %}
+{% if file[Scope] is not none %}
+read_xdc "{{file.Path|replace('\\', '/')}}" -ref "{{file[Scope]}}"
+{% else %}
 read_xdc "{{file.Path|replace('\\', '/')}}"
+{% endif %}
 {% elif file.FileType == VivadoIPSpecificationFile %}
-{% if file.Path.suffix == '.xcix' %}
+{% if file.Path.suffix == '.bd' %}
+import_bd_file "{{file.Path|replace('\\', '/')}}"
+{% elif file.Path.suffix == '.xcix' %}
 read_ip "{{file.Path|replace('\\', '/')}}"
 {% else %}
 import_ip "{{file.Path|replace('\\', '/')}}"
@@ -108,8 +126,6 @@ import_ip "{{file.Path|replace('\\', '/')}}"
 add_files "{{file.Path|replace('\\', '/')}}"
 {% elif file.Path.suffix in ['.edif', '.ngc'] %}
 read_edif "{{file.Path|replace('\\', '/')}}"
-{% elif file.Path.suffix == '.bd' %}
-read_bd "{{file.Path|replace('\\', '/')}}"
 {% elif file.FileType == VivadoBDTclFile %}
 send_msg_id {SimplHDL PRJ-3} {INFO} "Sourcing BD tcl file {{file.Path|replace('\\', '/')}}: this might take some time."
 source_bd_script "{{file.Path|replace('\\', '/')}}"

simplhdl-0.6.0/src/simplhdl/__init__.py

@@ -1 +0,0 @@
-__version__ = "0.6.0"