SimplHDL 0.5.8__tar.gz → 0.7.0__tar.gz

{simplhdl-0.5.8 → simplhdl-0.7.0}/PKG-INFO

@@ -1,6 +1,6 @@
 Metadata-Version: 2.4
 Name: SimplHDL
-Version: 0.5.8
+Version: 0.7.0
 Summary: A framework for simulating and implementing HDL designs
 Author-email: Rasmus Grøndahl Olsen <simplhdl@gmail.com>
 Maintainer-email: Rasmus Grøndahl Olsen <simplhdl@gmail.com>
@@ -56,6 +56,10 @@ Requires-Dist: rich
 Requires-Dist: vsg
 Requires-Dist: flake8
 Requires-Dist: black
+Requires-Dist: systemrdl-compiler
+Requires-Dist: peakrdl-html
+Requires-Dist: peakrdl-regblock
+Requires-Dist: peakrdl-pyuvm
 Dynamic: license-file
 
 ## Introduction

{simplhdl-0.5.8 → simplhdl-0.7.0}/pyproject.toml

@@ -24,6 +24,10 @@ dependencies = [
     "vsg",
     "flake8",
     "black",
+    "systemrdl-compiler",
+    "peakrdl-html",
+    "peakrdl-regblock",
+    "peakrdl-pyuvm",
 ]
 requires-python = ">=3.8"
 authors = [

{simplhdl-0.5.8 → simplhdl-0.7.0}/src/SimplHDL.egg-info/PKG-INFO

@@ -1,6 +1,6 @@
 Metadata-Version: 2.4
 Name: SimplHDL
-Version: 0.5.8
+Version: 0.7.0
 Summary: A framework for simulating and implementing HDL designs
 Author-email: Rasmus Grøndahl Olsen <simplhdl@gmail.com>
 Maintainer-email: Rasmus Grøndahl Olsen <simplhdl@gmail.com>
@@ -56,6 +56,10 @@ Requires-Dist: rich
 Requires-Dist: vsg
 Requires-Dist: flake8
 Requires-Dist: black
+Requires-Dist: systemrdl-compiler
+Requires-Dist: peakrdl-html
+Requires-Dist: peakrdl-regblock
+Requires-Dist: peakrdl-pyuvm
 Dynamic: license-file
 
 ## Introduction

{simplhdl-0.5.8 → simplhdl-0.7.0}/src/SimplHDL.egg-info/SOURCES.txt

@@ -177,6 +177,7 @@ src/simplhdl/resources/templates/vcs/files.j2
 src/simplhdl/resources/templates/vcs/fileset.j2
 src/simplhdl/resources/templates/vcs/pli.tab.j2
 src/simplhdl/resources/templates/vcs/project.mk.j2
+src/simplhdl/resources/templates/vcs/simv-run.do.j2
 src/simplhdl/resources/templates/vcs/synopsys_sim.setup.j2
 src/simplhdl/resources/templates/vcs/vcs.parameters.j2
 src/simplhdl/resources/templates/verible/__init__.py

{simplhdl-0.5.8 → simplhdl-0.7.0}/src/SimplHDL.egg-info/requires.txt

@@ -9,6 +9,10 @@ rich
 vsg
 flake8
 black
+systemrdl-compiler
+peakrdl-html
+peakrdl-regblock
+peakrdl-pyuvm
 
 [:python_version < "3.9"]
 importlib-resources

simplhdl-0.7.0/src/simplhdl/__init__.py

@@ -0,0 +1 @@
+__version__ = "0.7.0"

{simplhdl-0.5.8 → simplhdl-0.7.0}/src/simplhdl/cocotb.py

@@ -2,6 +2,8 @@ import logging
 import re
 import os
 
+from packaging.version import Version
+from pkg_resources import get_distribution
 from pathlib import Path
 from typing import Optional, Dict
 
@@ -15,8 +17,9 @@ logger = logging.getLogger(__name__)
 
 class Cocotb:
 
-    def __init__(self, project: Project) -> None:
+    def __init__(self, project: Project, seed: int) -> None:
         self.project = project
+        self.seed = seed
         self.top = self.module()
         self.dut = self.get_dut()
         self.toplevels = self.hdltoplevels()
@@ -36,6 +39,13 @@ class Cocotb:
             raise FileNotFoundError(f"{path}: not found")
         return path
 
+    def pythonbin(self) -> str:
+        output = sh(['cocotb-config', '--python-bin'])
+        path = Path(output)
+        if not path.exists():
+            raise FileNotFoundError(f"{path}: not found")
+        return path
+
     def module(self) -> Optional[str]:
         if not self.enabled:
             return None
@@ -140,9 +150,16 @@ class Cocotb:
             return f'-pli {lib_name_path}'
 
     def env(self) -> Dict[str, str]:
+        cocotb_version = Version(get_distribution('cocotb').version)
         e = os.environ.copy()
-        e['MODULE'] = self.top
-        e['TOPLEVEL'] = self.dut
+        if cocotb_version >= Version('2.0.0'):
+            e['COCOTB_TEST_MODULES'] = self.top
+            e['COCOTB_TOPLEVEL'] = self.dut
+            e['PYGPI_PYTHON_BIN'] = self.pythonbin()
+            e['COCOTB_RANDOM_SEED'] = str(self.seed)
+        else:
+            e['MODULE'] = self.top
+            e['TOPLEVEL'] = self.dut
         e['PYTHONPYCACHEPREFIX'] = './pycache'
         e['LIBPYTHON_LOC'] = self.libpython()
         if self.duttype == VHDLSourceFile:

{simplhdl-0.5.8 → simplhdl-0.7.0}/src/simplhdl/flows/quartusflow.py

@@ -34,7 +34,7 @@ from ..pyedaa import (
     QuartusSourceTCLFile
 )
 from ..pyedaa.project import Project
-from ..pyedaa.attributes import UsedIn
+from ..pyedaa.attributes import UsedIn, Scope
 
 logger = logging.getLogger(__name__)
 
@@ -130,7 +130,8 @@ class QuartusFlow(ImplementationFlow):
             QuartusIniFile=QuartusIniFile,
             MemoryInitFile=MemoryInitFile,
             project=self.project,
-            UsedIn=UsedIn)
+            UsedIn=UsedIn,
+            Scope=Scope)
         template = environment.get_template('run.tcl.j2')
         generate_from_template(template, self.builddir,
                                project=self.project)

{simplhdl-0.5.8 → simplhdl-0.7.0}/src/simplhdl/flows/questasim/questasimflow.py

@@ -362,6 +362,7 @@ class QuestaSimFlow(SimulationFlow):
                 shutil.copy(file.Path.absolute(), self.builddir.absolute())
 
     def generate(self):
+        self.check_external_libraries()
         templatedir = resources_files(self.templates)
         env = Environment(
             loader=FileSystemLoader(templatedir),

{simplhdl-0.5.8 → simplhdl-0.7.0}/src/simplhdl/flows/simulationflow.py

@@ -35,7 +35,7 @@ class SimulationFlow(FlowBase):
         self.hashfile = self.builddir.joinpath('filesets.hash')
 
     def run(self) -> None:
-        self.cocotb = Cocotb(self.project)
+        self.cocotb = Cocotb(self.project, self.args.seed)
         self.validate()
         self.configure()
         self.generate()
@@ -52,8 +52,6 @@ class SimulationFlow(FlowBase):
         os.makedirs(self.builddir, exist_ok=True)
         self.is_tool_setup()
         os.environ['RANDOM_SEED'] = str(self.args.seed)
-        if self.cocotb.enabled:
-            os.environ['MODULE'] = self.cocotb.module()
 
     def get_globals(self) -> Dict[str, Any]:
         incdirs = self.project.DefaultDesign.DefaultFileSet.IncludeDirs(usedin='simulation', isrecursive=True)
@@ -73,9 +71,17 @@ class SimulationFlow(FlowBase):
         globals['VHDLSourceFile'] = VHDLSourceFile
         globals['UsedIn'] = UsedIn
         globals['uvm'] = self.is_uvm()
+        globals['isinstance'] = isinstance
         return globals
 
+    def check_external_libraries(self):
+        for library in self.project.DefaultDesign.ExternalVHDLLibraries.values():
+            print(f"{library.Name}: {library.Path}")
+            if not library.Path.exists():
+                raise FlowError(f"External library {library.Name} doesn't exist at {library.Path.absolute()}")
+
     def generate(self):
+        self.check_external_libraries()
         templatedir = resources_files(self.templates)
         env = Environment(
             loader=FileSystemLoader(templatedir),

{simplhdl-0.5.8 → simplhdl-0.7.0}/src/simplhdl/flows/vcs/vcsflow.py

@@ -34,9 +34,11 @@ class VcsFlow(SimulationFlow):
         )
         parser.add_argument(
             '-w',
-            '--wave',
-            action='store_true',
-            help="Dump waveforms"
+            '--wavedump',
+            nargs='?',
+            const='vpd',
+            choices=['vpd', 'evcd', 'fsdb'],
+            help="Dump waveforms using vpd, evcd or fsdb format"
         )
         parser.add_argument(
             '--gui',
@@ -92,6 +94,7 @@ class VcsFlow(SimulationFlow):
 
     def get_globals(self) -> Dict[str, Any]:
         globals = super().get_globals()
+        globals['wavedump'] = self.args.wavedump
         globals['vlogan_args'] = self.vlogan_args()
         globals['vhdlan_args'] = self.vhdlan_args()
         globals['vcs_args'] = self.vcs_args()
@@ -124,6 +127,8 @@ class VcsFlow(SimulationFlow):
             environment.get_template('synopsys_sim.setup.j2'),
             environment.get_template('project.mk.j2'),
             environment.get_template('vcs.parameters.j2'),
+            environment.get_template('simv-run.do.j2'),
+
         ]
 
     def get_cocotb_templates(self, environment):
@@ -179,7 +184,7 @@ class VcsFlow(SimulationFlow):
             args.add(f"-timescale={self.args.timescale}")
         if self.is_uvm():
             args.add('-ntb_opts uvm')
-        if self.args.gui:
+        if self.args.gui or self.args.wavedump:
             args.add('-debug_access+all')
             if self.is_verdi():
                 args.add('-kdb')
@@ -195,6 +200,10 @@ class VcsFlow(SimulationFlow):
             args.add(f"+ntb_random_seed={self.args.seed}")
         for name, value in self.project.PlusArgs.items():
             args.add(f"+{name}={escape(value)}")
+        if self.args.wavedump == 'vpd':
+            args.add('-ucli -do simv-run.do')
+        if self.args.wavedump == 'evcd' or self.args.wavedump == 'fsdb':
+            raise NotImplementedError(f"Wavedump for {self.args.wavedump} format is not yet implemented")
         return ' '.join(list(args) + [self.args.simv_args])
 
     def get_library(self, fileset: FileSet) -> str:

{simplhdl-0.5.8 → simplhdl-0.7.0}/src/simplhdl/flows/vivadoflow.py

@@ -16,7 +16,7 @@ from ..pyedaa import (VivadoIPSpecificationFile, VerilogIncludeFile, VerilogSour
                       SystemVerilogSourceFile, VHDLSourceFile, ConstraintFile,
                       EDIFNetlistFile, NetlistFile, VivadoBDTclFile, VivadoProjectStepFile)
 from ..pyedaa.project import Project
-from ..pyedaa.attributes import UsedIn
+from ..pyedaa.attributes import UsedIn, Scope
 
 logger = logging.getLogger(__name__)
 
@@ -118,7 +118,8 @@ class VivadoFlow(FlowBase):
                                EDIFNetlistFile=EDIFNetlistFile,
                                NetlistFile=NetlistFile,
                                project=self.project,
-                               UsedIn=UsedIn)
+                               UsedIn=UsedIn,
+                               Scope=Scope)
         template = environment.get_template('run.tcl.j2')
         generate_from_template(template, self.builddir,
                                project=self.project)

{simplhdl-0.5.8 → simplhdl-0.7.0}/src/simplhdl/generators/ipxact.py

@@ -17,7 +17,7 @@ from ..pyedaa.vhdllibrary import VHDLLibrary
 from ..pyedaa import (
     File, SystemVerilogSourceFile, TCLSourceFile, ConstraintFile, HDLSourceFile,
     VHDLSourceFile, VerilogSourceFile, VivadoIPSpecificationFile,
-    VerilogIncludeFile
+    VerilogIncludeFile, SystemCSourceFile, SystemCHeaderFile
 )
 
 logger = logging.getLogger(__name__)
@@ -40,6 +40,8 @@ FILETYPE_2014_MAP = {
     '.tcl': TCLSourceFile,
     'SDC': ConstraintFile,
     '.sdc': ConstraintFile,
+    'systemCSource': SystemCSourceFile,
+    'systemCSourceInclude': SystemCHeaderFile,
     'unknown': File,
 }
 
@@ -191,7 +193,7 @@ class VivadoIP(GeneratorBase):
                 file = component.filepath(file_element).with_suffix('.xml')
                 if file.exists():
                     files += self.get_files(file)
-        for view in component.views('.*simulation.*'):
+        for view in component.views('.*(verilog|vhdl)simulation.*'):
             filesets = component.filesets(view)
             for fileset in filesets:
                 files += component.pyedaa_files(fileset)
@@ -217,6 +219,9 @@ class VivadoIP(GeneratorBase):
                             i += 1
                             filesets.append(fileset)
                         last_lib = file.Library.Name
-                    fileset.AddFile(file)
+                    try:
+                        fileset.AddFile(file)
+                    except Exception:
+                        logger.warning(f"Failed to add {file.Path}")
                 for fileset in filesets:
                     newipfile.FileSet._fileSets[fileset.Name] = fileset

simplhdl-0.7.0/src/simplhdl/generators/systemrdl.py

@@ -0,0 +1,271 @@
+import os
+import logging
+import jinja2
+
+from typing import List
+from pathlib import Path
+from systemrdl import RDLCompiler, RDLCompileError, RDLListener, RDLWalker
+from systemrdl.node import AddrmapNode
+from systemrdl.rdltypes import AccessType, OnReadType, OnWriteType
+from peakrdl_html import HTMLExporter
+from peakrdl_regblock.exporter import RegblockExporter
+from peakrdl_regblock.cpuif.axi4lite import AXI4Lite_Cpuif_flattened
+from peakrdl_regblock.udps import ALL_UDPS
+from peakrdl_pyuvm.exporter import PyUVMExporter
+
+from ..pyedaa.fileset import FileSet
+from ..generator import GeneratorFactory, GeneratorBase
+from ..pyedaa import SystemRDLSourceFile, SystemVerilogSourceFile, VerilogSourceFile, CocotbPythonFile
+from ..flow import FlowBase, FlowCategory
+
+
+logger = logging.getLogger(__name__)
+
+seennodetypes: List[AddrmapNode] = []
+leafnodetypes: List[AddrmapNode] = []
+hierachynodetypes: List[AddrmapNode] = []
+leafnodes: List[AddrmapNode] = []
+hierachynodes: List[AddrmapNode] = []
+nodes: List[AddrmapNode] = []
+
+
+class Environment(jinja2.Environment):
+    def find_template(self, name):
+        list = [i for i in self.list_templates() if i.startswith(name)]
+        if len(list) == 0:
+            raise jinja2.TemplateNotFound(name)
+        if len(list) > 1:
+            logger.warning(f"Multiple templates found ({list}) for {name}")
+        return self.get_template(list[0])
+
+
+class Listener(RDLListener):
+    def exit_Addrmap(self, node: AddrmapNode):
+        nodes.append(node)
+        if is_leaf(node):
+            leafnodes.append(node)
+        else:
+            hierachynodes.append(node)
+        seen = [n for n in seennodetypes if n.type_name == node.type_name]
+        if not seen:
+            seennodetypes.append(node)
+            if is_leaf(node):
+                leafnodetypes.append(node)
+            else:
+                hierachynodetypes.append(node)
+
+
+def get_template_dirs() -> List[Path]:
+    string = os.getenv('SIMPLHDL_SYSTEMRDL_TEMPLATES')
+    if string:
+        templates = [Path(p) for p in string.split(':')]
+        for t in templates:
+            if not t.is_dir():
+                logger.error(f"Directory {t} does not exist")
+                raise SystemError
+    else:
+        logger.error("SIMPLHDL_SYSTEMRDL_TEMPLATES is not set, no templates found")
+        raise SystemError
+    return templates
+
+
+def get_reg_access(reg) -> str:
+    if reg.has_sw_readable and reg.has_sw_writable:
+        return "RW"
+    elif reg.has_sw_writable:
+        return "WO"
+    elif reg.has_sw_readable:
+        return "RO"
+    else:
+        return "RW"
+
+
+def get_field_access(field) -> str:  # noqa: C901
+    """
+    Get field's UVM access string
+    """
+    sw = field.get_property("sw")
+    onread = field.get_property("onread")
+    onwrite = field.get_property("onwrite")
+
+    if sw == AccessType.rw:
+        if (onwrite is None) and (onread is None):
+            return "RW"
+        elif (onread == OnReadType.rclr) and (onwrite == OnWriteType.woset):
+            return "W1SRC"
+        elif (onread == OnReadType.rclr) and (onwrite == OnWriteType.wzs):
+            return "W0SRC"
+        elif (onread == OnReadType.rclr) and (onwrite == OnWriteType.wset):
+            return "WSRC"
+        elif (onread == OnReadType.rset) and (onwrite == OnWriteType.woclr):
+            return "W1CRS"
+        elif (onread == OnReadType.rset) and (onwrite == OnWriteType.wzc):
+            return "W0CRS"
+        elif (onread == OnReadType.rset) and (onwrite == OnWriteType.wclr):
+            return "WCRS"
+        elif onwrite == OnWriteType.woclr:
+            return "W1C"
+        elif onwrite == OnWriteType.woset:
+            return "W1S"
+        elif onwrite == OnWriteType.wot:
+            return "W1T"
+        elif onwrite == OnWriteType.wzc:
+            return "W0C"
+        elif onwrite == OnWriteType.wzs:
+            return "W0S"
+        elif onwrite == OnWriteType.wzt:
+            return "W0T"
+        elif onwrite == OnWriteType.wclr:
+            return "WC"
+        elif onwrite == OnWriteType.wset:
+            return "WS"
+        elif onread == OnReadType.rclr:
+            return "WRC"
+        elif onread == OnReadType.rset:
+            return "WRS"
+        else:
+            return "RW"
+
+    elif sw == AccessType.r:
+        if onread is None:
+            return "RO"
+        elif onread == OnReadType.rclr:
+            return "RC"
+        elif onread == OnReadType.rset:
+            return "RS"
+        else:
+            return "RO"
+
+    elif sw == AccessType.w:
+        if onwrite is None:
+            return "WO"
+        elif onwrite == OnWriteType.wclr:
+            return "WOC"
+        elif onwrite == OnWriteType.wset:
+            return "WOS"
+        else:
+            return "WO"
+
+    elif sw == AccessType.rw1:
+        return "W1"
+
+    elif sw == AccessType.w1:
+        return "WO1"
+
+    else:
+        return "NOACCESS"
+
+
+def is_leaf(node):
+    """
+    Check if node is leaf, meaning it has no children address maps
+    """
+    if AddrmapNode not in [type(c) for c in node.children()]:
+        return True
+    else:
+        return False
+
+
+def mask(node):
+    m = ~(node.size - 1) & 0xFFFFFFFF
+    return m
+
+
+@GeneratorFactory.register('SystemRDL')
+class SystemRDL(GeneratorBase):
+
+    def render_template(self, template: jinja2.Template, node, outputdir) -> Path:
+        if not template.filename.endswith('.j2'):
+            return
+        context = template.render(node=node)
+        outputdir.mkdir(parents=True, exist_ok=True)
+        outputfile: Path = outputdir.joinpath(f'{node.type_name}__{Path(template.filename).name[:-3]}').absolute()
+        with outputfile.open('w') as f:
+            f.write(context)
+        rdlfile = self.project.DefaultDesign.GetFile(node.inst.def_src_ref.path)
+        fileset = rdlfile.FileSet
+        if outputfile.suffix == '.sv':
+            fileset.InsertFileAfter(rdlfile, SystemVerilogSourceFile(outputfile))
+        if outputfile.suffix == '.v':
+            fileset.InsertFileAfter(rdlfile, VerilogSourceFile(outputfile))
+
+    def peakrdl_template(self, node, outputdir) -> None:
+        RegblockExporter().export(
+            node=node,
+            output_dir=str(outputdir.absolute()),
+            cpuif_cls=AXI4Lite_Cpuif_flattened,
+            module_name=f'{node.type_name}_addrmap',
+            package_name=f'{node.type_name}_pkg',
+            address_width=32,
+            default_reset_activelow=True
+
+        )
+        modulefile: Path = outputdir.joinpath(f'{node.type_name}_pkg.sv').absolute()
+        packetfile: Path = outputdir.joinpath(f'{node.type_name}_addrmap.sv').absolute()
+        rdlfile = self.project.DefaultDesign.GetFile(node.inst.def_src_ref.path)
+        parent_fileset = rdlfile.FileSet
+        fileset = FileSet(name=rdlfile.Path, vhdlLibrary=parent_fileset.VHDLLibrary)
+        fileset.AddFile(SystemVerilogSourceFile(modulefile))
+        fileset.AddFile(SystemVerilogSourceFile(packetfile))
+        parent_fileset.AddFileSet(fileset)
+
+    def run(self, flow: FlowBase):
+        rdlfiles = list(self.project.DefaultDesign.DefaultFileSet.Files(fileType=SystemRDLSourceFile))
+        output_dir = self.builddir.joinpath('systemrdl')
+
+        if not rdlfiles:
+            return
+
+        rdlc = RDLCompiler()
+
+        for udp in ALL_UDPS:
+            rdlc.register_udp(udp)
+
+        try:
+            for rdlfile in rdlfiles:
+                rdlc.compile_file(rdlfile.Path, defines=self.project.Defines)
+                root = rdlc.elaborate()
+        except RDLCompileError as e:
+            logger.error(str(e))
+            raise SystemError
+
+        walker = RDLWalker()
+        walker.walk(root, Listener())
+
+        templatedirs = get_template_dirs()
+
+        for templatedir in templatedirs:
+            logger.info(f"Generate from template {templatedir}")
+            sub_dir = output_dir.joinpath(templatedir.name)
+
+            env = Environment(
+                loader=jinja2.FileSystemLoader(templatedir),
+                trim_blocks=True)
+            env.globals['hex'] = hex
+            env.globals['len'] = len
+            env.globals['get_field_access'] = get_field_access
+            env.globals['get_reg_access'] = get_reg_access
+            env.globals['nodes'] = nodes
+            env.globals['leafnodes'] = leafnodes
+            env.globals['hierachynodes'] = hierachynodes
+            env.globals['is_leaf'] = is_leaf
+            env.globals['mask'] = mask
+            template = env.find_template('registermap')
+            for node in leafnodetypes:
+                self.render_template(template=template, node=node, outputdir=sub_dir)
+                self.peakrdl_template(node=node, outputdir=output_dir.joinpath('hdl'))
+
+            template = env.find_template('hierachymap')
+            for node in hierachynodetypes:
+                self.render_template(template=template, node=node, outputdir=sub_dir)
+
+        if flow.category == FlowCategory.SIMULATION:
+            logger.info("Generate PyUVM Register Model")
+            output = output_dir.joinpath('pyuvm', 'ralmodel.py')
+            output.parent.mkdir(parents=True, exist_ok=True)
+            PyUVMExporter().export(root, str(output))
+            fileset = rdlfiles[-1].FileSet
+            fileset.InsertFileAfter(rdlfile, CocotbPythonFile(output))
+
+        logger.info("Generate HTML Documentation")
+        HTMLExporter().export(root, output_dir.joinpath('docs'))

{simplhdl-0.5.8 → simplhdl-0.7.0}/src/simplhdl/pyedaa/__init__.py

@@ -3,7 +3,7 @@ import pyEDAA.ProjectModel as pm
 from pathlib import Path
 from typing import Optional
 from pyTooling.MetaClasses import ExtendedType
-from .attributes import Encrypt, UsedIn, SIMULATION, IMPLEMENTATION
+from .attributes import Encrypt, UsedIn, SIMULATION, IMPLEMENTATION, Scope
 
 
 class FileMixIn(metaclass=ExtendedType, mixin=True):
@@ -144,10 +144,25 @@ class EDIFNetlistFile(pm.EDIFNetlistFile, FileMixIn):
         FileMixIn._registerAttributes(self)
 
 
+class CHeaderFile(SourceFile):
+    def _registerAttributes(self):
+        super()._registerAttributes()
+        self[UsedIn] = {SIMULATION}
+
+
 class CSourceFile(pm.CSourceFile, FileMixIn):
     def _registerAttributes(self):
         super()._registerAttributes()
         FileMixIn._registerAttributes(self)
+        self[UsedIn] = {SIMULATION}
+
+
+class SystemCSourceFile(CSourceFile):
+    pass
+
+
+class SystemCHeaderFile(CHeaderFile):
+    pass
 
 
 class SettingFile(pm.SettingFile, FileMixIn):
@@ -161,6 +176,7 @@ class ConstraintFile(pm.ConstraintFile, FileMixIn):
         super()._registerAttributes()
         FileMixIn._registerAttributes(self)
         self[UsedIn] = {IMPLEMENTATION}
+        self[Scope] = None
 
 
 class QuartusSignalTapFile(File):

{simplhdl-0.5.8 → simplhdl-0.7.0}/src/simplhdl/pyedaa/attributes.py

@@ -14,3 +14,8 @@ class UsedIn(pm.Attribute):
 class Encrypt(pm.Attribute):
     NAME: 'Encrypt'
     VALUE_TYPE: bool
+
+
+class Scope(pm.Attribute):
+    NAME: 'Scope'
+    VALUE_TYPE: str

{simplhdl-0.5.8 → simplhdl-0.7.0}/src/simplhdl/pyedaa/design.py

@@ -3,6 +3,7 @@ import pyEDAA.ProjectModel as pm
 from pathlib import Path
 from typing import Dict, Union, Generator
 
+from . import File
 from .vhdllibrary import VHDLLibrary
 
 
@@ -82,3 +83,8 @@ class Design(pm.Design):
                     continue
                 seen.append(fileid)
             yield file
+
+    def GetFile(self, path: Path) -> File:
+        for file in self.Files():
+            if file.Path.absolute() == path.absolute():
+                return file

{simplhdl-0.5.8 → simplhdl-0.7.0}/src/simplhdl/pyedaa/vhdllibrary.py

@@ -1,3 +1,4 @@
+import logging
 import pyEDAA.ProjectModel as pm
 
 from typing import Optional
@@ -5,6 +6,9 @@ from pathlib import Path
 from pyVHDLModel import VHDLVersion  # type: ignore
 
 
+logger = logging.getLogger(__name__)
+
+
 class VHDLLibrary(pm.VHDLLibrary):
 
     _path: Optional[Path]
@@ -18,9 +22,9 @@ class VHDLLibrary(pm.VHDLLibrary):
     ):
         super().__init__(name, project, design, vhdlVersion)
         if path is None:
-            self._path = name
+            self.Path = Path(name)
         else:
-            self._path = path
+            self.Path = path
 
     @property
     def Path(self) -> Optional[Path]:
@@ -28,4 +32,9 @@ class VHDLLibrary(pm.VHDLLibrary):
 
     @Path.setter
     def Path(self, path: Path) -> None:
-        self._path = path
+        if isinstance(path, str):
+            filename, lineno, funcname, info = logger.findCaller(stacklevel=3)
+            logger.debug(f"The VHDL library path is a string in {filename}:{lineno}")
+            self._path = Path(path)
+        else:
+            self._path = path