SimplHDL 0.5.8__tar.gz → 0.6.0__tar.gz

{simplhdl-0.5.8 → simplhdl-0.6.0}/PKG-INFO

@@ -1,6 +1,6 @@
 Metadata-Version: 2.4
 Name: SimplHDL
-Version: 0.5.8
+Version: 0.6.0
 Summary: A framework for simulating and implementing HDL designs
 Author-email: Rasmus Grøndahl Olsen <simplhdl@gmail.com>
 Maintainer-email: Rasmus Grøndahl Olsen <simplhdl@gmail.com>
@@ -56,6 +56,8 @@ Requires-Dist: rich
 Requires-Dist: vsg
 Requires-Dist: flake8
 Requires-Dist: black
+Requires-Dist: systemrdl-compiler
+Requires-Dist: peakrdl-html
 Dynamic: license-file
 
 ## Introduction

{simplhdl-0.5.8 → simplhdl-0.6.0}/pyproject.toml

@@ -24,6 +24,8 @@ dependencies = [
     "vsg",
     "flake8",
     "black",
+    "systemrdl-compiler",
+    "peakrdl-html",
 ]
 requires-python = ">=3.8"
 authors = [

{simplhdl-0.5.8 → simplhdl-0.6.0}/src/SimplHDL.egg-info/PKG-INFO

@@ -1,6 +1,6 @@
 Metadata-Version: 2.4
 Name: SimplHDL
-Version: 0.5.8
+Version: 0.6.0
 Summary: A framework for simulating and implementing HDL designs
 Author-email: Rasmus Grøndahl Olsen <simplhdl@gmail.com>
 Maintainer-email: Rasmus Grøndahl Olsen <simplhdl@gmail.com>
@@ -56,6 +56,8 @@ Requires-Dist: rich
 Requires-Dist: vsg
 Requires-Dist: flake8
 Requires-Dist: black
+Requires-Dist: systemrdl-compiler
+Requires-Dist: peakrdl-html
 Dynamic: license-file
 
 ## Introduction

{simplhdl-0.5.8 → simplhdl-0.6.0}/src/SimplHDL.egg-info/SOURCES.txt

@@ -177,6 +177,7 @@ src/simplhdl/resources/templates/vcs/files.j2
 src/simplhdl/resources/templates/vcs/fileset.j2
 src/simplhdl/resources/templates/vcs/pli.tab.j2
 src/simplhdl/resources/templates/vcs/project.mk.j2
+src/simplhdl/resources/templates/vcs/simv-run.do.j2
 src/simplhdl/resources/templates/vcs/synopsys_sim.setup.j2
 src/simplhdl/resources/templates/vcs/vcs.parameters.j2
 src/simplhdl/resources/templates/verible/__init__.py

{simplhdl-0.5.8 → simplhdl-0.6.0}/src/SimplHDL.egg-info/requires.txt

@@ -9,6 +9,8 @@ rich
 vsg
 flake8
 black
+systemrdl-compiler
+peakrdl-html
 
 [:python_version < "3.9"]
 importlib-resources

simplhdl-0.6.0/src/simplhdl/__init__.py

@@ -0,0 +1 @@
+__version__ = "0.6.0"

{simplhdl-0.5.8 → simplhdl-0.6.0}/src/simplhdl/flows/simulationflow.py

@@ -73,6 +73,7 @@ class SimulationFlow(FlowBase):
         globals['VHDLSourceFile'] = VHDLSourceFile
         globals['UsedIn'] = UsedIn
         globals['uvm'] = self.is_uvm()
+        globals['isinstance'] = isinstance
         return globals
 
     def generate(self):

{simplhdl-0.5.8 → simplhdl-0.6.0}/src/simplhdl/flows/vcs/vcsflow.py

@@ -34,9 +34,11 @@ class VcsFlow(SimulationFlow):
         )
         parser.add_argument(
             '-w',
-            '--wave',
-            action='store_true',
-            help="Dump waveforms"
+            '--wavedump',
+            nargs='?',
+            const='vpd',
+            choices=['vpd', 'evcd', 'fsdb'],
+            help="Dump waveforms using vpd, evcd or fsdb format"
         )
         parser.add_argument(
             '--gui',
@@ -92,6 +94,7 @@ class VcsFlow(SimulationFlow):
 
     def get_globals(self) -> Dict[str, Any]:
         globals = super().get_globals()
+        globals['wavedump'] = self.args.wavedump
         globals['vlogan_args'] = self.vlogan_args()
         globals['vhdlan_args'] = self.vhdlan_args()
         globals['vcs_args'] = self.vcs_args()
@@ -124,6 +127,8 @@ class VcsFlow(SimulationFlow):
             environment.get_template('synopsys_sim.setup.j2'),
             environment.get_template('project.mk.j2'),
             environment.get_template('vcs.parameters.j2'),
+            environment.get_template('simv-run.do.j2'),
+
         ]
 
     def get_cocotb_templates(self, environment):
@@ -179,7 +184,7 @@ class VcsFlow(SimulationFlow):
             args.add(f"-timescale={self.args.timescale}")
         if self.is_uvm():
             args.add('-ntb_opts uvm')
-        if self.args.gui:
+        if self.args.gui or self.args.wavedump:
             args.add('-debug_access+all')
             if self.is_verdi():
                 args.add('-kdb')
@@ -195,6 +200,10 @@ class VcsFlow(SimulationFlow):
             args.add(f"+ntb_random_seed={self.args.seed}")
         for name, value in self.project.PlusArgs.items():
             args.add(f"+{name}={escape(value)}")
+        if self.args.wavedump == 'vpd':
+            args.add('-ucli -do simv-run.do')
+        if self.args.wavedump == 'evcd' or self.args.wavedump == 'fsdb':
+            raise NotImplementedError(f"Wavedump for {self.args.wavedump} format is not yet implemented")
         return ' '.join(list(args) + [self.args.simv_args])
 
     def get_library(self, fileset: FileSet) -> str:

{simplhdl-0.5.8 → simplhdl-0.6.0}/src/simplhdl/generators/ipxact.py

@@ -17,7 +17,7 @@ from ..pyedaa.vhdllibrary import VHDLLibrary
 from ..pyedaa import (
     File, SystemVerilogSourceFile, TCLSourceFile, ConstraintFile, HDLSourceFile,
     VHDLSourceFile, VerilogSourceFile, VivadoIPSpecificationFile,
-    VerilogIncludeFile
+    VerilogIncludeFile, SystemCSourceFile, SystemCHeaderFile
 )
 
 logger = logging.getLogger(__name__)
@@ -40,6 +40,8 @@ FILETYPE_2014_MAP = {
     '.tcl': TCLSourceFile,
     'SDC': ConstraintFile,
     '.sdc': ConstraintFile,
+    'systemCSource': SystemCSourceFile,
+    'systemCSourceInclude': SystemCHeaderFile,
     'unknown': File,
 }
 
@@ -191,7 +193,7 @@ class VivadoIP(GeneratorBase):
                 file = component.filepath(file_element).with_suffix('.xml')
                 if file.exists():
                     files += self.get_files(file)
-        for view in component.views('.*simulation.*'):
+        for view in component.views('.*(verilog|vhdl)simulation.*'):
             filesets = component.filesets(view)
             for fileset in filesets:
                 files += component.pyedaa_files(fileset)
@@ -217,6 +219,9 @@ class VivadoIP(GeneratorBase):
                             i += 1
                             filesets.append(fileset)
                         last_lib = file.Library.Name
-                    fileset.AddFile(file)
+                    try:
+                        fileset.AddFile(file)
+                    except Exception:
+                        logger.warning(f"Failed to add {file.Path}")
                 for fileset in filesets:
                     newipfile.FileSet._fileSets[fileset.Name] = fileset

simplhdl-0.6.0/src/simplhdl/generators/systemrdl.py

@@ -0,0 +1,202 @@
+import os
+import logging
+import jinja2
+
+from typing import List
+from pathlib import Path
+from systemrdl import RDLCompiler, RDLCompileError, RDLListener, RDLWalker
+from systemrdl.node import AddrmapNode
+from systemrdl.rdltypes import AccessType, OnReadType, OnWriteType
+from peakrdl_html import HTMLExporter
+
+from ..generator import GeneratorFactory, GeneratorBase
+from ..pyedaa import SystemRDLSourceFile, SystemVerilogSourceFile, VerilogSourceFile
+from ..flow import FlowBase
+
+
+logger = logging.getLogger(__name__)
+
+seennodes: List[AddrmapNode] = []
+addrmapnodes: List[AddrmapNode] = []
+hierachymapnodes: List[AddrmapNode] = []
+
+
+class Environment(jinja2.Environment):
+    def find_template(self, name):
+        list = [i for i in self.list_templates() if i.startswith(name)]
+        if len(list) == 0:
+            raise jinja2.TemplateNotFound(name)
+        if len(list) > 1:
+            logger.warning(f"Multiple templates found ({list}) for {name}")
+        return self.get_template(list[0])
+
+
+class Listener(RDLListener):
+    def exit_Addrmap(self, node: AddrmapNode):
+        seen = [n for n in seennodes if n.type_name == node.type_name]
+        if not seen:
+            seennodes.append(node)
+            if AddrmapNode not in [type(c) for c in node.children()]:
+                addrmapnodes.append(node)
+            else:
+                hierachymapnodes.append(node)
+
+
+def get_template_dirs() -> List[Path]:
+    string = os.getenv('SIMPLHDL_SYSTEMRDL_TEMPLATES')
+    if string:
+        templates = [Path(p) for p in string.split(':')]
+        for t in templates:
+            if not t.is_dir():
+                logger.error(f"Directory {t} does not exist")
+                raise SystemError
+    else:
+        logger.error("SIMPLHDL_SYSTEMRDL_TEMPLATES is not set, no templates found")
+        raise SystemError
+    return templates
+
+
+def get_reg_access(reg) -> str:
+    if reg.has_sw_readable and reg.has_sw_writable:
+        return "RW"
+    elif reg.has_sw_writable:
+        return "WO"
+    elif reg.has_sw_readable:
+        return "RO"
+    else:
+        return "RW"
+
+
+def get_field_access(field) -> str:  # noqa: C901
+    """
+    Get field's UVM access string
+    """
+    sw = field.get_property("sw")
+    onread = field.get_property("onread")
+    onwrite = field.get_property("onwrite")
+
+    if sw == AccessType.rw:
+        if (onwrite is None) and (onread is None):
+            return "RW"
+        elif (onread == OnReadType.rclr) and (onwrite == OnWriteType.woset):
+            return "W1SRC"
+        elif (onread == OnReadType.rclr) and (onwrite == OnWriteType.wzs):
+            return "W0SRC"
+        elif (onread == OnReadType.rclr) and (onwrite == OnWriteType.wset):
+            return "WSRC"
+        elif (onread == OnReadType.rset) and (onwrite == OnWriteType.woclr):
+            return "W1CRS"
+        elif (onread == OnReadType.rset) and (onwrite == OnWriteType.wzc):
+            return "W0CRS"
+        elif (onread == OnReadType.rset) and (onwrite == OnWriteType.wclr):
+            return "WCRS"
+        elif onwrite == OnWriteType.woclr:
+            return "W1C"
+        elif onwrite == OnWriteType.woset:
+            return "W1S"
+        elif onwrite == OnWriteType.wot:
+            return "W1T"
+        elif onwrite == OnWriteType.wzc:
+            return "W0C"
+        elif onwrite == OnWriteType.wzs:
+            return "W0S"
+        elif onwrite == OnWriteType.wzt:
+            return "W0T"
+        elif onwrite == OnWriteType.wclr:
+            return "WC"
+        elif onwrite == OnWriteType.wset:
+            return "WS"
+        elif onread == OnReadType.rclr:
+            return "WRC"
+        elif onread == OnReadType.rset:
+            return "WRS"
+        else:
+            return "RW"
+
+    elif sw == AccessType.r:
+        if onread is None:
+            return "RO"
+        elif onread == OnReadType.rclr:
+            return "RC"
+        elif onread == OnReadType.rset:
+            return "RS"
+        else:
+            return "RO"
+
+    elif sw == AccessType.w:
+        if onwrite is None:
+            return "WO"
+        elif onwrite == OnWriteType.wclr:
+            return "WOC"
+        elif onwrite == OnWriteType.wset:
+            return "WOS"
+        else:
+            return "WO"
+
+    elif sw == AccessType.rw1:
+        return "W1"
+
+    elif sw == AccessType.w1:
+        return "WO1"
+
+    else:
+        return "NOACCESS"
+
+
+@GeneratorFactory.register('SystemRDL')
+class SystemRDL(GeneratorBase):
+
+    def render_template(self, template, node, outputdir) -> Path:
+        context = template.render(node=node)
+        outputdir.mkdir(parents=True, exist_ok=True)
+        outputfile: Path = outputdir.joinpath(f'{node.type_name}__{Path(template.filename).name[:-3]}').absolute()
+        with outputfile.open('w') as f:
+            f.write(context)
+        rdlfile = self.project.DefaultDesign.GetFile(node.inst.def_src_ref.path)
+        fileset = rdlfile.FileSet
+        if outputfile.suffix == '.sv':
+            fileset.InsertFileAfter(rdlfile, SystemVerilogSourceFile(outputfile))
+        if outputfile.suffix == '.v':
+            fileset.InsertFileAfter(rdlfile, VerilogSourceFile(outputfile))
+
+    def run(self, flow: FlowBase):
+        rdlfiles = list(self.project.DefaultDesign.DefaultFileSet.Files(fileType=SystemRDLSourceFile))
+        output_dir = self.builddir.joinpath('systemrdl')
+
+        if not rdlfiles:
+            return
+
+        rdlc = RDLCompiler()
+        try:
+            for rdlfile in rdlfiles:
+                rdlc.compile_file(rdlfile.Path, defines=self.project.Defines)
+                root = rdlc.elaborate()
+        except RDLCompileError as e:
+            logger.error(str(e))
+            raise SystemError
+
+        walker = RDLWalker()
+        walker.walk(root, Listener())
+
+        templatedirs = get_template_dirs()
+
+        for templatedir in templatedirs:
+            logger.info(f"Generate from template {templatedir}")
+            sub_dir = output_dir.joinpath(templatedir.name)
+
+            env = Environment(
+                loader=jinja2.FileSystemLoader(templatedir),
+                trim_blocks=True)
+            env.globals['hex'] = hex
+            env.globals['get_field_access'] = get_field_access
+            env.globals['get_reg_access'] = get_reg_access
+            template = env.find_template('registermap')
+            for node in addrmapnodes:
+                self.render_template(template=template, node=node, outputdir=sub_dir)
+
+            template = env.find_template('hierachymap')
+            for node in hierachymapnodes:
+                self.render_template(template=template, node=node, outputdir=sub_dir)
+
+        logger.info("Generate HTML Documentation")
+        _ = HTMLExporter().export(root, output_dir.joinpath('docs'))

{simplhdl-0.5.8 → simplhdl-0.6.0}/src/simplhdl/pyedaa/__init__.py

@@ -144,10 +144,25 @@ class EDIFNetlistFile(pm.EDIFNetlistFile, FileMixIn):
         FileMixIn._registerAttributes(self)
 
 
+class CHeaderFile(SourceFile):
+    def _registerAttributes(self):
+        super()._registerAttributes()
+        self[UsedIn] = {SIMULATION}
+
+
 class CSourceFile(pm.CSourceFile, FileMixIn):
     def _registerAttributes(self):
         super()._registerAttributes()
         FileMixIn._registerAttributes(self)
+        self[UsedIn] = {SIMULATION}
+
+
+class SystemCSourceFile(CSourceFile):
+    pass
+
+
+class SystemCHeaderFile(CHeaderFile):
+    pass
 
 
 class SettingFile(pm.SettingFile, FileMixIn):

{simplhdl-0.5.8 → simplhdl-0.6.0}/src/simplhdl/pyedaa/design.py

@@ -3,6 +3,7 @@ import pyEDAA.ProjectModel as pm
 from pathlib import Path
 from typing import Dict, Union, Generator
 
+from . import File
 from .vhdllibrary import VHDLLibrary
 
 
@@ -82,3 +83,8 @@ class Design(pm.Design):
                     continue
                 seen.append(fileid)
             yield file
+
+    def GetFile(self, path: Path) -> File:
+        for file in self.Files():
+            if file.Path.absolute() == path.absolute():
+                return file

{simplhdl-0.5.8 → simplhdl-0.6.0}/src/simplhdl/resources/templates/questasim/project.qrun.j2

@@ -20,7 +20,8 @@
 {% for fileset in filesets %}
 -makelib {{fileset.VHDLLibrary.Name}}:{{fileset.VHDLLibrary.Path}}
 {% for file in fileset.GetFiles() %}
-{% if file.FileType in [SystemVerilogSourceFile, VerilogSourceFile, VHDLSourceFile] and 'simulation' in file[UsedIn] %}
+
+{% if isinstance(file, (SystemVerilogSourceFile, VerilogSourceFile, VHDLSourceFile)) and 'simulation' in file[UsedIn] %}
 	{{file.Path}}
 {% endif %}
 {% endfor %}

simplhdl-0.6.0/src/simplhdl/resources/templates/vcs/simv-run.do.j2

@@ -0,0 +1,6 @@
+{% if wavedump is not none %}
+set fid [dump -file waves.{{wavedump}} -type {{wavedump.upper()}}]
+dump -add . -aggregates -fid $fid
+{% endif %}
+run
+quit

{simplhdl-0.5.8 → simplhdl-0.6.0}/src/simplhdl/resources/templates/vivado/project.tcl.j2

@@ -6,6 +6,17 @@ proc source_script {filename} {
     }
 }
 
+
+proc source_bd_script {filename} {
+    # Fail if bd script return an error code or a non zero value
+    if {[catch {source -notrace $filename} err]} {
+        return -code 1
+    } elseif {$err != 0} {
+        return -code 1
+    }
+}
+
+
 proc source_step_script {filename} {
     # NOTE: make get_files fail if not files are found
     set_msg_config -id {Vivado 12-818} -new_severity {ERROR}
@@ -101,7 +112,7 @@ read_edif "{{file.Path|replace('\\', '/')}}"
 read_bd "{{file.Path|replace('\\', '/')}}"
 {% elif file.FileType == VivadoBDTclFile %}
 send_msg_id {SimplHDL PRJ-3} {INFO} "Sourcing BD tcl file {{file.Path|replace('\\', '/')}}: this might take some time."
-source_script "{{file.Path|replace('\\', '/')}}"
+source_bd_script "{{file.Path|replace('\\', '/')}}"
 {% elif file.FileType == VivadoProjectStepFile %}
 add_files -fileset utils_1 "{{file.Path|replace('\\', '/')}}"
 global step

simplhdl-0.5.8/src/simplhdl/__init__.py

@@ -1 +0,0 @@
-__version__ = "0.5.8"

simplhdl-0.5.8/src/simplhdl/generators/systemrdl.py

@@ -1,27 +0,0 @@
-import logging
-
-from ..generator import GeneratorFactory, GeneratorBase
-from ..pyedaa import SystemRDLSourceFile, SystemVerilogSourceFile
-from ..flow import FlowBase
-from ..utils import sh
-
-logger = logging.getLogger(__name__)
-
-
-@GeneratorFactory.register('SystemRDL')
-class SystemRDL(GeneratorBase):
-
-    def run(self, flow: FlowBase):
-        rdlfiles = self.project.DefaultDesign.DefaultFileSet.Files(fileType=SystemRDLSourceFile)
-        output_dir = self.builddir.joinpath('systemrdl')
-
-        for rdlfile in rdlfiles:
-            logger.debug("Running SystemRDL Generator")
-            output_dir.mkdir(exist_ok=True)
-            sh(f'peakrdl regblock {rdlfile.Path} -o {output_dir} --cpuif axi4-lite'.split())
-            pkgfile = SystemVerilogSourceFile(output_dir.joinpath(f'{rdlfile.Path.stem}_pkg.sv'))
-            svfile = SystemVerilogSourceFile(output_dir.joinpath(f'{rdlfile.Path.stem}.sv'))
-            rdlfile.FileSet.InsertFileAfter(rdlfile, pkgfile)
-            rdlfile.FileSet.InsertFileAfter(rdlfile, svfile)
-            # NOTE: After inserting files call next to prevent infinit iterations
-            next(rdlfiles)