SimplHDL 0.5.4__tar.gz → 0.5.6__tar.gz
This diff represents the content of publicly available package versions that have been released to one of the supported registries. The information contained in this diff is provided for informational purposes only and reflects changes between package versions as they appear in their respective public registries.
- {simplhdl-0.5.4 → simplhdl-0.5.6}/PKG-INFO +1 -1
- {simplhdl-0.5.4 → simplhdl-0.5.6}/src/SimplHDL.egg-info/PKG-INFO +1 -1
- simplhdl-0.5.6/src/simplhdl/__init__.py +1 -0
- {simplhdl-0.5.4 → simplhdl-0.5.6}/src/simplhdl/__main__.py +14 -2
- {simplhdl-0.5.4 → simplhdl-0.5.6}/src/simplhdl/cocotb.py +8 -6
- {simplhdl-0.5.4 → simplhdl-0.5.6}/src/simplhdl/flow.py +7 -0
- {simplhdl-0.5.4 → simplhdl-0.5.6}/src/simplhdl/flows/flake8/flake8flow.py +1 -1
- {simplhdl-0.5.4 → simplhdl-0.5.6}/src/simplhdl/flows/verible/veribleflow.py +7 -4
- {simplhdl-0.5.4 → simplhdl-0.5.6}/src/simplhdl/flows/vsg/vsgflow.py +5 -2
- {simplhdl-0.5.4 → simplhdl-0.5.6}/src/simplhdl/generators/spd.py +28 -10
- {simplhdl-0.5.4 → simplhdl-0.5.6}/src/simplhdl/pyedaa/design.py +5 -4
- {simplhdl-0.5.4 → simplhdl-0.5.6}/src/simplhdl/utils.py +2 -2
- simplhdl-0.5.4/src/simplhdl/__init__.py +0 -1
- {simplhdl-0.5.4 → simplhdl-0.5.6}/.github/workflows/publish.yml +0 -0
- {simplhdl-0.5.4 → simplhdl-0.5.6}/.gitignore +0 -0
- {simplhdl-0.5.4 → simplhdl-0.5.6}/.readthedocs.yaml +0 -0
- {simplhdl-0.5.4 → simplhdl-0.5.6}/LICENSE +0 -0
- {simplhdl-0.5.4 → simplhdl-0.5.6}/README.md +0 -0
- {simplhdl-0.5.4 → simplhdl-0.5.6}/docs/_static/simplhdl_dark.png +0 -0
- {simplhdl-0.5.4 → simplhdl-0.5.6}/docs/_static/simplhdl_light.png +0 -0
- {simplhdl-0.5.4 → simplhdl-0.5.6}/docs/_static/simplhdl_light_1.png +0 -0
- {simplhdl-0.5.4 → simplhdl-0.5.6}/docs/conf.py +0 -0
- {simplhdl-0.5.4 → simplhdl-0.5.6}/docs/drawing.svg +0 -0
- {simplhdl-0.5.4 → simplhdl-0.5.6}/docs/flows/ghdl.rst +0 -0
- {simplhdl-0.5.4 → simplhdl-0.5.6}/docs/flows/icarus.rst +0 -0
- {simplhdl-0.5.4 → simplhdl-0.5.6}/docs/flows/quartus.rst +0 -0
- {simplhdl-0.5.4 → simplhdl-0.5.6}/docs/flows/questasim.rst +0 -0
- {simplhdl-0.5.4 → simplhdl-0.5.6}/docs/flows/vcs.rst +0 -0
- {simplhdl-0.5.4 → simplhdl-0.5.6}/docs/flows/vivado.rst +0 -0
- {simplhdl-0.5.4 → simplhdl-0.5.6}/docs/flows/xsim.rst +0 -0
- {simplhdl-0.5.4 → simplhdl-0.5.6}/docs/flows.rst +0 -0
- {simplhdl-0.5.4 → simplhdl-0.5.6}/docs/index.rst +0 -0
- {simplhdl-0.5.4 → simplhdl-0.5.6}/docs/intel-ips.md +0 -0
- {simplhdl-0.5.4 → simplhdl-0.5.6}/docs/introduction.rst +0 -0
- {simplhdl-0.5.4 → simplhdl-0.5.6}/docs/plugins.rst +0 -0
- {simplhdl-0.5.4 → simplhdl-0.5.6}/docs/requirements.txt +0 -0
- {simplhdl-0.5.4 → simplhdl-0.5.6}/examples/hdl/adder/adder.yml +0 -0
- {simplhdl-0.5.4 → simplhdl-0.5.6}/examples/hdl/adder/hdl/adder.sv +0 -0
- {simplhdl-0.5.4 → simplhdl-0.5.6}/examples/hdl/adder/sim/testbench.sv +0 -0
- {simplhdl-0.5.4 → simplhdl-0.5.6}/examples/hdl/adder/sim/testbench.yml +0 -0
- {simplhdl-0.5.4 → simplhdl-0.5.6}/examples/hdl/adder/syn/build.yml +0 -0
- {simplhdl-0.5.4 → simplhdl-0.5.6}/examples/hdl/adder/syn/placement.xdc +0 -0
- {simplhdl-0.5.4 → simplhdl-0.5.6}/examples/hdl/adder/syn/timing.xdc +0 -0
- {simplhdl-0.5.4 → simplhdl-0.5.6}/examples/hdl/adder/syn/top.sv +0 -0
- {simplhdl-0.5.4 → simplhdl-0.5.6}/examples/hdl/alu/alu.yml +0 -0
- {simplhdl-0.5.4 → simplhdl-0.5.6}/examples/hdl/alu/hdl/add.sv +0 -0
- {simplhdl-0.5.4 → simplhdl-0.5.6}/examples/hdl/alu/hdl/alu.sv +0 -0
- {simplhdl-0.5.4 → simplhdl-0.5.6}/examples/hdl/alu/hdl/mul.sv +0 -0
- {simplhdl-0.5.4 → simplhdl-0.5.6}/examples/hdl/alu/hdl/sub.sv +0 -0
- {simplhdl-0.5.4 → simplhdl-0.5.6}/examples/hdl/alu/sim/pyuvm/alu_vip/__init__.py +0 -0
- {simplhdl-0.5.4 → simplhdl-0.5.6}/examples/hdl/alu/sim/pyuvm/alu_vip/agent.py +0 -0
- {simplhdl-0.5.4 → simplhdl-0.5.6}/examples/hdl/alu/sim/pyuvm/alu_vip/aluif.py +0 -0
- {simplhdl-0.5.4 → simplhdl-0.5.6}/examples/hdl/alu/sim/pyuvm/alu_vip/driver.py +0 -0
- {simplhdl-0.5.4 → simplhdl-0.5.6}/examples/hdl/alu/sim/pyuvm/alu_vip/monitor.py +0 -0
- {simplhdl-0.5.4 → simplhdl-0.5.6}/examples/hdl/alu/sim/pyuvm/alu_vip/sequenceitem.py +0 -0
- {simplhdl-0.5.4 → simplhdl-0.5.6}/examples/hdl/alu/sim/pyuvm/alu_vip/sequencer.py +0 -0
- {simplhdl-0.5.4 → simplhdl-0.5.6}/examples/hdl/alu/sim/pyuvm/clock_vip/__init__.py +0 -0
- {simplhdl-0.5.4 → simplhdl-0.5.6}/examples/hdl/alu/sim/pyuvm/clock_vip/agent.py +0 -0
- {simplhdl-0.5.4 → simplhdl-0.5.6}/examples/hdl/alu/sim/pyuvm/clock_vip/clockif.py +0 -0
- {simplhdl-0.5.4 → simplhdl-0.5.6}/examples/hdl/alu/sim/pyuvm/pyuvm.yml +0 -0
- {simplhdl-0.5.4 → simplhdl-0.5.6}/examples/hdl/alu/sim/pyuvm/test/__init__.py +0 -0
- {simplhdl-0.5.4 → simplhdl-0.5.6}/examples/hdl/alu/sim/pyuvm/test/env.py +0 -0
- {simplhdl-0.5.4 → simplhdl-0.5.6}/examples/hdl/alu/sim/pyuvm/test/seq_lib.py +0 -0
- {simplhdl-0.5.4 → simplhdl-0.5.6}/examples/hdl/alu/sim/pyuvm/test/test.py +0 -0
- {simplhdl-0.5.4 → simplhdl-0.5.6}/examples/hdl/alu/sim/pyuvm/testbench.py +0 -0
- {simplhdl-0.5.4 → simplhdl-0.5.6}/examples/hdl/alu/sim/uvm/alu_vip/agent.svh +0 -0
- {simplhdl-0.5.4 → simplhdl-0.5.6}/examples/hdl/alu/sim/uvm/alu_vip/alu_vip.sv +0 -0
- {simplhdl-0.5.4 → simplhdl-0.5.6}/examples/hdl/alu/sim/uvm/alu_vip/alu_vip.yml +0 -0
- {simplhdl-0.5.4 → simplhdl-0.5.6}/examples/hdl/alu/sim/uvm/alu_vip/driver.svh +0 -0
- {simplhdl-0.5.4 → simplhdl-0.5.6}/examples/hdl/alu/sim/uvm/alu_vip/env.svh +0 -0
- {simplhdl-0.5.4 → simplhdl-0.5.6}/examples/hdl/alu/sim/uvm/alu_vip/monitor.svh +0 -0
- {simplhdl-0.5.4 → simplhdl-0.5.6}/examples/hdl/alu/sim/uvm/alu_vip/sequence_item.svh +0 -0
- {simplhdl-0.5.4 → simplhdl-0.5.6}/examples/hdl/alu/sim/uvm/tb_env/seq_lib/add_seq.svh +0 -0
- {simplhdl-0.5.4 → simplhdl-0.5.6}/examples/hdl/alu/sim/uvm/tb_env/seq_lib/base_seq.svh +0 -0
- {simplhdl-0.5.4 → simplhdl-0.5.6}/examples/hdl/alu/sim/uvm/tb_env/tb_env.sv +0 -0
- {simplhdl-0.5.4 → simplhdl-0.5.6}/examples/hdl/alu/sim/uvm/tb_env/tb_env.yml +0 -0
- {simplhdl-0.5.4 → simplhdl-0.5.6}/examples/hdl/alu/sim/uvm/tb_env/test/base_test.svh +0 -0
- {simplhdl-0.5.4 → simplhdl-0.5.6}/examples/hdl/alu/sim/uvm/tb_env/test/test_add.svh +0 -0
- {simplhdl-0.5.4 → simplhdl-0.5.6}/examples/hdl/alu/sim/uvm/testbench/alu_if.sv +0 -0
- {simplhdl-0.5.4 → simplhdl-0.5.6}/examples/hdl/alu/sim/uvm/testbench/testbench.sv +0 -0
- {simplhdl-0.5.4 → simplhdl-0.5.6}/examples/hdl/alu/sim/uvm/testbench/testbench.yml +0 -0
- {simplhdl-0.5.4 → simplhdl-0.5.6}/examples/hdl/alu/sim/uvm/testcases/test_add/test_add.yml +0 -0
- {simplhdl-0.5.4 → simplhdl-0.5.6}/examples/hdl/alu/syn/build.yml +0 -0
- {simplhdl-0.5.4 → simplhdl-0.5.6}/examples/hdl/alu/syn/placement.xdc +0 -0
- {simplhdl-0.5.4 → simplhdl-0.5.6}/examples/hdl/alu/syn/timing.xdc +0 -0
- {simplhdl-0.5.4 → simplhdl-0.5.6}/examples/hdl/hello/build.sbt +0 -0
- {simplhdl-0.5.4 → simplhdl-0.5.6}/examples/hdl/hello/hello.yml +0 -0
- {simplhdl-0.5.4 → simplhdl-0.5.6}/examples/hdl/hello/src/main/scala/Hello.scala +0 -0
- {simplhdl-0.5.4 → simplhdl-0.5.6}/examples/hdl/hello/syn/build.yml +0 -0
- {simplhdl-0.5.4 → simplhdl-0.5.6}/examples/plugins/simple_parser/setup.py +0 -0
- {simplhdl-0.5.4 → simplhdl-0.5.6}/examples/plugins/simple_parser/src/simple_parser/__init__.py +0 -0
- {simplhdl-0.5.4 → simplhdl-0.5.6}/examples/plugins/simple_parser/src/simple_parser/simple_parser.py +0 -0
- {simplhdl-0.5.4 → simplhdl-0.5.6}/pyproject.toml +0 -0
- {simplhdl-0.5.4 → simplhdl-0.5.6}/setup.cfg +0 -0
- {simplhdl-0.5.4 → simplhdl-0.5.6}/src/SimplHDL.egg-info/SOURCES.txt +0 -0
- {simplhdl-0.5.4 → simplhdl-0.5.6}/src/SimplHDL.egg-info/dependency_links.txt +0 -0
- {simplhdl-0.5.4 → simplhdl-0.5.6}/src/SimplHDL.egg-info/entry_points.txt +0 -0
- {simplhdl-0.5.4 → simplhdl-0.5.6}/src/SimplHDL.egg-info/requires.txt +0 -0
- {simplhdl-0.5.4 → simplhdl-0.5.6}/src/SimplHDL.egg-info/top_level.txt +0 -0
- {simplhdl-0.5.4 → simplhdl-0.5.6}/src/simplhdl/flows/__init__.py +0 -0
- {simplhdl-0.5.4 → simplhdl-0.5.6}/src/simplhdl/flows/encrypt/__init__.py +0 -0
- {simplhdl-0.5.4 → simplhdl-0.5.6}/src/simplhdl/flows/encrypt/encryptflow.py +0 -0
- {simplhdl-0.5.4 → simplhdl-0.5.6}/src/simplhdl/flows/implementationflow.py +0 -0
- {simplhdl-0.5.4 → simplhdl-0.5.6}/src/simplhdl/flows/lint/lintflow.py +0 -0
- {simplhdl-0.5.4 → simplhdl-0.5.6}/src/simplhdl/flows/modelsim/__init__.py +0 -0
- {simplhdl-0.5.4 → simplhdl-0.5.6}/src/simplhdl/flows/modelsim/modelsimflow.py +0 -0
- {simplhdl-0.5.4 → simplhdl-0.5.6}/src/simplhdl/flows/quartusdse/__init__.py +0 -0
- {simplhdl-0.5.4 → simplhdl-0.5.6}/src/simplhdl/flows/quartusdse/quartusdseflow.py +0 -0
- {simplhdl-0.5.4 → simplhdl-0.5.6}/src/simplhdl/flows/quartusexport/__init__.py +0 -0
- {simplhdl-0.5.4 → simplhdl-0.5.6}/src/simplhdl/flows/quartusexport/quartusexportflow.py +0 -0
- {simplhdl-0.5.4 → simplhdl-0.5.6}/src/simplhdl/flows/quartusflow.py +0 -0
- {simplhdl-0.5.4 → simplhdl-0.5.6}/src/simplhdl/flows/questasim/__init__.py +0 -0
- {simplhdl-0.5.4 → simplhdl-0.5.6}/src/simplhdl/flows/questasim/questasimflow.py +0 -0
- {simplhdl-0.5.4 → simplhdl-0.5.6}/src/simplhdl/flows/rivierapro/__init__.py +0 -0
- {simplhdl-0.5.4 → simplhdl-0.5.6}/src/simplhdl/flows/rivierapro/rivieraproflow.py +0 -0
- {simplhdl-0.5.4 → simplhdl-0.5.6}/src/simplhdl/flows/simulationflow.py +0 -0
- {simplhdl-0.5.4 → simplhdl-0.5.6}/src/simplhdl/flows/vcs/__init__.py +0 -0
- {simplhdl-0.5.4 → simplhdl-0.5.6}/src/simplhdl/flows/vcs/vcsflow.py +0 -0
- {simplhdl-0.5.4 → simplhdl-0.5.6}/src/simplhdl/flows/verible/__init__.py +0 -0
- {simplhdl-0.5.4 → simplhdl-0.5.6}/src/simplhdl/flows/vivadoflow.py +0 -0
- {simplhdl-0.5.4 → simplhdl-0.5.6}/src/simplhdl/flows/vsg/__init__.py +0 -0
- {simplhdl-0.5.4 → simplhdl-0.5.6}/src/simplhdl/flows/xsim/__init__.py +0 -0
- {simplhdl-0.5.4 → simplhdl-0.5.6}/src/simplhdl/flows/xsim/xsimflow.py +0 -0
- {simplhdl-0.5.4 → simplhdl-0.5.6}/src/simplhdl/generator.py +0 -0
- {simplhdl-0.5.4 → simplhdl-0.5.6}/src/simplhdl/generators/__init__.py +0 -0
- {simplhdl-0.5.4 → simplhdl-0.5.6}/src/simplhdl/generators/chisel.py +0 -0
- {simplhdl-0.5.4 → simplhdl-0.5.6}/src/simplhdl/generators/ipxact.py +0 -0
- {simplhdl-0.5.4 → simplhdl-0.5.6}/src/simplhdl/generators/systemrdl.py +0 -0
- {simplhdl-0.5.4 → simplhdl-0.5.6}/src/simplhdl/info.py +0 -0
- {simplhdl-0.5.4 → simplhdl-0.5.6}/src/simplhdl/parser.py +0 -0
- {simplhdl-0.5.4 → simplhdl-0.5.6}/src/simplhdl/parsers/__init__.py +0 -0
- {simplhdl-0.5.4 → simplhdl-0.5.6}/src/simplhdl/parsers/fusesocparser.py +0 -0
- {simplhdl-0.5.4 → simplhdl-0.5.6}/src/simplhdl/parsers/simplhdlparser.py +0 -0
- {simplhdl-0.5.4 → simplhdl-0.5.6}/src/simplhdl/plugins.py +0 -0
- {simplhdl-0.5.4 → simplhdl-0.5.6}/src/simplhdl/pyedaa/__init__.py +0 -0
- {simplhdl-0.5.4 → simplhdl-0.5.6}/src/simplhdl/pyedaa/attributes.py +0 -0
- {simplhdl-0.5.4 → simplhdl-0.5.6}/src/simplhdl/pyedaa/fileset.py +0 -0
- {simplhdl-0.5.4 → simplhdl-0.5.6}/src/simplhdl/pyedaa/filetypes.py +0 -0
- {simplhdl-0.5.4 → simplhdl-0.5.6}/src/simplhdl/pyedaa/project.py +0 -0
- {simplhdl-0.5.4 → simplhdl-0.5.6}/src/simplhdl/pyedaa/target.py +0 -0
- {simplhdl-0.5.4 → simplhdl-0.5.6}/src/simplhdl/pyedaa/vhdllibrary.py +0 -0
- {simplhdl-0.5.4 → simplhdl-0.5.6}/src/simplhdl/repo.py +0 -0
- {simplhdl-0.5.4 → simplhdl-0.5.6}/src/simplhdl/resources/__init__.py +0 -0
- {simplhdl-0.5.4 → simplhdl-0.5.6}/src/simplhdl/resources/templates/__init__.py +0 -0
- {simplhdl-0.5.4 → simplhdl-0.5.6}/src/simplhdl/resources/templates/flake8/__init__.py +0 -0
- {simplhdl-0.5.4 → simplhdl-0.5.6}/src/simplhdl/resources/templates/flake8/setup.cfg.j2 +0 -0
- {simplhdl-0.5.4 → simplhdl-0.5.6}/src/simplhdl/resources/templates/modelsim/Makefile.j2 +0 -0
- {simplhdl-0.5.4 → simplhdl-0.5.6}/src/simplhdl/resources/templates/modelsim/__init__.py +0 -0
- {simplhdl-0.5.4 → simplhdl-0.5.6}/src/simplhdl/resources/templates/modelsim/cocotb.mk.j2 +0 -0
- {simplhdl-0.5.4 → simplhdl-0.5.6}/src/simplhdl/resources/templates/modelsim/dependencies.mk.j2 +0 -0
- {simplhdl-0.5.4 → simplhdl-0.5.6}/src/simplhdl/resources/templates/modelsim/files.j2 +0 -0
- {simplhdl-0.5.4 → simplhdl-0.5.6}/src/simplhdl/resources/templates/modelsim/fileset.j2 +0 -0
- {simplhdl-0.5.4 → simplhdl-0.5.6}/src/simplhdl/resources/templates/modelsim/modelsim.tcl.j2 +0 -0
- {simplhdl-0.5.4 → simplhdl-0.5.6}/src/simplhdl/resources/templates/modelsim/project.mk.j2 +0 -0
- {simplhdl-0.5.4 → simplhdl-0.5.6}/src/simplhdl/resources/templates/modelsim/run.do.j2 +0 -0
- {simplhdl-0.5.4 → simplhdl-0.5.6}/src/simplhdl/resources/templates/quartus/__init__.py +0 -0
- {simplhdl-0.5.4 → simplhdl-0.5.6}/src/simplhdl/resources/templates/quartus/project.tcl.j2 +0 -0
- {simplhdl-0.5.4 → simplhdl-0.5.6}/src/simplhdl/resources/templates/quartus/run.tcl.j2 +0 -0
- {simplhdl-0.5.4 → simplhdl-0.5.6}/src/simplhdl/resources/templates/questasim/__init__.py +0 -0
- {simplhdl-0.5.4 → simplhdl-0.5.6}/src/simplhdl/resources/templates/questasim/modelsim.tcl.j2 +0 -0
- {simplhdl-0.5.4 → simplhdl-0.5.6}/src/simplhdl/resources/templates/questasim/project.qrun.j2 +0 -0
- {simplhdl-0.5.4 → simplhdl-0.5.6}/src/simplhdl/resources/templates/questasim/visualizer.tcl.j2 +0 -0
- {simplhdl-0.5.4 → simplhdl-0.5.6}/src/simplhdl/resources/templates/questasim/vsim-run.do.j2 +0 -0
- {simplhdl-0.5.4 → simplhdl-0.5.6}/src/simplhdl/resources/templates/rivierapro/Makefile.j2 +0 -0
- {simplhdl-0.5.4 → simplhdl-0.5.6}/src/simplhdl/resources/templates/rivierapro/__init__.py +0 -0
- {simplhdl-0.5.4 → simplhdl-0.5.6}/src/simplhdl/resources/templates/rivierapro/cocotb.mk.j2 +0 -0
- {simplhdl-0.5.4 → simplhdl-0.5.6}/src/simplhdl/resources/templates/rivierapro/dependencies.mk.j2 +0 -0
- {simplhdl-0.5.4 → simplhdl-0.5.6}/src/simplhdl/resources/templates/rivierapro/files.j2 +0 -0
- {simplhdl-0.5.4 → simplhdl-0.5.6}/src/simplhdl/resources/templates/rivierapro/fileset.j2 +0 -0
- {simplhdl-0.5.4 → simplhdl-0.5.6}/src/simplhdl/resources/templates/rivierapro/project.mk.j2 +0 -0
- {simplhdl-0.5.4 → simplhdl-0.5.6}/src/simplhdl/resources/templates/vcs/Makefile.j2 +0 -0
- {simplhdl-0.5.4 → simplhdl-0.5.6}/src/simplhdl/resources/templates/vcs/__init__.py +0 -0
- {simplhdl-0.5.4 → simplhdl-0.5.6}/src/simplhdl/resources/templates/vcs/cocotb.mk.j2 +0 -0
- {simplhdl-0.5.4 → simplhdl-0.5.6}/src/simplhdl/resources/templates/vcs/dependencies.mk.j2 +0 -0
- {simplhdl-0.5.4 → simplhdl-0.5.6}/src/simplhdl/resources/templates/vcs/files.j2 +0 -0
- {simplhdl-0.5.4 → simplhdl-0.5.6}/src/simplhdl/resources/templates/vcs/fileset.j2 +0 -0
- {simplhdl-0.5.4 → simplhdl-0.5.6}/src/simplhdl/resources/templates/vcs/pli.tab.j2 +0 -0
- {simplhdl-0.5.4 → simplhdl-0.5.6}/src/simplhdl/resources/templates/vcs/project.mk.j2 +0 -0
- {simplhdl-0.5.4 → simplhdl-0.5.6}/src/simplhdl/resources/templates/vcs/synopsys_sim.setup.j2 +0 -0
- {simplhdl-0.5.4 → simplhdl-0.5.6}/src/simplhdl/resources/templates/vcs/vcs.parameters.j2 +0 -0
- {simplhdl-0.5.4 → simplhdl-0.5.6}/src/simplhdl/resources/templates/verible/__init__.py +0 -0
- {simplhdl-0.5.4 → simplhdl-0.5.6}/src/simplhdl/resources/templates/verible/rules.cfg.j2 +0 -0
- {simplhdl-0.5.4 → simplhdl-0.5.6}/src/simplhdl/resources/templates/vivado/__init__.py +0 -0
- {simplhdl-0.5.4 → simplhdl-0.5.6}/src/simplhdl/resources/templates/vivado/launch_run.sh.j2 +0 -0
- {simplhdl-0.5.4 → simplhdl-0.5.6}/src/simplhdl/resources/templates/vivado/project.tcl.j2 +0 -0
- {simplhdl-0.5.4 → simplhdl-0.5.6}/src/simplhdl/resources/templates/vivado/run.tcl.j2 +0 -0
- {simplhdl-0.5.4 → simplhdl-0.5.6}/src/simplhdl/resources/templates/vivado/steps.tcl.j2 +0 -0
- {simplhdl-0.5.4 → simplhdl-0.5.6}/src/simplhdl/resources/templates/vsg/__init__.py +0 -0
- {simplhdl-0.5.4 → simplhdl-0.5.6}/src/simplhdl/resources/templates/vsg/files.json.j2 +0 -0
- {simplhdl-0.5.4 → simplhdl-0.5.6}/src/simplhdl/resources/templates/vsg/rules.yml.j2 +0 -0
- {simplhdl-0.5.4 → simplhdl-0.5.6}/src/simplhdl/resources/templates/xsim/Makefile.j2 +0 -0
- {simplhdl-0.5.4 → simplhdl-0.5.6}/src/simplhdl/resources/templates/xsim/__init__.py +0 -0
- {simplhdl-0.5.4 → simplhdl-0.5.6}/src/simplhdl/resources/templates/xsim/cocotb.mk.j2 +0 -0
- {simplhdl-0.5.4 → simplhdl-0.5.6}/src/simplhdl/resources/templates/xsim/dependencies.mk.j2 +0 -0
- {simplhdl-0.5.4 → simplhdl-0.5.6}/src/simplhdl/resources/templates/xsim/files.j2 +0 -0
- {simplhdl-0.5.4 → simplhdl-0.5.6}/src/simplhdl/resources/templates/xsim/fileset.j2 +0 -0
- {simplhdl-0.5.4 → simplhdl-0.5.6}/src/simplhdl/resources/templates/xsim/project.mk.j2 +0 -0
- {simplhdl-0.5.4 → simplhdl-0.5.6}/src/simplhdl/run.py +0 -0
- {simplhdl-0.5.4 → simplhdl-0.5.6}/src/simplhdl/simplhdl.py +0 -0
- {simplhdl-0.5.4 → simplhdl-0.5.6}/src/simplhdl/tools.py +0 -0
- {simplhdl-0.5.4 → simplhdl-0.5.6}/tests/test_dummy.py +0 -0
- {simplhdl-0.5.4 → simplhdl-0.5.6}/tox.ini +0 -0
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__version__ = "0.5.6"
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UsedIn=UsedIn)
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ipfiles =
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for ipfile in
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logger.
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md5write(file.Path, filename=md5file)
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@@ -311,10 +321,18 @@ def copy_qsysfile(file: QuartusQSYSSpecificationFile, dest: Path) -> QuartusQSYS
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311
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Copy QSYS files to a directory and return a new QuartusQSYSSpecificationFile object with the new path.
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"""
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md5file = dest.joinpath(file.Path.name).with_suffix('.md5')
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314
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-
qsysdir = dest.joinpath(file.Path.name)
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|
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qsysdir = dest.joinpath(file.Path.name).with_suffix('')
|
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src = file.Path.parent
|
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|
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logger.debug(f"Copy {file.Path} to {qsysdir}")
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329
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+
# If destination is a subdirectory of source the copytree will have
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330
|
+
# to ignore this subdirectory
|
|
331
|
+
if qsysdir.absolute().is_relative_to(src.absolute()):
|
|
332
|
+
ignoredir = qsysdir.absolute().relative_to(src.absolute()).parents[-2]
|
|
333
|
+
copytree(str(src), str(qsysdir), dirs_exist_ok=True, ignore=ignore_patterns(ignoredir))
|
|
334
|
+
else:
|
|
335
|
+
copytree(str(src), str(qsysdir), dirs_exist_ok=True)
|
|
318
336
|
md5write(src, filename=md5file)
|
|
319
337
|
file._fileType = QuartusQSYSSpecificationFile
|
|
320
338
|
file._path = qsysdir.joinpath(file.Path.name).with_suffix('.qsys').resolve()
|
|
@@ -355,7 +373,7 @@ def unpack(file: Path, dest: Path) -> None:
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355
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"""
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356
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Unpack a file to a directory and return the new path.
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|
357
375
|
"""
|
|
358
|
-
md5file = dest.joinpath(file.name).with_suffix('.md5')
|
|
376
|
+
md5file = dest.parent.joinpath(file.name).with_suffix('.md5')
|
|
359
377
|
if not md5file.exists() or not md5check(file, filename=md5file):
|
|
360
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|
logger.info(f"Unpack {file} to {dest}")
|
|
361
379
|
with ZipFile(file, 'r') as zip:
|
|
@@ -39,15 +39,16 @@ class Design(pm.Design):
|
|
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39
39
|
@property
|
|
40
40
|
def TopLevel(self) -> str:
|
|
41
41
|
"""Property setting or returning the fileset's toplevel."""
|
|
42
|
-
top =
|
|
42
|
+
top = list()
|
|
43
43
|
if self._topLevel is not None:
|
|
44
44
|
for t in self._topLevel.split():
|
|
45
|
-
top.
|
|
45
|
+
top.append(t)
|
|
46
46
|
for fileset in self._fileSets.values():
|
|
47
47
|
if fileset.TopLevel is not None:
|
|
48
48
|
for t in fileset.TopLevel.split():
|
|
49
|
-
top.
|
|
50
|
-
|
|
49
|
+
top.append(t)
|
|
50
|
+
# remove duplicates without changing the order
|
|
51
|
+
return ' '.join(list(dict.fromkeys(top)))
|
|
51
52
|
|
|
52
53
|
@TopLevel.setter
|
|
53
54
|
def TopLevel(self, value: str) -> None:
|
|
@@ -17,7 +17,7 @@ class CalledShError(Exception):
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pass
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-
def sh(command: List[str], cwd: Optional[Path] = None, output=False, shell=False, env=None):
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+
def sh(command: List[str], cwd: Optional[Path] = None, output=False, shell=False, env=None, indent=2):
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if os.name == 'nt':
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shell = True
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@@ -26,7 +26,7 @@ def sh(command: List[str], cwd: Optional[Path] = None, output=False, shell=False
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if output:
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stdout: str = ''
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for line in p.stdout:
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-
sys.stdout.buffer.write(line)
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+
sys.stdout.buffer.write(b' '*indent + line)
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sys.stdout.buffer.flush()
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stdout += line.decode()
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_, stderr = p.communicate()
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@@ -1 +0,0 @@
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-
__version__ = "0.5.4"
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{simplhdl-0.5.4 → simplhdl-0.5.6}/examples/plugins/simple_parser/src/simple_parser/__init__.py
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{simplhdl-0.5.4 → simplhdl-0.5.6}/examples/plugins/simple_parser/src/simple_parser/simple_parser.py
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{simplhdl-0.5.4 → simplhdl-0.5.6}/src/simplhdl/resources/templates/modelsim/dependencies.mk.j2
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{simplhdl-0.5.4 → simplhdl-0.5.6}/src/simplhdl/resources/templates/questasim/modelsim.tcl.j2
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{simplhdl-0.5.4 → simplhdl-0.5.6}/src/simplhdl/resources/templates/questasim/project.qrun.j2
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{simplhdl-0.5.4 → simplhdl-0.5.6}/src/simplhdl/resources/templates/questasim/visualizer.tcl.j2
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{simplhdl-0.5.4 → simplhdl-0.5.6}/src/simplhdl/resources/templates/rivierapro/dependencies.mk.j2
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{simplhdl-0.5.4 → simplhdl-0.5.6}/src/simplhdl/resources/templates/vcs/synopsys_sim.setup.j2
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