SimplHDL 0.5.4__tar.gz → 0.5.6__tar.gz

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Files changed (202) hide show
  1. {simplhdl-0.5.4 → simplhdl-0.5.6}/PKG-INFO +1 -1
  2. {simplhdl-0.5.4 → simplhdl-0.5.6}/src/SimplHDL.egg-info/PKG-INFO +1 -1
  3. simplhdl-0.5.6/src/simplhdl/__init__.py +1 -0
  4. {simplhdl-0.5.4 → simplhdl-0.5.6}/src/simplhdl/__main__.py +14 -2
  5. {simplhdl-0.5.4 → simplhdl-0.5.6}/src/simplhdl/cocotb.py +8 -6
  6. {simplhdl-0.5.4 → simplhdl-0.5.6}/src/simplhdl/flow.py +7 -0
  7. {simplhdl-0.5.4 → simplhdl-0.5.6}/src/simplhdl/flows/flake8/flake8flow.py +1 -1
  8. {simplhdl-0.5.4 → simplhdl-0.5.6}/src/simplhdl/flows/verible/veribleflow.py +7 -4
  9. {simplhdl-0.5.4 → simplhdl-0.5.6}/src/simplhdl/flows/vsg/vsgflow.py +5 -2
  10. {simplhdl-0.5.4 → simplhdl-0.5.6}/src/simplhdl/generators/spd.py +28 -10
  11. {simplhdl-0.5.4 → simplhdl-0.5.6}/src/simplhdl/pyedaa/design.py +5 -4
  12. {simplhdl-0.5.4 → simplhdl-0.5.6}/src/simplhdl/utils.py +2 -2
  13. simplhdl-0.5.4/src/simplhdl/__init__.py +0 -1
  14. {simplhdl-0.5.4 → simplhdl-0.5.6}/.github/workflows/publish.yml +0 -0
  15. {simplhdl-0.5.4 → simplhdl-0.5.6}/.gitignore +0 -0
  16. {simplhdl-0.5.4 → simplhdl-0.5.6}/.readthedocs.yaml +0 -0
  17. {simplhdl-0.5.4 → simplhdl-0.5.6}/LICENSE +0 -0
  18. {simplhdl-0.5.4 → simplhdl-0.5.6}/README.md +0 -0
  19. {simplhdl-0.5.4 → simplhdl-0.5.6}/docs/_static/simplhdl_dark.png +0 -0
  20. {simplhdl-0.5.4 → simplhdl-0.5.6}/docs/_static/simplhdl_light.png +0 -0
  21. {simplhdl-0.5.4 → simplhdl-0.5.6}/docs/_static/simplhdl_light_1.png +0 -0
  22. {simplhdl-0.5.4 → simplhdl-0.5.6}/docs/conf.py +0 -0
  23. {simplhdl-0.5.4 → simplhdl-0.5.6}/docs/drawing.svg +0 -0
  24. {simplhdl-0.5.4 → simplhdl-0.5.6}/docs/flows/ghdl.rst +0 -0
  25. {simplhdl-0.5.4 → simplhdl-0.5.6}/docs/flows/icarus.rst +0 -0
  26. {simplhdl-0.5.4 → simplhdl-0.5.6}/docs/flows/quartus.rst +0 -0
  27. {simplhdl-0.5.4 → simplhdl-0.5.6}/docs/flows/questasim.rst +0 -0
  28. {simplhdl-0.5.4 → simplhdl-0.5.6}/docs/flows/vcs.rst +0 -0
  29. {simplhdl-0.5.4 → simplhdl-0.5.6}/docs/flows/vivado.rst +0 -0
  30. {simplhdl-0.5.4 → simplhdl-0.5.6}/docs/flows/xsim.rst +0 -0
  31. {simplhdl-0.5.4 → simplhdl-0.5.6}/docs/flows.rst +0 -0
  32. {simplhdl-0.5.4 → simplhdl-0.5.6}/docs/index.rst +0 -0
  33. {simplhdl-0.5.4 → simplhdl-0.5.6}/docs/intel-ips.md +0 -0
  34. {simplhdl-0.5.4 → simplhdl-0.5.6}/docs/introduction.rst +0 -0
  35. {simplhdl-0.5.4 → simplhdl-0.5.6}/docs/plugins.rst +0 -0
  36. {simplhdl-0.5.4 → simplhdl-0.5.6}/docs/requirements.txt +0 -0
  37. {simplhdl-0.5.4 → simplhdl-0.5.6}/examples/hdl/adder/adder.yml +0 -0
  38. {simplhdl-0.5.4 → simplhdl-0.5.6}/examples/hdl/adder/hdl/adder.sv +0 -0
  39. {simplhdl-0.5.4 → simplhdl-0.5.6}/examples/hdl/adder/sim/testbench.sv +0 -0
  40. {simplhdl-0.5.4 → simplhdl-0.5.6}/examples/hdl/adder/sim/testbench.yml +0 -0
  41. {simplhdl-0.5.4 → simplhdl-0.5.6}/examples/hdl/adder/syn/build.yml +0 -0
  42. {simplhdl-0.5.4 → simplhdl-0.5.6}/examples/hdl/adder/syn/placement.xdc +0 -0
  43. {simplhdl-0.5.4 → simplhdl-0.5.6}/examples/hdl/adder/syn/timing.xdc +0 -0
  44. {simplhdl-0.5.4 → simplhdl-0.5.6}/examples/hdl/adder/syn/top.sv +0 -0
  45. {simplhdl-0.5.4 → simplhdl-0.5.6}/examples/hdl/alu/alu.yml +0 -0
  46. {simplhdl-0.5.4 → simplhdl-0.5.6}/examples/hdl/alu/hdl/add.sv +0 -0
  47. {simplhdl-0.5.4 → simplhdl-0.5.6}/examples/hdl/alu/hdl/alu.sv +0 -0
  48. {simplhdl-0.5.4 → simplhdl-0.5.6}/examples/hdl/alu/hdl/mul.sv +0 -0
  49. {simplhdl-0.5.4 → simplhdl-0.5.6}/examples/hdl/alu/hdl/sub.sv +0 -0
  50. {simplhdl-0.5.4 → simplhdl-0.5.6}/examples/hdl/alu/sim/pyuvm/alu_vip/__init__.py +0 -0
  51. {simplhdl-0.5.4 → simplhdl-0.5.6}/examples/hdl/alu/sim/pyuvm/alu_vip/agent.py +0 -0
  52. {simplhdl-0.5.4 → simplhdl-0.5.6}/examples/hdl/alu/sim/pyuvm/alu_vip/aluif.py +0 -0
  53. {simplhdl-0.5.4 → simplhdl-0.5.6}/examples/hdl/alu/sim/pyuvm/alu_vip/driver.py +0 -0
  54. {simplhdl-0.5.4 → simplhdl-0.5.6}/examples/hdl/alu/sim/pyuvm/alu_vip/monitor.py +0 -0
  55. {simplhdl-0.5.4 → simplhdl-0.5.6}/examples/hdl/alu/sim/pyuvm/alu_vip/sequenceitem.py +0 -0
  56. {simplhdl-0.5.4 → simplhdl-0.5.6}/examples/hdl/alu/sim/pyuvm/alu_vip/sequencer.py +0 -0
  57. {simplhdl-0.5.4 → simplhdl-0.5.6}/examples/hdl/alu/sim/pyuvm/clock_vip/__init__.py +0 -0
  58. {simplhdl-0.5.4 → simplhdl-0.5.6}/examples/hdl/alu/sim/pyuvm/clock_vip/agent.py +0 -0
  59. {simplhdl-0.5.4 → simplhdl-0.5.6}/examples/hdl/alu/sim/pyuvm/clock_vip/clockif.py +0 -0
  60. {simplhdl-0.5.4 → simplhdl-0.5.6}/examples/hdl/alu/sim/pyuvm/pyuvm.yml +0 -0
  61. {simplhdl-0.5.4 → simplhdl-0.5.6}/examples/hdl/alu/sim/pyuvm/test/__init__.py +0 -0
  62. {simplhdl-0.5.4 → simplhdl-0.5.6}/examples/hdl/alu/sim/pyuvm/test/env.py +0 -0
  63. {simplhdl-0.5.4 → simplhdl-0.5.6}/examples/hdl/alu/sim/pyuvm/test/seq_lib.py +0 -0
  64. {simplhdl-0.5.4 → simplhdl-0.5.6}/examples/hdl/alu/sim/pyuvm/test/test.py +0 -0
  65. {simplhdl-0.5.4 → simplhdl-0.5.6}/examples/hdl/alu/sim/pyuvm/testbench.py +0 -0
  66. {simplhdl-0.5.4 → simplhdl-0.5.6}/examples/hdl/alu/sim/uvm/alu_vip/agent.svh +0 -0
  67. {simplhdl-0.5.4 → simplhdl-0.5.6}/examples/hdl/alu/sim/uvm/alu_vip/alu_vip.sv +0 -0
  68. {simplhdl-0.5.4 → simplhdl-0.5.6}/examples/hdl/alu/sim/uvm/alu_vip/alu_vip.yml +0 -0
  69. {simplhdl-0.5.4 → simplhdl-0.5.6}/examples/hdl/alu/sim/uvm/alu_vip/driver.svh +0 -0
  70. {simplhdl-0.5.4 → simplhdl-0.5.6}/examples/hdl/alu/sim/uvm/alu_vip/env.svh +0 -0
  71. {simplhdl-0.5.4 → simplhdl-0.5.6}/examples/hdl/alu/sim/uvm/alu_vip/monitor.svh +0 -0
  72. {simplhdl-0.5.4 → simplhdl-0.5.6}/examples/hdl/alu/sim/uvm/alu_vip/sequence_item.svh +0 -0
  73. {simplhdl-0.5.4 → simplhdl-0.5.6}/examples/hdl/alu/sim/uvm/tb_env/seq_lib/add_seq.svh +0 -0
  74. {simplhdl-0.5.4 → simplhdl-0.5.6}/examples/hdl/alu/sim/uvm/tb_env/seq_lib/base_seq.svh +0 -0
  75. {simplhdl-0.5.4 → simplhdl-0.5.6}/examples/hdl/alu/sim/uvm/tb_env/tb_env.sv +0 -0
  76. {simplhdl-0.5.4 → simplhdl-0.5.6}/examples/hdl/alu/sim/uvm/tb_env/tb_env.yml +0 -0
  77. {simplhdl-0.5.4 → simplhdl-0.5.6}/examples/hdl/alu/sim/uvm/tb_env/test/base_test.svh +0 -0
  78. {simplhdl-0.5.4 → simplhdl-0.5.6}/examples/hdl/alu/sim/uvm/tb_env/test/test_add.svh +0 -0
  79. {simplhdl-0.5.4 → simplhdl-0.5.6}/examples/hdl/alu/sim/uvm/testbench/alu_if.sv +0 -0
  80. {simplhdl-0.5.4 → simplhdl-0.5.6}/examples/hdl/alu/sim/uvm/testbench/testbench.sv +0 -0
  81. {simplhdl-0.5.4 → simplhdl-0.5.6}/examples/hdl/alu/sim/uvm/testbench/testbench.yml +0 -0
  82. {simplhdl-0.5.4 → simplhdl-0.5.6}/examples/hdl/alu/sim/uvm/testcases/test_add/test_add.yml +0 -0
  83. {simplhdl-0.5.4 → simplhdl-0.5.6}/examples/hdl/alu/syn/build.yml +0 -0
  84. {simplhdl-0.5.4 → simplhdl-0.5.6}/examples/hdl/alu/syn/placement.xdc +0 -0
  85. {simplhdl-0.5.4 → simplhdl-0.5.6}/examples/hdl/alu/syn/timing.xdc +0 -0
  86. {simplhdl-0.5.4 → simplhdl-0.5.6}/examples/hdl/hello/build.sbt +0 -0
  87. {simplhdl-0.5.4 → simplhdl-0.5.6}/examples/hdl/hello/hello.yml +0 -0
  88. {simplhdl-0.5.4 → simplhdl-0.5.6}/examples/hdl/hello/src/main/scala/Hello.scala +0 -0
  89. {simplhdl-0.5.4 → simplhdl-0.5.6}/examples/hdl/hello/syn/build.yml +0 -0
  90. {simplhdl-0.5.4 → simplhdl-0.5.6}/examples/plugins/simple_parser/setup.py +0 -0
  91. {simplhdl-0.5.4 → simplhdl-0.5.6}/examples/plugins/simple_parser/src/simple_parser/__init__.py +0 -0
  92. {simplhdl-0.5.4 → simplhdl-0.5.6}/examples/plugins/simple_parser/src/simple_parser/simple_parser.py +0 -0
  93. {simplhdl-0.5.4 → simplhdl-0.5.6}/pyproject.toml +0 -0
  94. {simplhdl-0.5.4 → simplhdl-0.5.6}/setup.cfg +0 -0
  95. {simplhdl-0.5.4 → simplhdl-0.5.6}/src/SimplHDL.egg-info/SOURCES.txt +0 -0
  96. {simplhdl-0.5.4 → simplhdl-0.5.6}/src/SimplHDL.egg-info/dependency_links.txt +0 -0
  97. {simplhdl-0.5.4 → simplhdl-0.5.6}/src/SimplHDL.egg-info/entry_points.txt +0 -0
  98. {simplhdl-0.5.4 → simplhdl-0.5.6}/src/SimplHDL.egg-info/requires.txt +0 -0
  99. {simplhdl-0.5.4 → simplhdl-0.5.6}/src/SimplHDL.egg-info/top_level.txt +0 -0
  100. {simplhdl-0.5.4 → simplhdl-0.5.6}/src/simplhdl/flows/__init__.py +0 -0
  101. {simplhdl-0.5.4 → simplhdl-0.5.6}/src/simplhdl/flows/encrypt/__init__.py +0 -0
  102. {simplhdl-0.5.4 → simplhdl-0.5.6}/src/simplhdl/flows/encrypt/encryptflow.py +0 -0
  103. {simplhdl-0.5.4 → simplhdl-0.5.6}/src/simplhdl/flows/implementationflow.py +0 -0
  104. {simplhdl-0.5.4 → simplhdl-0.5.6}/src/simplhdl/flows/lint/lintflow.py +0 -0
  105. {simplhdl-0.5.4 → simplhdl-0.5.6}/src/simplhdl/flows/modelsim/__init__.py +0 -0
  106. {simplhdl-0.5.4 → simplhdl-0.5.6}/src/simplhdl/flows/modelsim/modelsimflow.py +0 -0
  107. {simplhdl-0.5.4 → simplhdl-0.5.6}/src/simplhdl/flows/quartusdse/__init__.py +0 -0
  108. {simplhdl-0.5.4 → simplhdl-0.5.6}/src/simplhdl/flows/quartusdse/quartusdseflow.py +0 -0
  109. {simplhdl-0.5.4 → simplhdl-0.5.6}/src/simplhdl/flows/quartusexport/__init__.py +0 -0
  110. {simplhdl-0.5.4 → simplhdl-0.5.6}/src/simplhdl/flows/quartusexport/quartusexportflow.py +0 -0
  111. {simplhdl-0.5.4 → simplhdl-0.5.6}/src/simplhdl/flows/quartusflow.py +0 -0
  112. {simplhdl-0.5.4 → simplhdl-0.5.6}/src/simplhdl/flows/questasim/__init__.py +0 -0
  113. {simplhdl-0.5.4 → simplhdl-0.5.6}/src/simplhdl/flows/questasim/questasimflow.py +0 -0
  114. {simplhdl-0.5.4 → simplhdl-0.5.6}/src/simplhdl/flows/rivierapro/__init__.py +0 -0
  115. {simplhdl-0.5.4 → simplhdl-0.5.6}/src/simplhdl/flows/rivierapro/rivieraproflow.py +0 -0
  116. {simplhdl-0.5.4 → simplhdl-0.5.6}/src/simplhdl/flows/simulationflow.py +0 -0
  117. {simplhdl-0.5.4 → simplhdl-0.5.6}/src/simplhdl/flows/vcs/__init__.py +0 -0
  118. {simplhdl-0.5.4 → simplhdl-0.5.6}/src/simplhdl/flows/vcs/vcsflow.py +0 -0
  119. {simplhdl-0.5.4 → simplhdl-0.5.6}/src/simplhdl/flows/verible/__init__.py +0 -0
  120. {simplhdl-0.5.4 → simplhdl-0.5.6}/src/simplhdl/flows/vivadoflow.py +0 -0
  121. {simplhdl-0.5.4 → simplhdl-0.5.6}/src/simplhdl/flows/vsg/__init__.py +0 -0
  122. {simplhdl-0.5.4 → simplhdl-0.5.6}/src/simplhdl/flows/xsim/__init__.py +0 -0
  123. {simplhdl-0.5.4 → simplhdl-0.5.6}/src/simplhdl/flows/xsim/xsimflow.py +0 -0
  124. {simplhdl-0.5.4 → simplhdl-0.5.6}/src/simplhdl/generator.py +0 -0
  125. {simplhdl-0.5.4 → simplhdl-0.5.6}/src/simplhdl/generators/__init__.py +0 -0
  126. {simplhdl-0.5.4 → simplhdl-0.5.6}/src/simplhdl/generators/chisel.py +0 -0
  127. {simplhdl-0.5.4 → simplhdl-0.5.6}/src/simplhdl/generators/ipxact.py +0 -0
  128. {simplhdl-0.5.4 → simplhdl-0.5.6}/src/simplhdl/generators/systemrdl.py +0 -0
  129. {simplhdl-0.5.4 → simplhdl-0.5.6}/src/simplhdl/info.py +0 -0
  130. {simplhdl-0.5.4 → simplhdl-0.5.6}/src/simplhdl/parser.py +0 -0
  131. {simplhdl-0.5.4 → simplhdl-0.5.6}/src/simplhdl/parsers/__init__.py +0 -0
  132. {simplhdl-0.5.4 → simplhdl-0.5.6}/src/simplhdl/parsers/fusesocparser.py +0 -0
  133. {simplhdl-0.5.4 → simplhdl-0.5.6}/src/simplhdl/parsers/simplhdlparser.py +0 -0
  134. {simplhdl-0.5.4 → simplhdl-0.5.6}/src/simplhdl/plugins.py +0 -0
  135. {simplhdl-0.5.4 → simplhdl-0.5.6}/src/simplhdl/pyedaa/__init__.py +0 -0
  136. {simplhdl-0.5.4 → simplhdl-0.5.6}/src/simplhdl/pyedaa/attributes.py +0 -0
  137. {simplhdl-0.5.4 → simplhdl-0.5.6}/src/simplhdl/pyedaa/fileset.py +0 -0
  138. {simplhdl-0.5.4 → simplhdl-0.5.6}/src/simplhdl/pyedaa/filetypes.py +0 -0
  139. {simplhdl-0.5.4 → simplhdl-0.5.6}/src/simplhdl/pyedaa/project.py +0 -0
  140. {simplhdl-0.5.4 → simplhdl-0.5.6}/src/simplhdl/pyedaa/target.py +0 -0
  141. {simplhdl-0.5.4 → simplhdl-0.5.6}/src/simplhdl/pyedaa/vhdllibrary.py +0 -0
  142. {simplhdl-0.5.4 → simplhdl-0.5.6}/src/simplhdl/repo.py +0 -0
  143. {simplhdl-0.5.4 → simplhdl-0.5.6}/src/simplhdl/resources/__init__.py +0 -0
  144. {simplhdl-0.5.4 → simplhdl-0.5.6}/src/simplhdl/resources/templates/__init__.py +0 -0
  145. {simplhdl-0.5.4 → simplhdl-0.5.6}/src/simplhdl/resources/templates/flake8/__init__.py +0 -0
  146. {simplhdl-0.5.4 → simplhdl-0.5.6}/src/simplhdl/resources/templates/flake8/setup.cfg.j2 +0 -0
  147. {simplhdl-0.5.4 → simplhdl-0.5.6}/src/simplhdl/resources/templates/modelsim/Makefile.j2 +0 -0
  148. {simplhdl-0.5.4 → simplhdl-0.5.6}/src/simplhdl/resources/templates/modelsim/__init__.py +0 -0
  149. {simplhdl-0.5.4 → simplhdl-0.5.6}/src/simplhdl/resources/templates/modelsim/cocotb.mk.j2 +0 -0
  150. {simplhdl-0.5.4 → simplhdl-0.5.6}/src/simplhdl/resources/templates/modelsim/dependencies.mk.j2 +0 -0
  151. {simplhdl-0.5.4 → simplhdl-0.5.6}/src/simplhdl/resources/templates/modelsim/files.j2 +0 -0
  152. {simplhdl-0.5.4 → simplhdl-0.5.6}/src/simplhdl/resources/templates/modelsim/fileset.j2 +0 -0
  153. {simplhdl-0.5.4 → simplhdl-0.5.6}/src/simplhdl/resources/templates/modelsim/modelsim.tcl.j2 +0 -0
  154. {simplhdl-0.5.4 → simplhdl-0.5.6}/src/simplhdl/resources/templates/modelsim/project.mk.j2 +0 -0
  155. {simplhdl-0.5.4 → simplhdl-0.5.6}/src/simplhdl/resources/templates/modelsim/run.do.j2 +0 -0
  156. {simplhdl-0.5.4 → simplhdl-0.5.6}/src/simplhdl/resources/templates/quartus/__init__.py +0 -0
  157. {simplhdl-0.5.4 → simplhdl-0.5.6}/src/simplhdl/resources/templates/quartus/project.tcl.j2 +0 -0
  158. {simplhdl-0.5.4 → simplhdl-0.5.6}/src/simplhdl/resources/templates/quartus/run.tcl.j2 +0 -0
  159. {simplhdl-0.5.4 → simplhdl-0.5.6}/src/simplhdl/resources/templates/questasim/__init__.py +0 -0
  160. {simplhdl-0.5.4 → simplhdl-0.5.6}/src/simplhdl/resources/templates/questasim/modelsim.tcl.j2 +0 -0
  161. {simplhdl-0.5.4 → simplhdl-0.5.6}/src/simplhdl/resources/templates/questasim/project.qrun.j2 +0 -0
  162. {simplhdl-0.5.4 → simplhdl-0.5.6}/src/simplhdl/resources/templates/questasim/visualizer.tcl.j2 +0 -0
  163. {simplhdl-0.5.4 → simplhdl-0.5.6}/src/simplhdl/resources/templates/questasim/vsim-run.do.j2 +0 -0
  164. {simplhdl-0.5.4 → simplhdl-0.5.6}/src/simplhdl/resources/templates/rivierapro/Makefile.j2 +0 -0
  165. {simplhdl-0.5.4 → simplhdl-0.5.6}/src/simplhdl/resources/templates/rivierapro/__init__.py +0 -0
  166. {simplhdl-0.5.4 → simplhdl-0.5.6}/src/simplhdl/resources/templates/rivierapro/cocotb.mk.j2 +0 -0
  167. {simplhdl-0.5.4 → simplhdl-0.5.6}/src/simplhdl/resources/templates/rivierapro/dependencies.mk.j2 +0 -0
  168. {simplhdl-0.5.4 → simplhdl-0.5.6}/src/simplhdl/resources/templates/rivierapro/files.j2 +0 -0
  169. {simplhdl-0.5.4 → simplhdl-0.5.6}/src/simplhdl/resources/templates/rivierapro/fileset.j2 +0 -0
  170. {simplhdl-0.5.4 → simplhdl-0.5.6}/src/simplhdl/resources/templates/rivierapro/project.mk.j2 +0 -0
  171. {simplhdl-0.5.4 → simplhdl-0.5.6}/src/simplhdl/resources/templates/vcs/Makefile.j2 +0 -0
  172. {simplhdl-0.5.4 → simplhdl-0.5.6}/src/simplhdl/resources/templates/vcs/__init__.py +0 -0
  173. {simplhdl-0.5.4 → simplhdl-0.5.6}/src/simplhdl/resources/templates/vcs/cocotb.mk.j2 +0 -0
  174. {simplhdl-0.5.4 → simplhdl-0.5.6}/src/simplhdl/resources/templates/vcs/dependencies.mk.j2 +0 -0
  175. {simplhdl-0.5.4 → simplhdl-0.5.6}/src/simplhdl/resources/templates/vcs/files.j2 +0 -0
  176. {simplhdl-0.5.4 → simplhdl-0.5.6}/src/simplhdl/resources/templates/vcs/fileset.j2 +0 -0
  177. {simplhdl-0.5.4 → simplhdl-0.5.6}/src/simplhdl/resources/templates/vcs/pli.tab.j2 +0 -0
  178. {simplhdl-0.5.4 → simplhdl-0.5.6}/src/simplhdl/resources/templates/vcs/project.mk.j2 +0 -0
  179. {simplhdl-0.5.4 → simplhdl-0.5.6}/src/simplhdl/resources/templates/vcs/synopsys_sim.setup.j2 +0 -0
  180. {simplhdl-0.5.4 → simplhdl-0.5.6}/src/simplhdl/resources/templates/vcs/vcs.parameters.j2 +0 -0
  181. {simplhdl-0.5.4 → simplhdl-0.5.6}/src/simplhdl/resources/templates/verible/__init__.py +0 -0
  182. {simplhdl-0.5.4 → simplhdl-0.5.6}/src/simplhdl/resources/templates/verible/rules.cfg.j2 +0 -0
  183. {simplhdl-0.5.4 → simplhdl-0.5.6}/src/simplhdl/resources/templates/vivado/__init__.py +0 -0
  184. {simplhdl-0.5.4 → simplhdl-0.5.6}/src/simplhdl/resources/templates/vivado/launch_run.sh.j2 +0 -0
  185. {simplhdl-0.5.4 → simplhdl-0.5.6}/src/simplhdl/resources/templates/vivado/project.tcl.j2 +0 -0
  186. {simplhdl-0.5.4 → simplhdl-0.5.6}/src/simplhdl/resources/templates/vivado/run.tcl.j2 +0 -0
  187. {simplhdl-0.5.4 → simplhdl-0.5.6}/src/simplhdl/resources/templates/vivado/steps.tcl.j2 +0 -0
  188. {simplhdl-0.5.4 → simplhdl-0.5.6}/src/simplhdl/resources/templates/vsg/__init__.py +0 -0
  189. {simplhdl-0.5.4 → simplhdl-0.5.6}/src/simplhdl/resources/templates/vsg/files.json.j2 +0 -0
  190. {simplhdl-0.5.4 → simplhdl-0.5.6}/src/simplhdl/resources/templates/vsg/rules.yml.j2 +0 -0
  191. {simplhdl-0.5.4 → simplhdl-0.5.6}/src/simplhdl/resources/templates/xsim/Makefile.j2 +0 -0
  192. {simplhdl-0.5.4 → simplhdl-0.5.6}/src/simplhdl/resources/templates/xsim/__init__.py +0 -0
  193. {simplhdl-0.5.4 → simplhdl-0.5.6}/src/simplhdl/resources/templates/xsim/cocotb.mk.j2 +0 -0
  194. {simplhdl-0.5.4 → simplhdl-0.5.6}/src/simplhdl/resources/templates/xsim/dependencies.mk.j2 +0 -0
  195. {simplhdl-0.5.4 → simplhdl-0.5.6}/src/simplhdl/resources/templates/xsim/files.j2 +0 -0
  196. {simplhdl-0.5.4 → simplhdl-0.5.6}/src/simplhdl/resources/templates/xsim/fileset.j2 +0 -0
  197. {simplhdl-0.5.4 → simplhdl-0.5.6}/src/simplhdl/resources/templates/xsim/project.mk.j2 +0 -0
  198. {simplhdl-0.5.4 → simplhdl-0.5.6}/src/simplhdl/run.py +0 -0
  199. {simplhdl-0.5.4 → simplhdl-0.5.6}/src/simplhdl/simplhdl.py +0 -0
  200. {simplhdl-0.5.4 → simplhdl-0.5.6}/src/simplhdl/tools.py +0 -0
  201. {simplhdl-0.5.4 → simplhdl-0.5.6}/tests/test_dummy.py +0 -0
  202. {simplhdl-0.5.4 → simplhdl-0.5.6}/tox.ini +0 -0
@@ -1,6 +1,6 @@
1
1
  Metadata-Version: 2.4
2
2
  Name: SimplHDL
3
- Version: 0.5.4
3
+ Version: 0.5.6
4
4
  Summary: A framework for simulating and implementing HDL designs
5
5
  Author-email: Rasmus Grøndahl Olsen <simplhdl@gmail.com>
6
6
  Maintainer-email: Rasmus Grøndahl Olsen <simplhdl@gmail.com>
@@ -1,6 +1,6 @@
1
1
  Metadata-Version: 2.4
2
2
  Name: SimplHDL
3
- Version: 0.5.4
3
+ Version: 0.5.6
4
4
  Summary: A framework for simulating and implementing HDL designs
5
5
  Author-email: Rasmus Grøndahl Olsen <simplhdl@gmail.com>
6
6
  Maintainer-email: Rasmus Grøndahl Olsen <simplhdl@gmail.com>
@@ -0,0 +1 @@
1
+ __version__ = "0.5.6"
@@ -5,8 +5,9 @@ import logging
5
5
  import traceback
6
6
 
7
7
  from typing import Sequence
8
-
9
8
  from pathlib import Path
9
+ from rich.logging import RichHandler
10
+
10
11
  from . import __version__
11
12
  from .simplhdl import Simplhdl
12
13
  from .plugins import load_plugins
@@ -67,7 +68,18 @@ def main():
67
68
  args = parse_arguments()
68
69
  levels = [logging.INFO, logging.DEBUG, logging.NOTSET]
69
70
  level = levels[min(args.verbose, len(levels)-1)]
70
- logging.basicConfig(level=level)
71
+ if level < logging.INFO:
72
+ show_path = True
73
+ else:
74
+ show_path = False
75
+
76
+ FORMAT = "[simplhdl.%(module)s] - %(message)s"
77
+ console = RichHandler(level=level, show_time=False, rich_tracebacks=True, show_path=show_path)
78
+ logging.basicConfig(
79
+ level=5,
80
+ format=FORMAT,
81
+ handlers=[console]
82
+ )
71
83
  simpl = Simplhdl(args)
72
84
  simpl.run()
73
85
  except (NotImplementedError, FileNotFoundError, CalledShError,
@@ -41,7 +41,7 @@ class Cocotb:
41
41
  return None
42
42
  set_ = set()
43
43
  try:
44
- modules = self.project.DefaultDesign._topLevel.split()
44
+ modules = self.project.DefaultDesign.TopLevel.split()
45
45
  except AttributeError:
46
46
  raise FlowError("No top levels found")
47
47
 
@@ -58,14 +58,14 @@ class Cocotb:
58
58
 
59
59
  def hdltoplevels(self) -> str:
60
60
  tops = []
61
- for t in self.project.DefaultDesign._topLevel.split():
61
+ for t in self.project.DefaultDesign.TopLevel.split():
62
62
  if t != self.top:
63
63
  tops.append(t)
64
64
  return ' '.join(tops)
65
65
 
66
66
  def get_dut(self) -> str:
67
67
  try:
68
- for top in self.project.DefaultDesign._topLevel.split():
68
+ for top in self.project.DefaultDesign.TopLevel.split():
69
69
  if top != self.top:
70
70
  return top
71
71
  except AttributeError:
@@ -97,13 +97,15 @@ class Cocotb:
97
97
  with open(file.Path, 'r', errors='replace') as f:
98
98
  lines = f.readlines()
99
99
  for line in lines:
100
- if re.search(rf'^\s*module\s+{name}(\s+|\(|;|$)', line):
100
+ if re.search(rf'^\s*module\s+{name}(\s+|#\(|\(|;|$)', line):
101
101
  if file.Library.Name == lib:
102
102
  logger.info(f"Cocotb dut '{self.dut}' is Verilog")
103
103
  return VerilogSourceFile
104
104
  else:
105
- logger.warning(f"Found HDL module {name} in ",
106
- f"library '{file.Library.Name}' expected '{lib}'")
105
+ logger.warning(
106
+ f"Found HDL module {name} in "
107
+ f"library '{file.Library.Name}' expected '{lib}'"
108
+ )
107
109
  else:
108
110
  continue
109
111
  except UnicodeDecodeError:
@@ -1,3 +1,5 @@
1
+ import logging
2
+
1
3
  from argparse import Namespace
2
4
  from pathlib import Path
3
5
  from typing import Callable, Dict, Set
@@ -16,6 +18,11 @@ class FlowBase(metaclass=ABCMeta):
16
18
  self.builddir: Path = builddir
17
19
  self.category: FlowCategory = FlowCategory.DEFAULT
18
20
  self.tools: Set = set()
21
+ self.builddir.mkdir(parents=True, exist_ok=True)
22
+ file = logging.FileHandler(self.builddir.joinpath('simplhdl.log'), mode='w')
23
+ file.setLevel(logging.NOTSET)
24
+ file.setFormatter(logging.Formatter('%(asctime)s - %(levelname)s:%(filename)s:%(lineno)d - %(message)s'))
25
+ logging.getLogger().addHandler(file)
19
26
 
20
27
  @classmethod
21
28
  @abstractmethod
@@ -49,7 +49,7 @@ class Flake8Flow(FlowBase):
49
49
  self.files = [f.Path for f in self.project.DefaultDesign.DefaultFileSet.Files(PythonSourceFile)]
50
50
 
51
51
  def generate(self):
52
- config = os.getenv('SIMPLHDL_FLAKE8_RULES')
52
+ config = os.getenv('SIMPLHDL_FLAKE8_CONFIG')
53
53
  if config:
54
54
  shutil.copy(config, self.builddir.joinpath('setup.cfg'))
55
55
  else:
@@ -8,7 +8,7 @@ from argparse import Namespace
8
8
  from pathlib import Path
9
9
  from jinja2 import Environment, FileSystemLoader
10
10
 
11
- from simplhdl.flow import FlowFactory, FlowBase
11
+ from simplhdl.flow import FlowFactory, FlowBase, FlowError
12
12
  from simplhdl.resources.templates import verible as templates
13
13
  from simplhdl.utils import sh, CalledShError, generate_from_template
14
14
  from simplhdl.pyedaa import VerilogIncludeFile, VerilogSourceFile, SystemVerilogSourceFile
@@ -51,8 +51,11 @@ class VeribleFlow(FlowBase):
51
51
  def generate(self):
52
52
  if self.args.rules:
53
53
  self.rules = self.args.rules
54
- elif os.getenv('SIMPLHDL_VERIBLE_RULES'):
55
- self.rules = self.args.rules
54
+ elif os.getenv('SIMPLHDL_VERIBLE_CONFIG'):
55
+ rules = os.getenv('SIMPLHDL_VERIBLE_CONFIG')
56
+ if not Path(rules).exists():
57
+ raise FlowError(f"Rules file {rules} does not exist")
58
+ self.rules = rules
56
59
  else:
57
60
  templatedir = resources_files(self.templates)
58
61
  environment = Environment(
@@ -67,7 +70,7 @@ class VeribleFlow(FlowBase):
67
70
  command = [
68
71
  "verible-verilog-lint",
69
72
  "--check_syntax=false",
70
- "--ruleset=all",
73
+ "--ruleset=none",
71
74
  "--rules_config", self.rules
72
75
  ]
73
76
 
@@ -74,8 +74,11 @@ class VsgFlow(FlowBase):
74
74
  UsedIn=UsedIn)
75
75
  if self.args.rules:
76
76
  self.rules = self.args.rules
77
- elif os.getenv('SIMPLHDL_VSG_RULES'):
78
- self.rules = self.args.rules
77
+ elif os.getenv('SIMPLHDL_VSG_CONFIG'):
78
+ rules = os.getenv('SIMPLHDL_VSG_CONFIG')
79
+ if not Path(rules).exists():
80
+ raise FlowError(f"Rules file {rules} does not exist")
81
+ self.rules = rules
79
82
  else:
80
83
  template = environment.get_template('rules.yml.j2')
81
84
  generate_from_template(template, self.builddir)
@@ -5,7 +5,7 @@ from typing import List, Generator, Optional
5
5
  from pathlib import Path
6
6
  from xml.etree.ElementTree import Element, parse
7
7
  from zipfile import ZipFile
8
- from shutil import copy, copytree, rmtree
8
+ from shutil import copy, copytree, rmtree, ignore_patterns
9
9
 
10
10
  from simplhdl.pyedaa import (
11
11
  File,
@@ -72,6 +72,7 @@ class Spd:
72
72
  sh(command, cwd=filename.parent)
73
73
  if not spdfile.exists():
74
74
  raise FileNotFoundError(f"{spdfile}: doesn't exits")
75
+ logger.debug(f"Parse {spdfile}")
75
76
  self.tree = parse(spdfile)
76
77
  self.root = self.tree.getroot()
77
78
  self.location = spdfile.parent.absolute()
@@ -222,7 +223,7 @@ class QuartusIP(GeneratorBase):
222
223
  seen[fileid] = file
223
224
 
224
225
 
225
- def parse_qsys(filename: QuartusQSYSSpecificationFile) -> List[File]:
226
+ def get_list_of_ipfiles(filename: QuartusQSYSSpecificationFile) -> List[File]:
226
227
  """
227
228
  Search for IP files in a QSYS file and return a list of QuartusIPSpecificationFile objects.
228
229
  """
@@ -234,6 +235,15 @@ def parse_qsys(filename: QuartusQSYSSpecificationFile) -> List[File]:
234
235
  if m:
235
236
  ipfile = filename.Path.parent.joinpath(m.group(1))
236
237
  if ipfile.exists():
238
+ logger.debug(f"Found {ipfile} in {filename.Path}")
239
+ files.append(QuartusIPSpecificationFile(ipfile))
240
+ else:
241
+ logger.warning(f"File {ipfile} not found")
242
+ m = re.search(r'<parameter name="logicalView">(.*\.ip)</parameter>', line)
243
+ if m:
244
+ ipfile = filename.Path.parent.joinpath(m.group(1))
245
+ if ipfile.exists():
246
+ logger.debug(f"Found {ipfile} in {filename.Path}")
237
247
  files.append(QuartusIPSpecificationFile(ipfile))
238
248
  else:
239
249
  logger.warning(f"File {ipfile} not found")
@@ -244,10 +254,10 @@ def qsys_to_fileset(file: QuartusQSYSSpecificationFile, flow: FlowBase, library)
244
254
  """
245
255
  Parse a QSYS file and return a FileSet object.
246
256
  """
247
- ipfiles = parse_qsys(file)
257
+ ipfiles = get_list_of_ipfiles(file)
248
258
  if flow.category == FlowCategory.SIMULATION:
249
259
  parent = file.FileSet
250
- for ipfile in ipfiles + [file]:
260
+ for ipfile in [file] + ipfiles:
251
261
  spd = Spd(ipfile.Path, flow, file.Path.parent.absolute())
252
262
  for fileset in reversed(spd.filesets):
253
263
  # Add fileset to parent, then set parent to fileset to make a chain
@@ -290,14 +300,14 @@ def copy_ipfile(file: QuartusIPSpecificationFile, dest: Path) -> QuartusIPSpecif
290
300
  destfile = dest.joinpath(file.Path.name)
291
301
  if srcdir.exists():
292
302
  if not md5file.exists() or not md5check(file.Path, srcdir, filename=md5file):
293
- logger.info(f"Copy {file.Path} to {destfile}")
294
- logger.info(f"Copy {srcdir} to {destdir}")
303
+ logger.debug(f"Copy {file.Path} to {destfile}")
304
+ logger.debug(f"Copy {srcdir} to {destdir}")
295
305
  copy(str(file.Path), str(destfile))
296
306
  copytree(str(srcdir), str(destdir), dirs_exist_ok=True)
297
307
  md5write(file.Path, srcdir, filename=md5file)
298
308
  else:
299
309
  if not md5file.exists() or not md5check(file.Path, filename=md5file):
300
- logger.info(f"Copy {file.Path} to {destfile}")
310
+ logger.debug(f"Copy {file.Path} to {destfile}")
301
311
  rmtree(destdir, ignore_errors=True)
302
312
  copy(str(file.Path), str(destfile))
303
313
  md5write(file.Path, filename=md5file)
@@ -311,10 +321,18 @@ def copy_qsysfile(file: QuartusQSYSSpecificationFile, dest: Path) -> QuartusQSYS
311
321
  Copy QSYS files to a directory and return a new QuartusQSYSSpecificationFile object with the new path.
312
322
  """
313
323
  md5file = dest.joinpath(file.Path.name).with_suffix('.md5')
314
- qsysdir = dest.joinpath(file.Path.name)
324
+ qsysdir = dest.joinpath(file.Path.name).with_suffix('')
325
+
315
326
  src = file.Path.parent
316
327
  if not md5file.exists() or not md5check(src, filename=md5file):
317
- copytree(str(src), str(qsysdir), dirs_exist_ok=True)
328
+ logger.debug(f"Copy {file.Path} to {qsysdir}")
329
+ # If destination is a subdirectory of source the copytree will have
330
+ # to ignore this subdirectory
331
+ if qsysdir.absolute().is_relative_to(src.absolute()):
332
+ ignoredir = qsysdir.absolute().relative_to(src.absolute()).parents[-2]
333
+ copytree(str(src), str(qsysdir), dirs_exist_ok=True, ignore=ignore_patterns(ignoredir))
334
+ else:
335
+ copytree(str(src), str(qsysdir), dirs_exist_ok=True)
318
336
  md5write(src, filename=md5file)
319
337
  file._fileType = QuartusQSYSSpecificationFile
320
338
  file._path = qsysdir.joinpath(file.Path.name).with_suffix('.qsys').resolve()
@@ -355,7 +373,7 @@ def unpack(file: Path, dest: Path) -> None:
355
373
  """
356
374
  Unpack a file to a directory and return the new path.
357
375
  """
358
- md5file = dest.joinpath(file.name).with_suffix('.md5')
376
+ md5file = dest.parent.joinpath(file.name).with_suffix('.md5')
359
377
  if not md5file.exists() or not md5check(file, filename=md5file):
360
378
  logger.info(f"Unpack {file} to {dest}")
361
379
  with ZipFile(file, 'r') as zip:
@@ -39,15 +39,16 @@ class Design(pm.Design):
39
39
  @property
40
40
  def TopLevel(self) -> str:
41
41
  """Property setting or returning the fileset's toplevel."""
42
- top = set()
42
+ top = list()
43
43
  if self._topLevel is not None:
44
44
  for t in self._topLevel.split():
45
- top.add(t)
45
+ top.append(t)
46
46
  for fileset in self._fileSets.values():
47
47
  if fileset.TopLevel is not None:
48
48
  for t in fileset.TopLevel.split():
49
- top.add(t)
50
- return ' '.join(top)
49
+ top.append(t)
50
+ # remove duplicates without changing the order
51
+ return ' '.join(list(dict.fromkeys(top)))
51
52
 
52
53
  @TopLevel.setter
53
54
  def TopLevel(self, value: str) -> None:
@@ -17,7 +17,7 @@ class CalledShError(Exception):
17
17
  pass
18
18
 
19
19
 
20
- def sh(command: List[str], cwd: Optional[Path] = None, output=False, shell=False, env=None):
20
+ def sh(command: List[str], cwd: Optional[Path] = None, output=False, shell=False, env=None, indent=2):
21
21
  if os.name == 'nt':
22
22
  shell = True
23
23
 
@@ -26,7 +26,7 @@ def sh(command: List[str], cwd: Optional[Path] = None, output=False, shell=False
26
26
  if output:
27
27
  stdout: str = ''
28
28
  for line in p.stdout:
29
- sys.stdout.buffer.write(line)
29
+ sys.stdout.buffer.write(b' '*indent + line)
30
30
  sys.stdout.buffer.flush()
31
31
  stdout += line.decode()
32
32
  _, stderr = p.communicate()
@@ -1 +0,0 @@
1
- __version__ = "0.5.4"
File without changes
File without changes
File without changes
File without changes
File without changes
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