SimplHDL 0.3.0__tar.gz → 0.5.0__tar.gz
This diff represents the content of publicly available package versions that have been released to one of the supported registries. The information contained in this diff is provided for informational purposes only and reflects changes between package versions as they appear in their respective public registries.
- {simplhdl-0.3.0 → simplhdl-0.5.0}/PKG-INFO +2 -1
- {simplhdl-0.3.0 → simplhdl-0.5.0}/pyproject.toml +1 -0
- {simplhdl-0.3.0 → simplhdl-0.5.0}/src/SimplHDL.egg-info/PKG-INFO +2 -1
- {simplhdl-0.3.0 → simplhdl-0.5.0}/src/SimplHDL.egg-info/SOURCES.txt +4 -0
- simplhdl-0.5.0/src/simplhdl/__init__.py +1 -0
- {simplhdl-0.3.0 → simplhdl-0.5.0}/src/simplhdl/cocotb.py +6 -3
- simplhdl-0.5.0/src/simplhdl/flows/encrypt/encryptflow.py +129 -0
- simplhdl-0.5.0/src/simplhdl/flows/quartusexport/quartusexportflow.py +157 -0
- {simplhdl-0.3.0 → simplhdl-0.5.0}/src/simplhdl/flows/quartusflow.py +7 -6
- simplhdl-0.5.0/src/simplhdl/generators/spd.py +362 -0
- {simplhdl-0.3.0 → simplhdl-0.5.0}/src/simplhdl/plugins.py +2 -0
- {simplhdl-0.3.0 → simplhdl-0.5.0}/src/simplhdl/pyedaa/__init__.py +11 -0
- {simplhdl-0.3.0 → simplhdl-0.5.0}/src/simplhdl/pyedaa/design.py +15 -1
- {simplhdl-0.3.0 → simplhdl-0.5.0}/src/simplhdl/resources/templates/quartus/project.tcl.j2 +16 -2
- {simplhdl-0.3.0 → simplhdl-0.5.0}/src/simplhdl/resources/templates/questasim/project.qrun.j2 +2 -0
- simplhdl-0.5.0/src/simplhdl/resources/templates/vsg/__init__.py +0 -0
- simplhdl-0.5.0/src/simplhdl/resources/templates/xsim/__init__.py +0 -0
- simplhdl-0.3.0/src/simplhdl/__init__.py +0 -1
- simplhdl-0.3.0/src/simplhdl/generators/spd.py +0 -211
- {simplhdl-0.3.0 → simplhdl-0.5.0}/.github/workflows/publish.yml +0 -0
- {simplhdl-0.3.0 → simplhdl-0.5.0}/.gitignore +0 -0
- {simplhdl-0.3.0 → simplhdl-0.5.0}/.readthedocs.yaml +0 -0
- {simplhdl-0.3.0 → simplhdl-0.5.0}/LICENSE +0 -0
- {simplhdl-0.3.0 → simplhdl-0.5.0}/README.md +0 -0
- {simplhdl-0.3.0 → simplhdl-0.5.0}/docs/_static/simplhdl_dark.png +0 -0
- {simplhdl-0.3.0 → simplhdl-0.5.0}/docs/_static/simplhdl_light.png +0 -0
- {simplhdl-0.3.0 → simplhdl-0.5.0}/docs/_static/simplhdl_light_1.png +0 -0
- {simplhdl-0.3.0 → simplhdl-0.5.0}/docs/conf.py +0 -0
- {simplhdl-0.3.0 → simplhdl-0.5.0}/docs/drawing.svg +0 -0
- {simplhdl-0.3.0 → simplhdl-0.5.0}/docs/flows/ghdl.rst +0 -0
- {simplhdl-0.3.0 → simplhdl-0.5.0}/docs/flows/icarus.rst +0 -0
- {simplhdl-0.3.0 → simplhdl-0.5.0}/docs/flows/quartus.rst +0 -0
- {simplhdl-0.3.0 → simplhdl-0.5.0}/docs/flows/questasim.rst +0 -0
- {simplhdl-0.3.0 → simplhdl-0.5.0}/docs/flows/vcs.rst +0 -0
- {simplhdl-0.3.0 → simplhdl-0.5.0}/docs/flows/vivado.rst +0 -0
- {simplhdl-0.3.0 → simplhdl-0.5.0}/docs/flows/xsim.rst +0 -0
- {simplhdl-0.3.0 → simplhdl-0.5.0}/docs/flows.rst +0 -0
- {simplhdl-0.3.0 → simplhdl-0.5.0}/docs/index.rst +0 -0
- {simplhdl-0.3.0 → simplhdl-0.5.0}/docs/intel-ips.md +0 -0
- {simplhdl-0.3.0 → simplhdl-0.5.0}/docs/introduction.rst +0 -0
- {simplhdl-0.3.0 → simplhdl-0.5.0}/docs/plugins.rst +0 -0
- {simplhdl-0.3.0 → simplhdl-0.5.0}/docs/requirements.txt +0 -0
- {simplhdl-0.3.0 → simplhdl-0.5.0}/examples/hdl/adder/adder.yml +0 -0
- {simplhdl-0.3.0 → simplhdl-0.5.0}/examples/hdl/adder/hdl/adder.sv +0 -0
- {simplhdl-0.3.0 → simplhdl-0.5.0}/examples/hdl/adder/sim/testbench.sv +0 -0
- {simplhdl-0.3.0 → simplhdl-0.5.0}/examples/hdl/adder/sim/testbench.yml +0 -0
- {simplhdl-0.3.0 → simplhdl-0.5.0}/examples/hdl/adder/syn/build.yml +0 -0
- {simplhdl-0.3.0 → simplhdl-0.5.0}/examples/hdl/adder/syn/placement.xdc +0 -0
- {simplhdl-0.3.0 → simplhdl-0.5.0}/examples/hdl/adder/syn/timing.xdc +0 -0
- {simplhdl-0.3.0 → simplhdl-0.5.0}/examples/hdl/adder/syn/top.sv +0 -0
- {simplhdl-0.3.0 → simplhdl-0.5.0}/examples/hdl/alu/alu.yml +0 -0
- {simplhdl-0.3.0 → simplhdl-0.5.0}/examples/hdl/alu/hdl/add.sv +0 -0
- {simplhdl-0.3.0 → simplhdl-0.5.0}/examples/hdl/alu/hdl/alu.sv +0 -0
- {simplhdl-0.3.0 → simplhdl-0.5.0}/examples/hdl/alu/hdl/mul.sv +0 -0
- {simplhdl-0.3.0 → simplhdl-0.5.0}/examples/hdl/alu/hdl/sub.sv +0 -0
- {simplhdl-0.3.0 → simplhdl-0.5.0}/examples/hdl/alu/sim/pyuvm/alu_vip/__init__.py +0 -0
- {simplhdl-0.3.0 → simplhdl-0.5.0}/examples/hdl/alu/sim/pyuvm/alu_vip/agent.py +0 -0
- {simplhdl-0.3.0 → simplhdl-0.5.0}/examples/hdl/alu/sim/pyuvm/alu_vip/aluif.py +0 -0
- {simplhdl-0.3.0 → simplhdl-0.5.0}/examples/hdl/alu/sim/pyuvm/alu_vip/driver.py +0 -0
- {simplhdl-0.3.0 → simplhdl-0.5.0}/examples/hdl/alu/sim/pyuvm/alu_vip/monitor.py +0 -0
- {simplhdl-0.3.0 → simplhdl-0.5.0}/examples/hdl/alu/sim/pyuvm/alu_vip/sequenceitem.py +0 -0
- {simplhdl-0.3.0 → simplhdl-0.5.0}/examples/hdl/alu/sim/pyuvm/alu_vip/sequencer.py +0 -0
- {simplhdl-0.3.0 → simplhdl-0.5.0}/examples/hdl/alu/sim/pyuvm/clock_vip/__init__.py +0 -0
- {simplhdl-0.3.0 → simplhdl-0.5.0}/examples/hdl/alu/sim/pyuvm/clock_vip/agent.py +0 -0
- {simplhdl-0.3.0 → simplhdl-0.5.0}/examples/hdl/alu/sim/pyuvm/clock_vip/clockif.py +0 -0
- {simplhdl-0.3.0 → simplhdl-0.5.0}/examples/hdl/alu/sim/pyuvm/pyuvm.yml +0 -0
- {simplhdl-0.3.0 → simplhdl-0.5.0}/examples/hdl/alu/sim/pyuvm/test/__init__.py +0 -0
- {simplhdl-0.3.0 → simplhdl-0.5.0}/examples/hdl/alu/sim/pyuvm/test/env.py +0 -0
- {simplhdl-0.3.0 → simplhdl-0.5.0}/examples/hdl/alu/sim/pyuvm/test/seq_lib.py +0 -0
- {simplhdl-0.3.0 → simplhdl-0.5.0}/examples/hdl/alu/sim/pyuvm/test/test.py +0 -0
- {simplhdl-0.3.0 → simplhdl-0.5.0}/examples/hdl/alu/sim/pyuvm/testbench.py +0 -0
- {simplhdl-0.3.0 → simplhdl-0.5.0}/examples/hdl/alu/sim/uvm/alu_vip/agent.svh +0 -0
- {simplhdl-0.3.0 → simplhdl-0.5.0}/examples/hdl/alu/sim/uvm/alu_vip/alu_vip.sv +0 -0
- {simplhdl-0.3.0 → simplhdl-0.5.0}/examples/hdl/alu/sim/uvm/alu_vip/alu_vip.yml +0 -0
- {simplhdl-0.3.0 → simplhdl-0.5.0}/examples/hdl/alu/sim/uvm/alu_vip/driver.svh +0 -0
- {simplhdl-0.3.0 → simplhdl-0.5.0}/examples/hdl/alu/sim/uvm/alu_vip/env.svh +0 -0
- {simplhdl-0.3.0 → simplhdl-0.5.0}/examples/hdl/alu/sim/uvm/alu_vip/monitor.svh +0 -0
- {simplhdl-0.3.0 → simplhdl-0.5.0}/examples/hdl/alu/sim/uvm/alu_vip/sequence_item.svh +0 -0
- {simplhdl-0.3.0 → simplhdl-0.5.0}/examples/hdl/alu/sim/uvm/tb_env/seq_lib/add_seq.svh +0 -0
- {simplhdl-0.3.0 → simplhdl-0.5.0}/examples/hdl/alu/sim/uvm/tb_env/seq_lib/base_seq.svh +0 -0
- {simplhdl-0.3.0 → simplhdl-0.5.0}/examples/hdl/alu/sim/uvm/tb_env/tb_env.sv +0 -0
- {simplhdl-0.3.0 → simplhdl-0.5.0}/examples/hdl/alu/sim/uvm/tb_env/tb_env.yml +0 -0
- {simplhdl-0.3.0 → simplhdl-0.5.0}/examples/hdl/alu/sim/uvm/tb_env/test/base_test.svh +0 -0
- {simplhdl-0.3.0 → simplhdl-0.5.0}/examples/hdl/alu/sim/uvm/tb_env/test/test_add.svh +0 -0
- {simplhdl-0.3.0 → simplhdl-0.5.0}/examples/hdl/alu/sim/uvm/testbench/alu_if.sv +0 -0
- {simplhdl-0.3.0 → simplhdl-0.5.0}/examples/hdl/alu/sim/uvm/testbench/testbench.sv +0 -0
- {simplhdl-0.3.0 → simplhdl-0.5.0}/examples/hdl/alu/sim/uvm/testbench/testbench.yml +0 -0
- {simplhdl-0.3.0 → simplhdl-0.5.0}/examples/hdl/alu/sim/uvm/testcases/test_add/test_add.yml +0 -0
- {simplhdl-0.3.0 → simplhdl-0.5.0}/examples/hdl/alu/syn/build.yml +0 -0
- {simplhdl-0.3.0 → simplhdl-0.5.0}/examples/hdl/alu/syn/placement.xdc +0 -0
- {simplhdl-0.3.0 → simplhdl-0.5.0}/examples/hdl/alu/syn/timing.xdc +0 -0
- {simplhdl-0.3.0 → simplhdl-0.5.0}/examples/hdl/hello/build.sbt +0 -0
- {simplhdl-0.3.0 → simplhdl-0.5.0}/examples/hdl/hello/hello.yml +0 -0
- {simplhdl-0.3.0 → simplhdl-0.5.0}/examples/hdl/hello/src/main/scala/Hello.scala +0 -0
- {simplhdl-0.3.0 → simplhdl-0.5.0}/examples/hdl/hello/syn/build.yml +0 -0
- {simplhdl-0.3.0 → simplhdl-0.5.0}/examples/plugins/simple_parser/setup.py +0 -0
- {simplhdl-0.3.0 → simplhdl-0.5.0}/examples/plugins/simple_parser/src/simple_parser/__init__.py +0 -0
- {simplhdl-0.3.0 → simplhdl-0.5.0}/examples/plugins/simple_parser/src/simple_parser/simple_parser.py +0 -0
- {simplhdl-0.3.0 → simplhdl-0.5.0}/setup.cfg +0 -0
- {simplhdl-0.3.0 → simplhdl-0.5.0}/src/SimplHDL.egg-info/dependency_links.txt +0 -0
- {simplhdl-0.3.0 → simplhdl-0.5.0}/src/SimplHDL.egg-info/entry_points.txt +0 -0
- {simplhdl-0.3.0 → simplhdl-0.5.0}/src/SimplHDL.egg-info/requires.txt +0 -0
- {simplhdl-0.3.0 → simplhdl-0.5.0}/src/SimplHDL.egg-info/top_level.txt +0 -0
- {simplhdl-0.3.0 → simplhdl-0.5.0}/src/simplhdl/__main__.py +0 -0
- {simplhdl-0.3.0 → simplhdl-0.5.0}/src/simplhdl/flow.py +0 -0
- {simplhdl-0.3.0 → simplhdl-0.5.0}/src/simplhdl/flows/__init__.py +0 -0
- {simplhdl-0.3.0/src/simplhdl/flows/modelsim → simplhdl-0.5.0/src/simplhdl/flows/encrypt}/__init__.py +0 -0
- {simplhdl-0.3.0 → simplhdl-0.5.0}/src/simplhdl/flows/flake8/flake8flow.py +0 -0
- {simplhdl-0.3.0 → simplhdl-0.5.0}/src/simplhdl/flows/implementationflow.py +0 -0
- {simplhdl-0.3.0 → simplhdl-0.5.0}/src/simplhdl/flows/lint/lintflow.py +0 -0
- {simplhdl-0.3.0/src/simplhdl/flows/quartusdse → simplhdl-0.5.0/src/simplhdl/flows/modelsim}/__init__.py +0 -0
- {simplhdl-0.3.0 → simplhdl-0.5.0}/src/simplhdl/flows/modelsim/modelsimflow.py +0 -0
- {simplhdl-0.3.0/src/simplhdl/flows/questasim → simplhdl-0.5.0/src/simplhdl/flows/quartusdse}/__init__.py +0 -0
- {simplhdl-0.3.0 → simplhdl-0.5.0}/src/simplhdl/flows/quartusdse/quartusdseflow.py +0 -0
- {simplhdl-0.3.0/src/simplhdl/flows/rivierapro → simplhdl-0.5.0/src/simplhdl/flows/quartusexport}/__init__.py +0 -0
- {simplhdl-0.3.0/src/simplhdl/flows/vcs → simplhdl-0.5.0/src/simplhdl/flows/questasim}/__init__.py +0 -0
- {simplhdl-0.3.0 → simplhdl-0.5.0}/src/simplhdl/flows/questasim/questasimflow.py +0 -0
- {simplhdl-0.3.0/src/simplhdl/flows/verible → simplhdl-0.5.0/src/simplhdl/flows/rivierapro}/__init__.py +0 -0
- {simplhdl-0.3.0 → simplhdl-0.5.0}/src/simplhdl/flows/rivierapro/rivieraproflow.py +0 -0
- {simplhdl-0.3.0 → simplhdl-0.5.0}/src/simplhdl/flows/simulationflow.py +0 -0
- {simplhdl-0.3.0/src/simplhdl/flows/vsg → simplhdl-0.5.0/src/simplhdl/flows/vcs}/__init__.py +0 -0
- {simplhdl-0.3.0 → simplhdl-0.5.0}/src/simplhdl/flows/vcs/vcsflow.py +0 -0
- {simplhdl-0.3.0/src/simplhdl/flows/xsim → simplhdl-0.5.0/src/simplhdl/flows/verible}/__init__.py +0 -0
- {simplhdl-0.3.0 → simplhdl-0.5.0}/src/simplhdl/flows/verible/veribleflow.py +0 -0
- {simplhdl-0.3.0 → simplhdl-0.5.0}/src/simplhdl/flows/vivadoflow.py +0 -0
- {simplhdl-0.3.0/src/simplhdl/generators → simplhdl-0.5.0/src/simplhdl/flows/vsg}/__init__.py +0 -0
- {simplhdl-0.3.0 → simplhdl-0.5.0}/src/simplhdl/flows/vsg/vsgflow.py +0 -0
- {simplhdl-0.3.0/src/simplhdl/parsers → simplhdl-0.5.0/src/simplhdl/flows/xsim}/__init__.py +0 -0
- {simplhdl-0.3.0 → simplhdl-0.5.0}/src/simplhdl/flows/xsim/xsimflow.py +0 -0
- {simplhdl-0.3.0 → simplhdl-0.5.0}/src/simplhdl/generator.py +0 -0
- {simplhdl-0.3.0/src/simplhdl/resources → simplhdl-0.5.0/src/simplhdl/generators}/__init__.py +0 -0
- {simplhdl-0.3.0 → simplhdl-0.5.0}/src/simplhdl/generators/chisel.py +0 -0
- {simplhdl-0.3.0 → simplhdl-0.5.0}/src/simplhdl/generators/ipxact.py +0 -0
- {simplhdl-0.3.0 → simplhdl-0.5.0}/src/simplhdl/generators/systemrdl.py +0 -0
- {simplhdl-0.3.0 → simplhdl-0.5.0}/src/simplhdl/info.py +0 -0
- {simplhdl-0.3.0 → simplhdl-0.5.0}/src/simplhdl/parser.py +0 -0
- {simplhdl-0.3.0/src/simplhdl/resources/templates → simplhdl-0.5.0/src/simplhdl/parsers}/__init__.py +0 -0
- {simplhdl-0.3.0 → simplhdl-0.5.0}/src/simplhdl/parsers/fusesocparser.py +0 -0
- {simplhdl-0.3.0 → simplhdl-0.5.0}/src/simplhdl/parsers/simplhdlparser.py +0 -0
- {simplhdl-0.3.0 → simplhdl-0.5.0}/src/simplhdl/pyedaa/attributes.py +0 -0
- {simplhdl-0.3.0 → simplhdl-0.5.0}/src/simplhdl/pyedaa/fileset.py +0 -0
- {simplhdl-0.3.0 → simplhdl-0.5.0}/src/simplhdl/pyedaa/filetypes.py +0 -0
- {simplhdl-0.3.0 → simplhdl-0.5.0}/src/simplhdl/pyedaa/project.py +0 -0
- {simplhdl-0.3.0 → simplhdl-0.5.0}/src/simplhdl/pyedaa/target.py +0 -0
- {simplhdl-0.3.0 → simplhdl-0.5.0}/src/simplhdl/pyedaa/vhdllibrary.py +0 -0
- {simplhdl-0.3.0 → simplhdl-0.5.0}/src/simplhdl/repo.py +0 -0
- {simplhdl-0.3.0/src/simplhdl/resources/templates/flake8 → simplhdl-0.5.0/src/simplhdl/resources}/__init__.py +0 -0
- {simplhdl-0.3.0/src/simplhdl/resources/templates/modelsim → simplhdl-0.5.0/src/simplhdl/resources/templates}/__init__.py +0 -0
- {simplhdl-0.3.0/src/simplhdl/resources/templates/quartus → simplhdl-0.5.0/src/simplhdl/resources/templates/flake8}/__init__.py +0 -0
- {simplhdl-0.3.0 → simplhdl-0.5.0}/src/simplhdl/resources/templates/flake8/setup.cfg.j2 +0 -0
- {simplhdl-0.3.0 → simplhdl-0.5.0}/src/simplhdl/resources/templates/modelsim/Makefile.j2 +0 -0
- {simplhdl-0.3.0/src/simplhdl/resources/templates/questasim → simplhdl-0.5.0/src/simplhdl/resources/templates/modelsim}/__init__.py +0 -0
- {simplhdl-0.3.0 → simplhdl-0.5.0}/src/simplhdl/resources/templates/modelsim/cocotb.mk.j2 +0 -0
- {simplhdl-0.3.0 → simplhdl-0.5.0}/src/simplhdl/resources/templates/modelsim/dependencies.mk.j2 +0 -0
- {simplhdl-0.3.0 → simplhdl-0.5.0}/src/simplhdl/resources/templates/modelsim/files.j2 +0 -0
- {simplhdl-0.3.0 → simplhdl-0.5.0}/src/simplhdl/resources/templates/modelsim/fileset.j2 +0 -0
- {simplhdl-0.3.0 → simplhdl-0.5.0}/src/simplhdl/resources/templates/modelsim/modelsim.tcl.j2 +0 -0
- {simplhdl-0.3.0 → simplhdl-0.5.0}/src/simplhdl/resources/templates/modelsim/project.mk.j2 +0 -0
- {simplhdl-0.3.0 → simplhdl-0.5.0}/src/simplhdl/resources/templates/modelsim/run.do.j2 +0 -0
- {simplhdl-0.3.0/src/simplhdl/resources/templates/rivierapro → simplhdl-0.5.0/src/simplhdl/resources/templates/quartus}/__init__.py +0 -0
- {simplhdl-0.3.0 → simplhdl-0.5.0}/src/simplhdl/resources/templates/quartus/run.tcl.j2 +0 -0
- {simplhdl-0.3.0/src/simplhdl/resources/templates/vcs → simplhdl-0.5.0/src/simplhdl/resources/templates/questasim}/__init__.py +0 -0
- {simplhdl-0.3.0 → simplhdl-0.5.0}/src/simplhdl/resources/templates/questasim/modelsim.tcl.j2 +0 -0
- {simplhdl-0.3.0 → simplhdl-0.5.0}/src/simplhdl/resources/templates/questasim/visualizer.tcl.j2 +0 -0
- {simplhdl-0.3.0 → simplhdl-0.5.0}/src/simplhdl/resources/templates/questasim/vsim-run.do.j2 +0 -0
- {simplhdl-0.3.0 → simplhdl-0.5.0}/src/simplhdl/resources/templates/rivierapro/Makefile.j2 +0 -0
- {simplhdl-0.3.0/src/simplhdl/resources/templates/verible → simplhdl-0.5.0/src/simplhdl/resources/templates/rivierapro}/__init__.py +0 -0
- {simplhdl-0.3.0 → simplhdl-0.5.0}/src/simplhdl/resources/templates/rivierapro/cocotb.mk.j2 +0 -0
- {simplhdl-0.3.0 → simplhdl-0.5.0}/src/simplhdl/resources/templates/rivierapro/dependencies.mk.j2 +0 -0
- {simplhdl-0.3.0 → simplhdl-0.5.0}/src/simplhdl/resources/templates/rivierapro/files.j2 +0 -0
- {simplhdl-0.3.0 → simplhdl-0.5.0}/src/simplhdl/resources/templates/rivierapro/fileset.j2 +0 -0
- {simplhdl-0.3.0 → simplhdl-0.5.0}/src/simplhdl/resources/templates/rivierapro/project.mk.j2 +0 -0
- {simplhdl-0.3.0 → simplhdl-0.5.0}/src/simplhdl/resources/templates/vcs/Makefile.j2 +0 -0
- {simplhdl-0.3.0/src/simplhdl/resources/templates/vivado → simplhdl-0.5.0/src/simplhdl/resources/templates/vcs}/__init__.py +0 -0
- {simplhdl-0.3.0 → simplhdl-0.5.0}/src/simplhdl/resources/templates/vcs/cocotb.mk.j2 +0 -0
- {simplhdl-0.3.0 → simplhdl-0.5.0}/src/simplhdl/resources/templates/vcs/dependencies.mk.j2 +0 -0
- {simplhdl-0.3.0 → simplhdl-0.5.0}/src/simplhdl/resources/templates/vcs/files.j2 +0 -0
- {simplhdl-0.3.0 → simplhdl-0.5.0}/src/simplhdl/resources/templates/vcs/fileset.j2 +0 -0
- {simplhdl-0.3.0 → simplhdl-0.5.0}/src/simplhdl/resources/templates/vcs/pli.tab.j2 +0 -0
- {simplhdl-0.3.0 → simplhdl-0.5.0}/src/simplhdl/resources/templates/vcs/project.mk.j2 +0 -0
- {simplhdl-0.3.0 → simplhdl-0.5.0}/src/simplhdl/resources/templates/vcs/synopsys_sim.setup.j2 +0 -0
- {simplhdl-0.3.0 → simplhdl-0.5.0}/src/simplhdl/resources/templates/vcs/vcs.parameters.j2 +0 -0
- {simplhdl-0.3.0/src/simplhdl/resources/templates/vsg → simplhdl-0.5.0/src/simplhdl/resources/templates/verible}/__init__.py +0 -0
- {simplhdl-0.3.0 → simplhdl-0.5.0}/src/simplhdl/resources/templates/verible/rules.cfg.j2 +0 -0
- {simplhdl-0.3.0/src/simplhdl/resources/templates/xsim → simplhdl-0.5.0/src/simplhdl/resources/templates/vivado}/__init__.py +0 -0
- {simplhdl-0.3.0 → simplhdl-0.5.0}/src/simplhdl/resources/templates/vivado/launch_run.sh.j2 +0 -0
- {simplhdl-0.3.0 → simplhdl-0.5.0}/src/simplhdl/resources/templates/vivado/project.tcl.j2 +0 -0
- {simplhdl-0.3.0 → simplhdl-0.5.0}/src/simplhdl/resources/templates/vivado/run.tcl.j2 +0 -0
- {simplhdl-0.3.0 → simplhdl-0.5.0}/src/simplhdl/resources/templates/vivado/steps.tcl.j2 +0 -0
- {simplhdl-0.3.0 → simplhdl-0.5.0}/src/simplhdl/resources/templates/vsg/files.json.j2 +0 -0
- {simplhdl-0.3.0 → simplhdl-0.5.0}/src/simplhdl/resources/templates/vsg/rules.yml.j2 +0 -0
- {simplhdl-0.3.0 → simplhdl-0.5.0}/src/simplhdl/resources/templates/xsim/Makefile.j2 +0 -0
- {simplhdl-0.3.0 → simplhdl-0.5.0}/src/simplhdl/resources/templates/xsim/cocotb.mk.j2 +0 -0
- {simplhdl-0.3.0 → simplhdl-0.5.0}/src/simplhdl/resources/templates/xsim/dependencies.mk.j2 +0 -0
- {simplhdl-0.3.0 → simplhdl-0.5.0}/src/simplhdl/resources/templates/xsim/files.j2 +0 -0
- {simplhdl-0.3.0 → simplhdl-0.5.0}/src/simplhdl/resources/templates/xsim/fileset.j2 +0 -0
- {simplhdl-0.3.0 → simplhdl-0.5.0}/src/simplhdl/resources/templates/xsim/project.mk.j2 +0 -0
- {simplhdl-0.3.0 → simplhdl-0.5.0}/src/simplhdl/run.py +0 -0
- {simplhdl-0.3.0 → simplhdl-0.5.0}/src/simplhdl/simplhdl.py +0 -0
- {simplhdl-0.3.0 → simplhdl-0.5.0}/src/simplhdl/tools.py +0 -0
- {simplhdl-0.3.0 → simplhdl-0.5.0}/src/simplhdl/utils.py +0 -0
- {simplhdl-0.3.0 → simplhdl-0.5.0}/tests/test_dummy.py +0 -0
- {simplhdl-0.3.0 → simplhdl-0.5.0}/tox.ini +0 -0
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Metadata-Version: 2.2
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Name: SimplHDL
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Classifier: Programming Language :: Python :: 3.13
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Classifier: Operating System :: OS Independent
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Summary: A framework for simulating and implementing HDL designs
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Author-email: Rasmus Grøndahl Olsen <simplhdl@gmail.com>
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Classifier: Intended Audience :: Developers
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Classifier: License :: OSI Approved :: MIT License
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@@ -103,12 +103,16 @@ src/simplhdl/flows/implementationflow.py
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src/simplhdl/flows/simulationflow.py
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src/simplhdl/flows/vivadoflow.py
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src/simplhdl/flows/encrypt/__init__.py
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src/simplhdl/flows/encrypt/encryptflow.py
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src/simplhdl/flows/flake8/flake8flow.py
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src/simplhdl/flows/lint/lintflow.py
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src/simplhdl/flows/quartusexport/__init__.py
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src/simplhdl/flows/quartusexport/quartusexportflow.py
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src/simplhdl/flows/questasim/__init__.py
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src/simplhdl/flows/questasim/questasimflow.py
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src/simplhdl/flows/rivierapro/__init__.py
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__version__ = "0.5.0"
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@@ -64,9 +64,12 @@ class Cocotb:
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return ' '.join(tops)
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def get_dut(self) -> str:
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try:
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for top in self.project.DefaultDesign._topLevel.split():
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if top != self.top:
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return top
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except AttributeError:
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raise FlowError("No top levels found")
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def hdltype(self): # noqa: C901
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logger.debug(f"Cocotb hdl dut '{self.dut}'")
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import shutil
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import logging
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from typing import List
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from argparse import Namespace
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from pathlib import Path
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from simplhdl.flow import FlowFactory, FlowTools, FlowError
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from simplhdl.flows.implementationflow import ImplementationFlow
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from simplhdl.utils import sh
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from simplhdl.pyedaa.project import Project
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from simplhdl.pyedaa import SystemVerilogSourceFile, VerilogSourceFile, VHDLSourceFile, VerilogIncludeFile
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logger = logging.getLogger(__name__)
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VENDORS = ["cadence", "mentor", "synopsys", "spyglass", "dsim", "veloce", "dcfcf"]
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@FlowFactory.register('encrypt')
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class EncryptFlow(ImplementationFlow):
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@classmethod
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def parse_args(self, subparsers) -> None:
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parser = subparsers.add_parser('encrypt', help='Encrypt HDL source for diffent tool vendors')
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parser.add_argument(
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'--inplace',
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action='store_true',
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help="Place the encrypted file next to the source file"
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)
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parser.add_argument(
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'--no-encrypt',
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action='store_true',
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help="Disable encryption"
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)
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parser.add_argument(
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'--vendors',
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action='store',
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nargs='+',
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choices=VENDORS,
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help="Vendor list to support"
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)
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parser.add_argument(
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'--outputdir',
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type=Path,
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dest='outdir',
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action='store',
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help='Output directory'
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)
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def __init__(self, name, args: Namespace, project: Project, builddir: Path):
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super().__init__(name, args, project, builddir)
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self.tools.add(FlowTools.QUARTUS)
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if self.args.inplace and self.args.no_encrypt:
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raise FlowError("Both --inplace and --no-encrypt options are enabled.")
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def run(self) -> None:
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self.configure()
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self.execute()
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def configure(self) -> None:
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self.is_tool_setup()
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def execute(self):
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outputdir = self.args.outdir or self.builddir
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outputdir.mkdir(parents=True, exist_ok=True)
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for file in self.project.DefaultDesign.Files():
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if file.FileType in [SystemVerilogSourceFile, VerilogIncludeFile]:
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language = "systemverilog"
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elif file.FileType == VerilogSourceFile:
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language = "verilog"
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elif file.FileType == VHDLSourceFile:
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language = "vhdl"
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else:
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continue
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if self.args.no_encrypt:
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destFile = outputdir.joinpath(file.Path.name)
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elif self.args.inplace:
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destFile = file.Path.with_suffix(f"{file.Path.suffix}p")
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else:
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destFile = outputdir.joinpath(file.Path.name).with_suffix(f"{file.Path.suffix}p")
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+
|
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85
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if self.args.vendors:
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vendors = self.args.vendors
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else:
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vendors = VENDORS
|
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+
|
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90
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+
if self.args.no_encrypt:
|
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91
|
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shutil.copyfile(file.Path.absolute(), destFile.absolute())
|
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else:
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93
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encrypt(file.Path, destFile, language, vendors)
|
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+
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95
|
+
def is_tool_setup(self) -> None:
|
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96
|
+
exit: bool = False
|
|
97
|
+
if shutil.which('encrypt_1735') is None:
|
|
98
|
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logger.error('encrypt_1735: not found in PATH')
|
|
99
|
+
exit = True
|
|
100
|
+
if exit:
|
|
101
|
+
raise FileNotFoundError("Quartus is not setup correctly")
|
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103
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+
|
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104
|
+
def encrypt(src: Path, dst: Path, language: str, vendors: List[str]) -> Path:
|
|
105
|
+
"""
|
|
106
|
+
Encrypt a HDL source file using the 'encrypt_1735' tool.
|
|
107
|
+
|
|
108
|
+
Parameters:
|
|
109
|
+
src (Path): The source file path of the HDL file to be encrypted.
|
|
110
|
+
dst (Path): The destination file path or directory for the encrypted file.
|
|
111
|
+
If dst is a directory, the source file name is appended.
|
|
112
|
+
language (str): The language type of the HDL file (e.g., "systemverilog", "verilog", "vhdl").
|
|
113
|
+
vendors (List[str]): A list of vendor names used to set up the simulation options.
|
|
114
|
+
|
|
115
|
+
Returns:
|
|
116
|
+
Path: The absolute path to the encrypted file.
|
|
117
|
+
|
|
118
|
+
Example:
|
|
119
|
+
encrypted_path = encrypt(Path("/path/to/source.v"), Path("/path/to/output"), "verilog", ["cadence", "mentor"])
|
|
120
|
+
"""
|
|
121
|
+
destFile = dst.joinpath(src.name) if dst.is_dir() else dst
|
|
122
|
+
command = [
|
|
123
|
+
"encrypt_1735", str(src.absolute()),
|
|
124
|
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"--language", language,
|
|
125
|
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"--quartus",
|
|
126
|
+
f"--simulation={','.join(vendors)}",
|
|
127
|
+
"-of", f"{destFile.absolute()}"
|
|
128
|
+
]
|
|
129
|
+
sh(command, output=True)
|
|
@@ -0,0 +1,157 @@
|
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1
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import shutil
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2
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+
import logging
|
|
3
|
+
import zipfile
|
|
4
|
+
|
|
5
|
+
from argparse import Namespace
|
|
6
|
+
from pathlib import Path
|
|
7
|
+
|
|
8
|
+
from simplhdl.flow import FlowFactory, FlowTools
|
|
9
|
+
from simplhdl.flows.implementationflow import ImplementationFlow
|
|
10
|
+
from simplhdl.flows.quartusflow import QuartusFlow
|
|
11
|
+
from simplhdl.resources.templates import quartus as templates
|
|
12
|
+
from simplhdl.flows.encrypt.encryptflow import encrypt
|
|
13
|
+
from simplhdl.pyedaa.project import Project
|
|
14
|
+
from simplhdl.pyedaa.attributes import UsedIn
|
|
15
|
+
from simplhdl.pyedaa import (
|
|
16
|
+
File,
|
|
17
|
+
HDLSearchPath,
|
|
18
|
+
HDLIncludeFile,
|
|
19
|
+
HDLSourceFile,
|
|
20
|
+
VerilogIncludeFile,
|
|
21
|
+
VerilogSourceFile,
|
|
22
|
+
SystemVerilogSourceFile,
|
|
23
|
+
VHDLSourceFile,
|
|
24
|
+
ConstraintFile,
|
|
25
|
+
QuartusQIPSpecificationFile,
|
|
26
|
+
QuartusIPSpecificationFile,
|
|
27
|
+
SettingFile
|
|
28
|
+
)
|
|
29
|
+
|
|
30
|
+
logger = logging.getLogger(__name__)
|
|
31
|
+
|
|
32
|
+
|
|
33
|
+
@FlowFactory.register('quartus-export')
|
|
34
|
+
class QuartusExportFlow(ImplementationFlow):
|
|
35
|
+
|
|
36
|
+
@classmethod
|
|
37
|
+
def parse_args(self, subparsers) -> None:
|
|
38
|
+
parser = subparsers.add_parser('quartus-export', help='Export Quartus project')
|
|
39
|
+
parser.add_argument(
|
|
40
|
+
'--encrypt',
|
|
41
|
+
action='store_true',
|
|
42
|
+
help="Encrypt HDL source files"
|
|
43
|
+
)
|
|
44
|
+
parser.add_argument(
|
|
45
|
+
'-o',
|
|
46
|
+
'--output',
|
|
47
|
+
action='store',
|
|
48
|
+
metavar='FILE',
|
|
49
|
+
dest='archivefile',
|
|
50
|
+
type=Path,
|
|
51
|
+
help="Output zip file"
|
|
52
|
+
)
|
|
53
|
+
|
|
54
|
+
def __init__(self, name, args: Namespace, project: Project, builddir: Path):
|
|
55
|
+
super().__init__(name, args, project, builddir)
|
|
56
|
+
self.vendors = ['mentor', 'synopsys']
|
|
57
|
+
self.templates = templates
|
|
58
|
+
self.tools.add(FlowTools.QUARTUS)
|
|
59
|
+
|
|
60
|
+
def copy_files(self):
|
|
61
|
+
seen = dict()
|
|
62
|
+
files = [f for f in self.project.DefaultDesign.Files() if 'implementation' in f[UsedIn]]
|
|
63
|
+
for file in files:
|
|
64
|
+
fileid = str(file.Path.resolve())
|
|
65
|
+
if fileid in seen:
|
|
66
|
+
file._path = seen.get(fileid)._path
|
|
67
|
+
continue
|
|
68
|
+
elif isinstance(file, SettingFile):
|
|
69
|
+
continue
|
|
70
|
+
elif isinstance(file, (ConstraintFile, QuartusQIPSpecificationFile)):
|
|
71
|
+
dest = self.builddir.joinpath('constraints', file.Path.name)
|
|
72
|
+
dest.parent.mkdir(parents=True, exist_ok=True)
|
|
73
|
+
shutil.copyfile(file.Path, dest)
|
|
74
|
+
elif isinstance(file, (HDLSearchPath, QuartusIPSpecificationFile)):
|
|
75
|
+
dest = file.Path
|
|
76
|
+
elif isinstance(file, (HDLSourceFile, HDLIncludeFile)):
|
|
77
|
+
if isinstance(file, HDLSourceFile):
|
|
78
|
+
dest = self.builddir.joinpath('rtl', file.Path.name)
|
|
79
|
+
else:
|
|
80
|
+
dest = self.builddir.joinpath('rtl', 'include', file.Path.name)
|
|
81
|
+
dest.parent.mkdir(parents=True, exist_ok=True)
|
|
82
|
+
if self.args.encrypt:
|
|
83
|
+
encrypt(file.Path, dest, language=get_language(file), vendors=self.vendors)
|
|
84
|
+
else:
|
|
85
|
+
shutil.copyfile(file.Path, dest)
|
|
86
|
+
else:
|
|
87
|
+
dest = self.builddir.joinpath('misc', file.Path.name)
|
|
88
|
+
dest.parent.mkdir(parents=True, exist_ok=True)
|
|
89
|
+
shutil.copyfile(file.Path, dest)
|
|
90
|
+
file._path = dest.absolute().relative_to(self.builddir.absolute())
|
|
91
|
+
# Convert to relative path
|
|
92
|
+
file._path = dest.absolute().relative_to(self.builddir.absolute())
|
|
93
|
+
seen[fileid] = file
|
|
94
|
+
|
|
95
|
+
def create_project(self) -> None:
|
|
96
|
+
args = Namespace(step='project', archive=False, gui=False)
|
|
97
|
+
quartus = QuartusFlow('quartus', args, self.project, self.builddir)
|
|
98
|
+
quartus.run()
|
|
99
|
+
|
|
100
|
+
def archive_project(self) -> None:
|
|
101
|
+
if self.args.archivefile:
|
|
102
|
+
archive(self.builddir, self.args.archivefile)
|
|
103
|
+
else:
|
|
104
|
+
output = self.builddir.parrent.joinpath(self.project.Name).with_suffix('.zip')
|
|
105
|
+
archive(self.builddir, output)
|
|
106
|
+
shutil.move(output, self.builddir)
|
|
107
|
+
|
|
108
|
+
def run(self) -> None:
|
|
109
|
+
self.copy_files()
|
|
110
|
+
self.create_project()
|
|
111
|
+
self.archive_project()
|
|
112
|
+
|
|
113
|
+
def is_tool_setup(self) -> None:
|
|
114
|
+
exit: bool = False
|
|
115
|
+
if shutil.which('quartus_sh') is None:
|
|
116
|
+
logger.error('quartus_sh: not found in PATH')
|
|
117
|
+
exit = True
|
|
118
|
+
if shutil.which('quartus') is None:
|
|
119
|
+
logger.error('quartus: not found in PATH')
|
|
120
|
+
exit = True
|
|
121
|
+
if exit:
|
|
122
|
+
raise FileNotFoundError("Quartus is not setup correctly")
|
|
123
|
+
|
|
124
|
+
|
|
125
|
+
def get_language(file: File) -> str:
|
|
126
|
+
fileMap = {
|
|
127
|
+
SystemVerilogSourceFile: 'systemverilog',
|
|
128
|
+
VerilogSourceFile: 'verilog',
|
|
129
|
+
VerilogIncludeFile: 'systemverilog',
|
|
130
|
+
VHDLSourceFile: 'vhdl'
|
|
131
|
+
}
|
|
132
|
+
return fileMap[file.FileType]
|
|
133
|
+
|
|
134
|
+
|
|
135
|
+
def archive(directory: Path, destination: Path) -> Path:
|
|
136
|
+
"""
|
|
137
|
+
Recursively zip all contents of the given folder into a zip file.
|
|
138
|
+
The zip archive will contain a top-level folder with the same name
|
|
139
|
+
as the zip file (excluding the extension).
|
|
140
|
+
|
|
141
|
+
Parameters:
|
|
142
|
+
directory (Path): The folder whose contents will be zipped.
|
|
143
|
+
destination (Path): The path to the resulting zip file.
|
|
144
|
+
Its stem will be used as the top-level folder name.
|
|
145
|
+
|
|
146
|
+
Returns:
|
|
147
|
+
Path: The path to the created zip archive.
|
|
148
|
+
"""
|
|
149
|
+
top_folder = destination.stem # top folder inside the archive
|
|
150
|
+
with zipfile.ZipFile(destination, 'w', zipfile.ZIP_DEFLATED) as zipf:
|
|
151
|
+
# Walk through all files in the directory
|
|
152
|
+
for file in directory.rglob('*'):
|
|
153
|
+
if file.is_file():
|
|
154
|
+
# Place each file under the top_folder
|
|
155
|
+
arcname = Path(top_folder) / file.relative_to(directory)
|
|
156
|
+
zipf.write(file, arcname=arcname)
|
|
157
|
+
return destination
|
|
@@ -18,7 +18,7 @@ from ..pyedaa import (QuartusIPSpecificationFile, VerilogIncludeFile, VerilogSou
|
|
|
18
18
|
SystemVerilogSourceFile, VHDLSourceFile, ConstraintFile,
|
|
19
19
|
EDIFNetlistFile, NetlistFile, SettingFile, QuartusSignalTapFile,
|
|
20
20
|
QuartusIniFile, QuartusQIPSpecificationFile, QuartusQSYSSpecificationFile,
|
|
21
|
-
HDLSearchPath, VerilogIncludeSearchPath)
|
|
21
|
+
HDLSearchPath, VerilogIncludeSearchPath, MemoryInitFile)
|
|
22
22
|
from ..pyedaa.project import Project
|
|
23
23
|
from ..pyedaa.attributes import UsedIn
|
|
24
24
|
|
|
@@ -62,10 +62,11 @@ class QuartusFlow(ImplementationFlow):
|
|
|
62
62
|
def run(self) -> None:
|
|
63
63
|
if self.args.archive:
|
|
64
64
|
self.archive()
|
|
65
|
-
|
|
66
|
-
|
|
67
|
-
|
|
68
|
-
|
|
65
|
+
else:
|
|
66
|
+
self.validate()
|
|
67
|
+
self.configure()
|
|
68
|
+
self.generate()
|
|
69
|
+
self.execute(self.args.step)
|
|
69
70
|
|
|
70
71
|
def archive(self) -> None:
|
|
71
72
|
name = self.project.Name
|
|
@@ -79,7 +80,6 @@ class QuartusFlow(ImplementationFlow):
|
|
|
79
80
|
raise Exception("Unknown value for argument --archive: {self.args.archive}")
|
|
80
81
|
command = f"quartus_sh --archive -use_file_set {fileset} -revision {name} -no_discover -output {name}.qar {name}" # noqa
|
|
81
82
|
sh(command.split(), output=True, cwd=self.builddir)
|
|
82
|
-
raise SystemExit
|
|
83
83
|
|
|
84
84
|
def validate(self):
|
|
85
85
|
if self.project.DefaultDesign.DefaultFileSet.TopLevel is None:
|
|
@@ -113,6 +113,7 @@ class QuartusFlow(ImplementationFlow):
|
|
|
113
113
|
QuartusQIPSpecificationFile=QuartusQIPSpecificationFile,
|
|
114
114
|
QuartusQSYSSpecificationFile=QuartusQSYSSpecificationFile,
|
|
115
115
|
QuartusIniFile=QuartusIniFile,
|
|
116
|
+
MemoryInitFile=MemoryInitFile,
|
|
116
117
|
project=self.project,
|
|
117
118
|
UsedIn=UsedIn)
|
|
118
119
|
template = environment.get_template('run.tcl.j2')
|