SimplHDL 0.2.2__tar.gz → 0.3.0__tar.gz

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Files changed (199) hide show
  1. {simplhdl-0.2.2 → simplhdl-0.3.0}/PKG-INFO +2 -2
  2. simplhdl-0.3.0/examples/hdl/adder/sim/testbench.yml +14 -0
  3. {simplhdl-0.2.2 → simplhdl-0.3.0}/src/SimplHDL.egg-info/PKG-INFO +2 -2
  4. {simplhdl-0.2.2 → simplhdl-0.3.0}/src/SimplHDL.egg-info/SOURCES.txt +2 -0
  5. simplhdl-0.3.0/src/simplhdl/__init__.py +1 -0
  6. {simplhdl-0.2.2 → simplhdl-0.3.0}/src/simplhdl/__main__.py +4 -2
  7. {simplhdl-0.2.2 → simplhdl-0.3.0}/src/simplhdl/flows/quartusflow.py +1 -1
  8. {simplhdl-0.2.2 → simplhdl-0.3.0}/src/simplhdl/flows/questasim/questasimflow.py +5 -2
  9. {simplhdl-0.2.2 → simplhdl-0.3.0}/src/simplhdl/flows/vivadoflow.py +12 -6
  10. {simplhdl-0.2.2 → simplhdl-0.3.0}/src/simplhdl/flows/xsim/xsimflow.py +4 -0
  11. {simplhdl-0.2.2 → simplhdl-0.3.0}/src/simplhdl/parser.py +1 -2
  12. {simplhdl-0.2.2 → simplhdl-0.3.0}/src/simplhdl/parsers/simplhdlparser.py +9 -3
  13. {simplhdl-0.2.2 → simplhdl-0.3.0}/src/simplhdl/plugins.py +1 -0
  14. {simplhdl-0.2.2 → simplhdl-0.3.0}/src/simplhdl/pyedaa/fileset.py +1 -1
  15. {simplhdl-0.2.2 → simplhdl-0.3.0}/src/simplhdl/pyedaa/project.py +24 -0
  16. simplhdl-0.3.0/src/simplhdl/pyedaa/target.py +31 -0
  17. {simplhdl-0.2.2 → simplhdl-0.3.0}/src/simplhdl/resources/templates/quartus/run.tcl.j2 +1 -1
  18. {simplhdl-0.2.2 → simplhdl-0.3.0}/src/simplhdl/resources/templates/vivado/project.tcl.j2 +1 -1
  19. {simplhdl-0.2.2 → simplhdl-0.3.0}/src/simplhdl/resources/templates/vivado/run.tcl.j2 +15 -2
  20. {simplhdl-0.2.2 → simplhdl-0.3.0}/src/simplhdl/resources/templates/xsim/Makefile.j2 +1 -1
  21. simplhdl-0.3.0/src/simplhdl/run.py +51 -0
  22. {simplhdl-0.2.2 → simplhdl-0.3.0}/src/simplhdl/utils.py +10 -0
  23. simplhdl-0.2.2/examples/hdl/adder/sim/testbench.yml +0 -10
  24. simplhdl-0.2.2/src/simplhdl/__init__.py +0 -1
  25. {simplhdl-0.2.2 → simplhdl-0.3.0}/.github/workflows/publish.yml +0 -0
  26. {simplhdl-0.2.2 → simplhdl-0.3.0}/.gitignore +0 -0
  27. {simplhdl-0.2.2 → simplhdl-0.3.0}/.readthedocs.yaml +0 -0
  28. {simplhdl-0.2.2 → simplhdl-0.3.0}/LICENSE +0 -0
  29. {simplhdl-0.2.2 → simplhdl-0.3.0}/README.md +0 -0
  30. {simplhdl-0.2.2 → simplhdl-0.3.0}/docs/_static/simplhdl_dark.png +0 -0
  31. {simplhdl-0.2.2 → simplhdl-0.3.0}/docs/_static/simplhdl_light.png +0 -0
  32. {simplhdl-0.2.2 → simplhdl-0.3.0}/docs/_static/simplhdl_light_1.png +0 -0
  33. {simplhdl-0.2.2 → simplhdl-0.3.0}/docs/conf.py +0 -0
  34. {simplhdl-0.2.2 → simplhdl-0.3.0}/docs/drawing.svg +0 -0
  35. {simplhdl-0.2.2 → simplhdl-0.3.0}/docs/flows/ghdl.rst +0 -0
  36. {simplhdl-0.2.2 → simplhdl-0.3.0}/docs/flows/icarus.rst +0 -0
  37. {simplhdl-0.2.2 → simplhdl-0.3.0}/docs/flows/quartus.rst +0 -0
  38. {simplhdl-0.2.2 → simplhdl-0.3.0}/docs/flows/questasim.rst +0 -0
  39. {simplhdl-0.2.2 → simplhdl-0.3.0}/docs/flows/vcs.rst +0 -0
  40. {simplhdl-0.2.2 → simplhdl-0.3.0}/docs/flows/vivado.rst +0 -0
  41. {simplhdl-0.2.2 → simplhdl-0.3.0}/docs/flows/xsim.rst +0 -0
  42. {simplhdl-0.2.2 → simplhdl-0.3.0}/docs/flows.rst +0 -0
  43. {simplhdl-0.2.2 → simplhdl-0.3.0}/docs/index.rst +0 -0
  44. {simplhdl-0.2.2 → simplhdl-0.3.0}/docs/intel-ips.md +0 -0
  45. {simplhdl-0.2.2 → simplhdl-0.3.0}/docs/introduction.rst +0 -0
  46. {simplhdl-0.2.2 → simplhdl-0.3.0}/docs/plugins.rst +0 -0
  47. {simplhdl-0.2.2 → simplhdl-0.3.0}/docs/requirements.txt +0 -0
  48. {simplhdl-0.2.2 → simplhdl-0.3.0}/examples/hdl/adder/adder.yml +0 -0
  49. {simplhdl-0.2.2 → simplhdl-0.3.0}/examples/hdl/adder/hdl/adder.sv +0 -0
  50. {simplhdl-0.2.2 → simplhdl-0.3.0}/examples/hdl/adder/sim/testbench.sv +0 -0
  51. {simplhdl-0.2.2 → simplhdl-0.3.0}/examples/hdl/adder/syn/build.yml +0 -0
  52. {simplhdl-0.2.2 → simplhdl-0.3.0}/examples/hdl/adder/syn/placement.xdc +0 -0
  53. {simplhdl-0.2.2 → simplhdl-0.3.0}/examples/hdl/adder/syn/timing.xdc +0 -0
  54. {simplhdl-0.2.2 → simplhdl-0.3.0}/examples/hdl/adder/syn/top.sv +0 -0
  55. {simplhdl-0.2.2 → simplhdl-0.3.0}/examples/hdl/alu/alu.yml +0 -0
  56. {simplhdl-0.2.2 → simplhdl-0.3.0}/examples/hdl/alu/hdl/add.sv +0 -0
  57. {simplhdl-0.2.2 → simplhdl-0.3.0}/examples/hdl/alu/hdl/alu.sv +0 -0
  58. {simplhdl-0.2.2 → simplhdl-0.3.0}/examples/hdl/alu/hdl/mul.sv +0 -0
  59. {simplhdl-0.2.2 → simplhdl-0.3.0}/examples/hdl/alu/hdl/sub.sv +0 -0
  60. {simplhdl-0.2.2 → simplhdl-0.3.0}/examples/hdl/alu/sim/pyuvm/alu_vip/__init__.py +0 -0
  61. {simplhdl-0.2.2 → simplhdl-0.3.0}/examples/hdl/alu/sim/pyuvm/alu_vip/agent.py +0 -0
  62. {simplhdl-0.2.2 → simplhdl-0.3.0}/examples/hdl/alu/sim/pyuvm/alu_vip/aluif.py +0 -0
  63. {simplhdl-0.2.2 → simplhdl-0.3.0}/examples/hdl/alu/sim/pyuvm/alu_vip/driver.py +0 -0
  64. {simplhdl-0.2.2 → simplhdl-0.3.0}/examples/hdl/alu/sim/pyuvm/alu_vip/monitor.py +0 -0
  65. {simplhdl-0.2.2 → simplhdl-0.3.0}/examples/hdl/alu/sim/pyuvm/alu_vip/sequenceitem.py +0 -0
  66. {simplhdl-0.2.2 → simplhdl-0.3.0}/examples/hdl/alu/sim/pyuvm/alu_vip/sequencer.py +0 -0
  67. {simplhdl-0.2.2 → simplhdl-0.3.0}/examples/hdl/alu/sim/pyuvm/clock_vip/__init__.py +0 -0
  68. {simplhdl-0.2.2 → simplhdl-0.3.0}/examples/hdl/alu/sim/pyuvm/clock_vip/agent.py +0 -0
  69. {simplhdl-0.2.2 → simplhdl-0.3.0}/examples/hdl/alu/sim/pyuvm/clock_vip/clockif.py +0 -0
  70. {simplhdl-0.2.2 → simplhdl-0.3.0}/examples/hdl/alu/sim/pyuvm/pyuvm.yml +0 -0
  71. {simplhdl-0.2.2 → simplhdl-0.3.0}/examples/hdl/alu/sim/pyuvm/test/__init__.py +0 -0
  72. {simplhdl-0.2.2 → simplhdl-0.3.0}/examples/hdl/alu/sim/pyuvm/test/env.py +0 -0
  73. {simplhdl-0.2.2 → simplhdl-0.3.0}/examples/hdl/alu/sim/pyuvm/test/seq_lib.py +0 -0
  74. {simplhdl-0.2.2 → simplhdl-0.3.0}/examples/hdl/alu/sim/pyuvm/test/test.py +0 -0
  75. {simplhdl-0.2.2 → simplhdl-0.3.0}/examples/hdl/alu/sim/pyuvm/testbench.py +0 -0
  76. {simplhdl-0.2.2 → simplhdl-0.3.0}/examples/hdl/alu/sim/uvm/alu_vip/agent.svh +0 -0
  77. {simplhdl-0.2.2 → simplhdl-0.3.0}/examples/hdl/alu/sim/uvm/alu_vip/alu_vip.sv +0 -0
  78. {simplhdl-0.2.2 → simplhdl-0.3.0}/examples/hdl/alu/sim/uvm/alu_vip/alu_vip.yml +0 -0
  79. {simplhdl-0.2.2 → simplhdl-0.3.0}/examples/hdl/alu/sim/uvm/alu_vip/driver.svh +0 -0
  80. {simplhdl-0.2.2 → simplhdl-0.3.0}/examples/hdl/alu/sim/uvm/alu_vip/env.svh +0 -0
  81. {simplhdl-0.2.2 → simplhdl-0.3.0}/examples/hdl/alu/sim/uvm/alu_vip/monitor.svh +0 -0
  82. {simplhdl-0.2.2 → simplhdl-0.3.0}/examples/hdl/alu/sim/uvm/alu_vip/sequence_item.svh +0 -0
  83. {simplhdl-0.2.2 → simplhdl-0.3.0}/examples/hdl/alu/sim/uvm/tb_env/seq_lib/add_seq.svh +0 -0
  84. {simplhdl-0.2.2 → simplhdl-0.3.0}/examples/hdl/alu/sim/uvm/tb_env/seq_lib/base_seq.svh +0 -0
  85. {simplhdl-0.2.2 → simplhdl-0.3.0}/examples/hdl/alu/sim/uvm/tb_env/tb_env.sv +0 -0
  86. {simplhdl-0.2.2 → simplhdl-0.3.0}/examples/hdl/alu/sim/uvm/tb_env/tb_env.yml +0 -0
  87. {simplhdl-0.2.2 → simplhdl-0.3.0}/examples/hdl/alu/sim/uvm/tb_env/test/base_test.svh +0 -0
  88. {simplhdl-0.2.2 → simplhdl-0.3.0}/examples/hdl/alu/sim/uvm/tb_env/test/test_add.svh +0 -0
  89. {simplhdl-0.2.2 → simplhdl-0.3.0}/examples/hdl/alu/sim/uvm/testbench/alu_if.sv +0 -0
  90. {simplhdl-0.2.2 → simplhdl-0.3.0}/examples/hdl/alu/sim/uvm/testbench/testbench.sv +0 -0
  91. {simplhdl-0.2.2 → simplhdl-0.3.0}/examples/hdl/alu/sim/uvm/testbench/testbench.yml +0 -0
  92. {simplhdl-0.2.2 → simplhdl-0.3.0}/examples/hdl/alu/sim/uvm/testcases/test_add/test_add.yml +0 -0
  93. {simplhdl-0.2.2 → simplhdl-0.3.0}/examples/hdl/alu/syn/build.yml +0 -0
  94. {simplhdl-0.2.2 → simplhdl-0.3.0}/examples/hdl/alu/syn/placement.xdc +0 -0
  95. {simplhdl-0.2.2 → simplhdl-0.3.0}/examples/hdl/alu/syn/timing.xdc +0 -0
  96. {simplhdl-0.2.2 → simplhdl-0.3.0}/examples/hdl/hello/build.sbt +0 -0
  97. {simplhdl-0.2.2 → simplhdl-0.3.0}/examples/hdl/hello/hello.yml +0 -0
  98. {simplhdl-0.2.2 → simplhdl-0.3.0}/examples/hdl/hello/src/main/scala/Hello.scala +0 -0
  99. {simplhdl-0.2.2 → simplhdl-0.3.0}/examples/hdl/hello/syn/build.yml +0 -0
  100. {simplhdl-0.2.2 → simplhdl-0.3.0}/examples/plugins/simple_parser/setup.py +0 -0
  101. {simplhdl-0.2.2 → simplhdl-0.3.0}/examples/plugins/simple_parser/src/simple_parser/__init__.py +0 -0
  102. {simplhdl-0.2.2 → simplhdl-0.3.0}/examples/plugins/simple_parser/src/simple_parser/simple_parser.py +0 -0
  103. {simplhdl-0.2.2 → simplhdl-0.3.0}/pyproject.toml +0 -0
  104. {simplhdl-0.2.2 → simplhdl-0.3.0}/setup.cfg +0 -0
  105. {simplhdl-0.2.2 → simplhdl-0.3.0}/src/SimplHDL.egg-info/dependency_links.txt +0 -0
  106. {simplhdl-0.2.2 → simplhdl-0.3.0}/src/SimplHDL.egg-info/entry_points.txt +0 -0
  107. {simplhdl-0.2.2 → simplhdl-0.3.0}/src/SimplHDL.egg-info/requires.txt +0 -0
  108. {simplhdl-0.2.2 → simplhdl-0.3.0}/src/SimplHDL.egg-info/top_level.txt +0 -0
  109. {simplhdl-0.2.2 → simplhdl-0.3.0}/src/simplhdl/cocotb.py +0 -0
  110. {simplhdl-0.2.2 → simplhdl-0.3.0}/src/simplhdl/flow.py +0 -0
  111. {simplhdl-0.2.2 → simplhdl-0.3.0}/src/simplhdl/flows/__init__.py +0 -0
  112. {simplhdl-0.2.2 → simplhdl-0.3.0}/src/simplhdl/flows/flake8/flake8flow.py +0 -0
  113. {simplhdl-0.2.2 → simplhdl-0.3.0}/src/simplhdl/flows/implementationflow.py +0 -0
  114. {simplhdl-0.2.2 → simplhdl-0.3.0}/src/simplhdl/flows/lint/lintflow.py +0 -0
  115. {simplhdl-0.2.2 → simplhdl-0.3.0}/src/simplhdl/flows/modelsim/__init__.py +0 -0
  116. {simplhdl-0.2.2 → simplhdl-0.3.0}/src/simplhdl/flows/modelsim/modelsimflow.py +0 -0
  117. {simplhdl-0.2.2 → simplhdl-0.3.0}/src/simplhdl/flows/quartusdse/__init__.py +0 -0
  118. {simplhdl-0.2.2 → simplhdl-0.3.0}/src/simplhdl/flows/quartusdse/quartusdseflow.py +0 -0
  119. {simplhdl-0.2.2 → simplhdl-0.3.0}/src/simplhdl/flows/questasim/__init__.py +0 -0
  120. {simplhdl-0.2.2 → simplhdl-0.3.0}/src/simplhdl/flows/rivierapro/__init__.py +0 -0
  121. {simplhdl-0.2.2 → simplhdl-0.3.0}/src/simplhdl/flows/rivierapro/rivieraproflow.py +0 -0
  122. {simplhdl-0.2.2 → simplhdl-0.3.0}/src/simplhdl/flows/simulationflow.py +0 -0
  123. {simplhdl-0.2.2 → simplhdl-0.3.0}/src/simplhdl/flows/vcs/__init__.py +0 -0
  124. {simplhdl-0.2.2 → simplhdl-0.3.0}/src/simplhdl/flows/vcs/vcsflow.py +0 -0
  125. {simplhdl-0.2.2 → simplhdl-0.3.0}/src/simplhdl/flows/verible/__init__.py +0 -0
  126. {simplhdl-0.2.2 → simplhdl-0.3.0}/src/simplhdl/flows/verible/veribleflow.py +0 -0
  127. {simplhdl-0.2.2 → simplhdl-0.3.0}/src/simplhdl/flows/vsg/__init__.py +0 -0
  128. {simplhdl-0.2.2 → simplhdl-0.3.0}/src/simplhdl/flows/vsg/vsgflow.py +0 -0
  129. {simplhdl-0.2.2 → simplhdl-0.3.0}/src/simplhdl/flows/xsim/__init__.py +0 -0
  130. {simplhdl-0.2.2 → simplhdl-0.3.0}/src/simplhdl/generator.py +0 -0
  131. {simplhdl-0.2.2 → simplhdl-0.3.0}/src/simplhdl/generators/__init__.py +0 -0
  132. {simplhdl-0.2.2 → simplhdl-0.3.0}/src/simplhdl/generators/chisel.py +0 -0
  133. {simplhdl-0.2.2 → simplhdl-0.3.0}/src/simplhdl/generators/ipxact.py +0 -0
  134. {simplhdl-0.2.2 → simplhdl-0.3.0}/src/simplhdl/generators/spd.py +0 -0
  135. {simplhdl-0.2.2 → simplhdl-0.3.0}/src/simplhdl/generators/systemrdl.py +0 -0
  136. {simplhdl-0.2.2 → simplhdl-0.3.0}/src/simplhdl/info.py +0 -0
  137. {simplhdl-0.2.2 → simplhdl-0.3.0}/src/simplhdl/parsers/__init__.py +0 -0
  138. {simplhdl-0.2.2 → simplhdl-0.3.0}/src/simplhdl/parsers/fusesocparser.py +0 -0
  139. {simplhdl-0.2.2 → simplhdl-0.3.0}/src/simplhdl/pyedaa/__init__.py +0 -0
  140. {simplhdl-0.2.2 → simplhdl-0.3.0}/src/simplhdl/pyedaa/attributes.py +0 -0
  141. {simplhdl-0.2.2 → simplhdl-0.3.0}/src/simplhdl/pyedaa/design.py +0 -0
  142. {simplhdl-0.2.2 → simplhdl-0.3.0}/src/simplhdl/pyedaa/filetypes.py +0 -0
  143. {simplhdl-0.2.2 → simplhdl-0.3.0}/src/simplhdl/pyedaa/vhdllibrary.py +0 -0
  144. {simplhdl-0.2.2 → simplhdl-0.3.0}/src/simplhdl/repo.py +0 -0
  145. {simplhdl-0.2.2 → simplhdl-0.3.0}/src/simplhdl/resources/__init__.py +0 -0
  146. {simplhdl-0.2.2 → simplhdl-0.3.0}/src/simplhdl/resources/templates/__init__.py +0 -0
  147. {simplhdl-0.2.2 → simplhdl-0.3.0}/src/simplhdl/resources/templates/flake8/__init__.py +0 -0
  148. {simplhdl-0.2.2 → simplhdl-0.3.0}/src/simplhdl/resources/templates/flake8/setup.cfg.j2 +0 -0
  149. {simplhdl-0.2.2 → simplhdl-0.3.0}/src/simplhdl/resources/templates/modelsim/Makefile.j2 +0 -0
  150. {simplhdl-0.2.2 → simplhdl-0.3.0}/src/simplhdl/resources/templates/modelsim/__init__.py +0 -0
  151. {simplhdl-0.2.2 → simplhdl-0.3.0}/src/simplhdl/resources/templates/modelsim/cocotb.mk.j2 +0 -0
  152. {simplhdl-0.2.2 → simplhdl-0.3.0}/src/simplhdl/resources/templates/modelsim/dependencies.mk.j2 +0 -0
  153. {simplhdl-0.2.2 → simplhdl-0.3.0}/src/simplhdl/resources/templates/modelsim/files.j2 +0 -0
  154. {simplhdl-0.2.2 → simplhdl-0.3.0}/src/simplhdl/resources/templates/modelsim/fileset.j2 +0 -0
  155. {simplhdl-0.2.2 → simplhdl-0.3.0}/src/simplhdl/resources/templates/modelsim/modelsim.tcl.j2 +0 -0
  156. {simplhdl-0.2.2 → simplhdl-0.3.0}/src/simplhdl/resources/templates/modelsim/project.mk.j2 +0 -0
  157. {simplhdl-0.2.2 → simplhdl-0.3.0}/src/simplhdl/resources/templates/modelsim/run.do.j2 +0 -0
  158. {simplhdl-0.2.2 → simplhdl-0.3.0}/src/simplhdl/resources/templates/quartus/__init__.py +0 -0
  159. {simplhdl-0.2.2 → simplhdl-0.3.0}/src/simplhdl/resources/templates/quartus/project.tcl.j2 +0 -0
  160. {simplhdl-0.2.2 → simplhdl-0.3.0}/src/simplhdl/resources/templates/questasim/__init__.py +0 -0
  161. {simplhdl-0.2.2 → simplhdl-0.3.0}/src/simplhdl/resources/templates/questasim/modelsim.tcl.j2 +0 -0
  162. {simplhdl-0.2.2 → simplhdl-0.3.0}/src/simplhdl/resources/templates/questasim/project.qrun.j2 +0 -0
  163. {simplhdl-0.2.2 → simplhdl-0.3.0}/src/simplhdl/resources/templates/questasim/visualizer.tcl.j2 +0 -0
  164. {simplhdl-0.2.2 → simplhdl-0.3.0}/src/simplhdl/resources/templates/questasim/vsim-run.do.j2 +0 -0
  165. {simplhdl-0.2.2 → simplhdl-0.3.0}/src/simplhdl/resources/templates/rivierapro/Makefile.j2 +0 -0
  166. {simplhdl-0.2.2 → simplhdl-0.3.0}/src/simplhdl/resources/templates/rivierapro/__init__.py +0 -0
  167. {simplhdl-0.2.2 → simplhdl-0.3.0}/src/simplhdl/resources/templates/rivierapro/cocotb.mk.j2 +0 -0
  168. {simplhdl-0.2.2 → simplhdl-0.3.0}/src/simplhdl/resources/templates/rivierapro/dependencies.mk.j2 +0 -0
  169. {simplhdl-0.2.2 → simplhdl-0.3.0}/src/simplhdl/resources/templates/rivierapro/files.j2 +0 -0
  170. {simplhdl-0.2.2 → simplhdl-0.3.0}/src/simplhdl/resources/templates/rivierapro/fileset.j2 +0 -0
  171. {simplhdl-0.2.2 → simplhdl-0.3.0}/src/simplhdl/resources/templates/rivierapro/project.mk.j2 +0 -0
  172. {simplhdl-0.2.2 → simplhdl-0.3.0}/src/simplhdl/resources/templates/vcs/Makefile.j2 +0 -0
  173. {simplhdl-0.2.2 → simplhdl-0.3.0}/src/simplhdl/resources/templates/vcs/__init__.py +0 -0
  174. {simplhdl-0.2.2 → simplhdl-0.3.0}/src/simplhdl/resources/templates/vcs/cocotb.mk.j2 +0 -0
  175. {simplhdl-0.2.2 → simplhdl-0.3.0}/src/simplhdl/resources/templates/vcs/dependencies.mk.j2 +0 -0
  176. {simplhdl-0.2.2 → simplhdl-0.3.0}/src/simplhdl/resources/templates/vcs/files.j2 +0 -0
  177. {simplhdl-0.2.2 → simplhdl-0.3.0}/src/simplhdl/resources/templates/vcs/fileset.j2 +0 -0
  178. {simplhdl-0.2.2 → simplhdl-0.3.0}/src/simplhdl/resources/templates/vcs/pli.tab.j2 +0 -0
  179. {simplhdl-0.2.2 → simplhdl-0.3.0}/src/simplhdl/resources/templates/vcs/project.mk.j2 +0 -0
  180. {simplhdl-0.2.2 → simplhdl-0.3.0}/src/simplhdl/resources/templates/vcs/synopsys_sim.setup.j2 +0 -0
  181. {simplhdl-0.2.2 → simplhdl-0.3.0}/src/simplhdl/resources/templates/vcs/vcs.parameters.j2 +0 -0
  182. {simplhdl-0.2.2 → simplhdl-0.3.0}/src/simplhdl/resources/templates/verible/__init__.py +0 -0
  183. {simplhdl-0.2.2 → simplhdl-0.3.0}/src/simplhdl/resources/templates/verible/rules.cfg.j2 +0 -0
  184. {simplhdl-0.2.2 → simplhdl-0.3.0}/src/simplhdl/resources/templates/vivado/__init__.py +0 -0
  185. {simplhdl-0.2.2 → simplhdl-0.3.0}/src/simplhdl/resources/templates/vivado/launch_run.sh.j2 +0 -0
  186. {simplhdl-0.2.2 → simplhdl-0.3.0}/src/simplhdl/resources/templates/vivado/steps.tcl.j2 +0 -0
  187. {simplhdl-0.2.2 → simplhdl-0.3.0}/src/simplhdl/resources/templates/vsg/__init__.py +0 -0
  188. {simplhdl-0.2.2 → simplhdl-0.3.0}/src/simplhdl/resources/templates/vsg/files.json.j2 +0 -0
  189. {simplhdl-0.2.2 → simplhdl-0.3.0}/src/simplhdl/resources/templates/vsg/rules.yml.j2 +0 -0
  190. {simplhdl-0.2.2 → simplhdl-0.3.0}/src/simplhdl/resources/templates/xsim/__init__.py +0 -0
  191. {simplhdl-0.2.2 → simplhdl-0.3.0}/src/simplhdl/resources/templates/xsim/cocotb.mk.j2 +0 -0
  192. {simplhdl-0.2.2 → simplhdl-0.3.0}/src/simplhdl/resources/templates/xsim/dependencies.mk.j2 +0 -0
  193. {simplhdl-0.2.2 → simplhdl-0.3.0}/src/simplhdl/resources/templates/xsim/files.j2 +0 -0
  194. {simplhdl-0.2.2 → simplhdl-0.3.0}/src/simplhdl/resources/templates/xsim/fileset.j2 +0 -0
  195. {simplhdl-0.2.2 → simplhdl-0.3.0}/src/simplhdl/resources/templates/xsim/project.mk.j2 +0 -0
  196. {simplhdl-0.2.2 → simplhdl-0.3.0}/src/simplhdl/simplhdl.py +0 -0
  197. {simplhdl-0.2.2 → simplhdl-0.3.0}/src/simplhdl/tools.py +0 -0
  198. {simplhdl-0.2.2 → simplhdl-0.3.0}/tests/test_dummy.py +0 -0
  199. {simplhdl-0.2.2 → simplhdl-0.3.0}/tox.ini +0 -0
@@ -1,6 +1,6 @@
1
- Metadata-Version: 2.1
1
+ Metadata-Version: 2.2
2
2
  Name: SimplHDL
3
- Version: 0.2.2
3
+ Version: 0.3.0
4
4
  Summary: A framework for simulating and implementing HDL designs
5
5
  Author-email: Rasmus Grøndahl Olsen <simplhdl@gmail.com>
6
6
  Maintainer-email: Rasmus Grøndahl Olsen <simplhdl@gmail.com>
@@ -0,0 +1,14 @@
1
+ #%SimplAPI=1.0
2
+
3
+ library: work
4
+ top: testbench
5
+
6
+ dependencies:
7
+ - ../adder.yml
8
+
9
+ files:
10
+ - testbench.sv
11
+
12
+ targets:
13
+ questasim: questasim --vopt-args "-suppress vopt-2685"
14
+ vcs: vcs --vcs-args +warn=noTFIPC
@@ -1,6 +1,6 @@
1
- Metadata-Version: 2.1
1
+ Metadata-Version: 2.2
2
2
  Name: SimplHDL
3
- Version: 0.2.2
3
+ Version: 0.3.0
4
4
  Summary: A framework for simulating and implementing HDL designs
5
5
  Author-email: Rasmus Grøndahl Olsen <simplhdl@gmail.com>
6
6
  Maintainer-email: Rasmus Grøndahl Olsen <simplhdl@gmail.com>
@@ -94,6 +94,7 @@ src/simplhdl/info.py
94
94
  src/simplhdl/parser.py
95
95
  src/simplhdl/plugins.py
96
96
  src/simplhdl/repo.py
97
+ src/simplhdl/run.py
97
98
  src/simplhdl/simplhdl.py
98
99
  src/simplhdl/tools.py
99
100
  src/simplhdl/utils.py
@@ -134,6 +135,7 @@ src/simplhdl/pyedaa/design.py
134
135
  src/simplhdl/pyedaa/fileset.py
135
136
  src/simplhdl/pyedaa/filetypes.py
136
137
  src/simplhdl/pyedaa/project.py
138
+ src/simplhdl/pyedaa/target.py
137
139
  src/simplhdl/pyedaa/vhdllibrary.py
138
140
  src/simplhdl/resources/__init__.py
139
141
  src/simplhdl/resources/templates/__init__.py
@@ -0,0 +1 @@
1
+ __version__ = "0.3.0"
@@ -4,6 +4,8 @@ import argcomplete
4
4
  import logging
5
5
  import traceback
6
6
 
7
+ from typing import Sequence
8
+
7
9
  from pathlib import Path
8
10
  from . import __version__
9
11
  from .simplhdl import Simplhdl
@@ -16,7 +18,7 @@ from .utils import CalledShError
16
18
  logger = logging.getLogger(__name__)
17
19
 
18
20
 
19
- def parse_arguments():
21
+ def parse_arguments(args: Sequence[str] = None, namespace: None = None) -> argparse.Namespace:
20
22
 
21
23
  parser = argparse.ArgumentParser(
22
24
  prog="simpl",
@@ -56,7 +58,7 @@ def parse_arguments():
56
58
  flow_class.parse_args(subparsers)
57
59
 
58
60
  argcomplete.autocomplete(parser)
59
- return parser.parse_args()
61
+ return parser.parse_args(args=args, namespace=namespace)
60
62
 
61
63
 
62
64
  def main():
@@ -35,7 +35,7 @@ class QuartusFlow(ImplementationFlow):
35
35
  '-s',
36
36
  '--step',
37
37
  action='store',
38
- choices=['project', 'synthesis', 'implement', 'finalize', 'compile'],
38
+ choices=['project', 'elaborate', 'implement', 'finalize', 'compile'],
39
39
  default='compile',
40
40
  help="flow step to run"
41
41
  )
@@ -168,11 +168,11 @@ class QuestaSimFlow(SimulationFlow):
168
168
  args.add(f"-g{name}={escape(value)}")
169
169
  for name, value in self.project.Parameters.items():
170
170
  args.add(f"-g{name}={escape(value)}")
171
- if self.args.debug:
171
+ if self.args.gui or self.args.debug:
172
172
  args.add('+acc')
173
173
  args.add('-debugdb')
174
174
  args.add('-fsmdebug')
175
- elif self.args.gui or self.args.do or self.args.wavedump or self.cocotb.enabled:
175
+ elif self.args.do or self.args.wavedump or self.cocotb.enabled:
176
176
  args.add('+acc=npr')
177
177
  return ' '.join(list(args) + [self.args.vopt_args])
178
178
 
@@ -259,6 +259,9 @@ class QuestaSimFlow(SimulationFlow):
259
259
  command.append('-visualizer')
260
260
  command.append('-gui')
261
261
  elif self.args.step:
262
+ if step == "elaborate":
263
+ command.append('-optimize')
264
+ return command
262
265
  command.append(f'-{step}')
263
266
 
264
267
  if self.args.do:
@@ -31,6 +31,8 @@ class VivadoFlow(FlowBase):
31
31
  '--step',
32
32
  action='store',
33
33
  choices=[
34
+ 'lint',
35
+ 'elaborate',
34
36
  'synthesis',
35
37
  'opt',
36
38
  'power_opt',
@@ -83,6 +85,15 @@ class VivadoFlow(FlowBase):
83
85
  sh(command, cwd=self.builddir, output=True)
84
86
  raise SystemExit
85
87
 
88
+ def get_files(self):
89
+ files = []
90
+ seen = []
91
+ for f in self.project.DefaultDesign.Files():
92
+ if 'implementation' in f[UsedIn] and f.Path not in seen:
93
+ seen.append(f.Path)
94
+ files.append(f)
95
+ return files
96
+
86
97
  def setup(self):
87
98
  self.is_tool_setup()
88
99
  os.makedirs(self.builddir, exist_ok=True)
@@ -94,6 +105,7 @@ class VivadoFlow(FlowBase):
94
105
  trim_blocks=True)
95
106
  template = environment.get_template('project.tcl.j2')
96
107
  generate_from_template(template, self.builddir,
108
+ files=self.get_files(),
97
109
  dict2str=dict2str,
98
110
  VerilogIncludeFile=VerilogIncludeFile,
99
111
  VerilogSourceFile=VerilogSourceFile,
@@ -119,12 +131,6 @@ class VivadoFlow(FlowBase):
119
131
  name = self.project.Name
120
132
  command = f"vivado {name}.xpr -mode batch -notrace -source run.tcl -tclargs {step}".split()
121
133
  sh(command, cwd=self.builddir, output=True)
122
- # jsonfile = self.builddir.joinpath('runs.json')
123
- # with jsonfile.open() as f:
124
- # runs: Dict[str, List[str]] = json.load(f)
125
- # for name, run in runs.items():
126
- # for script in run:
127
- # sh(['bash', 'launch_run.sh', script], output=True, cwd=self.builddir)
128
134
 
129
135
  def run(self) -> None:
130
136
  if self.args.archive:
@@ -133,6 +133,8 @@ class XsimFlow(SimulationFlow):
133
133
  args.add(f"-v {self.args.verbose if self.args.verbose < 2 else 2}")
134
134
  for name, value in self.project.Defines.items():
135
135
  args.add(f"-d {name}={escape(value)}")
136
+ if self.is_uvm():
137
+ args.add('-L uvm')
136
138
  return ' '.join(list(args) + [self.args.xvlog_args]).strip()
137
139
 
138
140
  def xvhdl_args(self) -> str:
@@ -150,6 +152,8 @@ class XsimFlow(SimulationFlow):
150
152
  args.add(f"--generic_top {name}={escape(value)}")
151
153
  for name, value in self.project.Parameters.items():
152
154
  args.add(f"--generic_top {name}={escape(value)}")
155
+ if self.args.wave or self.args.gui:
156
+ args.add('-debug all')
153
157
  return ' '.join(list(args) + [self.args.xelab_args])
154
158
 
155
159
  def xsim_args(self) -> str:
@@ -62,8 +62,7 @@ class ParserFactory:
62
62
  if parser.is_valid_format(filename):
63
63
  return parser
64
64
  if filename is None:
65
- logger.info("No project specification found, continue with empty project")
66
- return NoParser()
65
+ raise ParserError("Couldn't find any project specification in current directory")
67
66
  else:
68
67
  raise ParserError(f"Couldn't find Parser for parsing '{filename}'")
69
68
 
@@ -1,9 +1,12 @@
1
1
  import yaml
2
2
 
3
- from typing import Dict, List, Optional
3
+ from typing import Dict, Optional
4
4
  from pathlib import Path
5
5
  from argparse import Namespace
6
+ from shlex import split
7
+ from simplhdl.__main__ import parse_arguments
6
8
  from simplhdl.pyedaa.project import Project
9
+ from simplhdl.pyedaa.target import Target
7
10
  from simplhdl.pyedaa.fileset import FileSet # type: ignore
8
11
  from simplhdl.pyedaa.vhdllibrary import VHDLLibrary
9
12
  from simplhdl.pyedaa import (
@@ -18,11 +21,11 @@ from ..parser import ParserFactory, ParserBase
18
21
  class SimplHdlParser(ParserBase):
19
22
 
20
23
  _format_id: str = "#%SimplAPI=1.0"
21
- _core_stack: List[Path] = list()
22
- _core_visited: List[Path] = list()
23
24
 
24
25
  def __init__(self):
25
26
  super().__init__()
27
+ self._core_stack = list()
28
+ self._core_visited = list()
26
29
 
27
30
  def is_valid_format(self, filename: Optional[Path]) -> bool:
28
31
  if filename is None:
@@ -62,6 +65,9 @@ class SimplHdlParser(ParserBase):
62
65
  if 'top' in spec:
63
66
  fileset.TopLevel = spec.get('top')
64
67
 
68
+ for name, value in spec.get('targets', dict()).items():
69
+ target = Target(name=name, args=parse_arguments(split(value)), cwd=self._core_stack[-1].parent)
70
+ project.AddTarget(target)
65
71
  for name, value in spec.get('defines', dict()).items():
66
72
  project.AddDefine(name, value)
67
73
  for name, value in spec.get('parameters', dict()).items():
@@ -23,6 +23,7 @@ def load_builtin_plugins() -> None:
23
23
  Loads builtin plugins.
24
24
  """
25
25
  import_module('simplhdl.info')
26
+ import_module('simplhdl.run')
26
27
  import_module('simplhdl.flows.vcs.vcsflow')
27
28
  import_module('simplhdl.flows.questasim.questasimflow')
28
29
  import_module('simplhdl.flows.modelsim.modelsimflow')
@@ -85,5 +85,5 @@ class FileSet(pm.FileSet):
85
85
  if isinstance(item, VerilogIncludeFile):
86
86
  dirs.append(VerilogIncludeSearchPath(item.Path.parent.absolute()))
87
87
  elif isinstance(item, HDLSearchPath):
88
- dirs.append(HDLSearchPath(item.Path.parent.absolute()))
88
+ dirs.append(HDLSearchPath(item.Path.absolute()))
89
89
  return dirs
@@ -5,6 +5,7 @@ from typing import Dict, List, Optional
5
5
  from pathlib import Path
6
6
  from ..repo import Repo
7
7
  from .design import Design
8
+ from .target import Target
8
9
  from . import (
9
10
  IPSpecificationFile, TCLSourceFile, CocotbPythonFile, SettingFile, HDLIncludeFile,
10
11
  ConstraintFile, VHDLSourceFile, VerilogSourceFile, SystemVerilogSourceFile)
@@ -22,6 +23,7 @@ class Project(pm.Project):
22
23
  _hooks: Dict[str, List[str]]
23
24
  _repos: Dict[str, Repo]
24
25
  _reposdir: Optional[Path]
26
+ _targets: Dict[str, Target]
25
27
 
26
28
  def __init__(
27
29
  self,
@@ -40,6 +42,28 @@ class Project(pm.Project):
40
42
  self._repos = dict()
41
43
  self._reposdir = None
42
44
  self._part = None
45
+ self._targets = dict()
46
+
47
+ def GetTarget(self, name: str) -> Target:
48
+ try:
49
+ target = self._targets[name]
50
+ except KeyError:
51
+ raise FileNotFoundError(f"Target with name '{name}' doesn't exists")
52
+ return target
53
+
54
+ def AddTarget(self, target: Target) -> None:
55
+ if target.name in self._targets:
56
+ logger.warning(f"Ignore '{target.name}', target already exists")
57
+ else:
58
+ self._targets[target.name] = target
59
+
60
+ @property
61
+ def DefaultTarget(self) -> Target:
62
+ try:
63
+ target = next(iter(self._targets.values()))
64
+ except StopIteration:
65
+ raise FileNotFoundError("No targets defined")
66
+ return target
43
67
 
44
68
  @property
45
69
  def ReposDir(self) -> Optional[Path]:
@@ -0,0 +1,31 @@
1
+ from typing import Optional
2
+ from pathlib import Path
3
+
4
+ from argparse import Namespace
5
+
6
+
7
+ class Target:
8
+ def __init__(self, name: str, args: Optional[Namespace] = None, cwd: Path = None) -> None:
9
+ self.name = name
10
+ self._args = args
11
+ self._cwd = cwd or Path('.')
12
+
13
+ @property
14
+ def args(self) -> Namespace:
15
+ if self._args is None:
16
+ raise FileNotFoundError(f"Target '{self.name}' has no arguments defined")
17
+ return self._args
18
+
19
+ @args.setter
20
+ def args(self, args: Namespace) -> None:
21
+ self._args = args
22
+
23
+ @property
24
+ def cwd(self) -> Path:
25
+ if self._cwd is None:
26
+ raise FileNotFoundError(f"Target '{self.name}' has no cwd defined")
27
+ return self._cwd
28
+
29
+ @cwd.setter
30
+ def cwd(self, path: Path) -> None:
31
+ self._cwd = path
@@ -18,7 +18,7 @@ switch $step {
18
18
  puts "\nINFO: Compilation was successful.\n"
19
19
  }
20
20
  }
21
- synthesis {
21
+ elaborate {
22
22
  if {[catch {execute_flow -analysis_and_elaboration} result]} {
23
23
  puts "\nResult: $result\n"
24
24
  puts "ERROR: Analysis and Elaboraion failed. See report files.\n"
@@ -76,7 +76,7 @@ foreach fileset [get_filesets -filter {FILESET_TYPE =~ *Srcs}] {
76
76
  set_property verilog_define "{{dict2str(project.Defines)}}" $fileset
77
77
  }
78
78
  {% endif %}
79
- {% for file in project.DefaultDesign.Files() if 'implementation' in file[UsedIn] %}
79
+ {% for file in files %}
80
80
  {% if file.FileType == VerilogIncludeFile %}
81
81
  add_files "{{file.Path|replace('\\', '/')}}"
82
82
  {% elif file.FileType == SystemVerilogSourceFile %}
@@ -35,8 +35,21 @@ switch $step {
35
35
 
36
36
  }
37
37
 
38
- set runs [list [current_run -synthesis] [current_run -implementation]]
39
- launch_runs [current_run] {*}[split $launch_args]
38
+ if {$step == "lint"} {
39
+ set runs [list [current_run -synthesis]]
40
+ synth_design -top [get_property TOP [current_fileset]] -part [get_property PART [current_project]] -lint
41
+ exit
42
+ } elseif {$step == "elaborate"} {
43
+ set runs [list [current_run -synthesis]]
44
+ synth_design -rtl -rtl_skip_mlo
45
+ exit
46
+ } elseif {$step == "synthesis"} {
47
+ set runs [list [current_run -synthesis]]
48
+ launch_runs [current_run -synthesis]
49
+ } else {
50
+ set runs [list [current_run -synthesis] [current_run -implementation]]
51
+ launch_runs [current_run] {*}[split $launch_args]
52
+ }
40
53
 
41
54
  # wait_on_run renamed to wait_on_runs from Vivado 2022.1
42
55
  if {[package vsatisfies 1.[version -s] 1.2022.1]} {
@@ -19,7 +19,7 @@ simulate: elaborate
19
19
 
20
20
 
21
21
  gui: elaborate
22
- $(XSIM) $(XSIM_FLAGS) $(TOPLEVELS)
22
+ $(XSIM) $(XSIM_FLAGS) $(TOPLEVELS) -gui
23
23
 
24
24
 
25
25
  elaborate: compile
@@ -0,0 +1,51 @@
1
+ from pprint import pprint
2
+ from simplhdl.simplhdl import Simplhdl
3
+ from simplhdl.flow import FlowBase, FlowFactory, FlowError
4
+ from simplhdl.utils import chdir
5
+
6
+
7
+ @FlowFactory.register('run')
8
+ class Run(FlowBase):
9
+
10
+ @classmethod
11
+ def parse_args(self, subparsers) -> None:
12
+ parser = subparsers.add_parser('run', help='Run project targets')
13
+ parser.add_argument(
14
+ '-l',
15
+ '--list',
16
+ nargs='?',
17
+ const='text',
18
+ choices=['text', 'json'],
19
+ help="List project targets"
20
+ )
21
+ parser.add_argument(
22
+ '-t',
23
+ '--target',
24
+ help="Project target to run"
25
+ )
26
+
27
+ def run(self) -> None:
28
+ if self.args.list:
29
+ self._show_list(self.args.list)
30
+ else:
31
+ self._run_target()
32
+
33
+ def _show_list(self, format) -> None:
34
+ if format == 'json':
35
+ targets = list(self.project._targets.keys())
36
+ pprint(targets)
37
+ else:
38
+ print("TARGETS:")
39
+ for target in self.project._targets.keys():
40
+ print(f" - {target}")
41
+
42
+ def _run_target(self) -> None:
43
+ if self.args.target:
44
+ target = self.project.GetTarget(self.args.target)
45
+ else:
46
+ target = self.project.DefaultTarget
47
+ if target.args.flow == 'run':
48
+ raise FlowError("Target flow can't be 'run'")
49
+ with chdir(target.cwd):
50
+ simplhdl = Simplhdl(target.args)
51
+ simplhdl.run()
@@ -140,3 +140,13 @@ def lock(directory: Path) -> Generator[Path, None, None]:
140
140
  yield directory
141
141
  finally:
142
142
  directory.rmdir()
143
+
144
+
145
+ @contextmanager
146
+ def chdir(directory: Path) -> Generator[Path, None, None]:
147
+ old = Path.cwd()
148
+ os.chdir(directory)
149
+ try:
150
+ yield directory
151
+ finally:
152
+ os.chdir(old)
@@ -1,10 +0,0 @@
1
- #%SimplAPI=1.0
2
-
3
- library: work
4
- top: testbench
5
-
6
- dependencies:
7
- - ../adder.yml
8
-
9
- files:
10
- - testbench.sv
@@ -1 +0,0 @@
1
- __version__ = "0.2.2"
File without changes
File without changes
File without changes
File without changes
File without changes
File without changes
File without changes
File without changes
File without changes
File without changes
File without changes
File without changes
File without changes
File without changes
File without changes
File without changes
File without changes
File without changes
File without changes
File without changes
File without changes
File without changes
File without changes
File without changes
File without changes