SimplHDL 0.2.2__tar.gz → 0.2.3__tar.gz

{simplhdl-0.2.2 → simplhdl-0.2.3}/PKG-INFO

@@ -1,6 +1,6 @@
 Metadata-Version: 2.1
 Name: SimplHDL
-Version: 0.2.2
+Version: 0.2.3
 Summary: A framework for simulating and implementing HDL designs
 Author-email: Rasmus Grøndahl Olsen <simplhdl@gmail.com>
 Maintainer-email: Rasmus Grøndahl Olsen <simplhdl@gmail.com>

{simplhdl-0.2.2 → simplhdl-0.2.3}/src/SimplHDL.egg-info/PKG-INFO

@@ -1,6 +1,6 @@
 Metadata-Version: 2.1
 Name: SimplHDL
-Version: 0.2.2
+Version: 0.2.3
 Summary: A framework for simulating and implementing HDL designs
 Author-email: Rasmus Grøndahl Olsen <simplhdl@gmail.com>
 Maintainer-email: Rasmus Grøndahl Olsen <simplhdl@gmail.com>

simplhdl-0.2.3/src/simplhdl/__init__.py

@@ -0,0 +1 @@
+__version__ = "0.2.3"

{simplhdl-0.2.2 → simplhdl-0.2.3}/src/simplhdl/flows/questasim/questasimflow.py

@@ -168,11 +168,11 @@ class QuestaSimFlow(SimulationFlow):
             args.add(f"-g{name}={escape(value)}")
         for name, value in self.project.Parameters.items():
             args.add(f"-g{name}={escape(value)}")
-        if self.args.debug:
+        if self.args.gui or self.args.debug:
             args.add('+acc')
             args.add('-debugdb')
             args.add('-fsmdebug')
-        elif self.args.gui or self.args.do or self.args.wavedump or self.cocotb.enabled:
+        elif self.args.do or self.args.wavedump or self.cocotb.enabled:
             args.add('+acc=npr')
         return ' '.join(list(args) + [self.args.vopt_args])
 
@@ -259,6 +259,9 @@ class QuestaSimFlow(SimulationFlow):
                 command.append('-visualizer')
             command.append('-gui')
         elif self.args.step:
+            if step == "elaborate":
+                command.append('-optimize')
+                return command
             command.append(f'-{step}')
 
         if self.args.do:

{simplhdl-0.2.2 → simplhdl-0.2.3}/src/simplhdl/flows/vivadoflow.py

@@ -83,6 +83,15 @@ class VivadoFlow(FlowBase):
         sh(command, cwd=self.builddir, output=True)
         raise SystemExit
 
+    def get_files(self):
+        files = []
+        seen = []
+        for f in self.project.DefaultDesign.Files():
+            if 'implementation' in f[UsedIn] and f.Path not in seen:
+                seen.append(f.Path)
+                files.append(f)
+        return files
+
     def setup(self):
         self.is_tool_setup()
         os.makedirs(self.builddir, exist_ok=True)
@@ -94,6 +103,7 @@ class VivadoFlow(FlowBase):
             trim_blocks=True)
         template = environment.get_template('project.tcl.j2')
         generate_from_template(template, self.builddir,
+                               files=self.get_files(),
                                dict2str=dict2str,
                                VerilogIncludeFile=VerilogIncludeFile,
                                VerilogSourceFile=VerilogSourceFile,
@@ -119,12 +129,6 @@ class VivadoFlow(FlowBase):
         name = self.project.Name
         command = f"vivado {name}.xpr -mode batch -notrace -source run.tcl -tclargs {step}".split()
         sh(command, cwd=self.builddir, output=True)
-        # jsonfile = self.builddir.joinpath('runs.json')
-        # with jsonfile.open() as f:
-        #     runs: Dict[str, List[str]] = json.load(f)
-        # for name, run in runs.items():
-        #     for script in run:
-        #         sh(['bash', 'launch_run.sh', script], output=True, cwd=self.builddir)
 
     def run(self) -> None:
         if self.args.archive:

{simplhdl-0.2.2 → simplhdl-0.2.3}/src/simplhdl/flows/xsim/xsimflow.py

@@ -133,6 +133,8 @@ class XsimFlow(SimulationFlow):
         args.add(f"-v {self.args.verbose if self.args.verbose < 2 else 2}")
         for name, value in self.project.Defines.items():
             args.add(f"-d {name}={escape(value)}")
+        if self.is_uvm():
+            args.add('-L uvm')
         return ' '.join(list(args) + [self.args.xvlog_args]).strip()
 
     def xvhdl_args(self) -> str:
@@ -150,6 +152,8 @@ class XsimFlow(SimulationFlow):
             args.add(f"--generic_top {name}={escape(value)}")
         for name, value in self.project.Parameters.items():
             args.add(f"--generic_top {name}={escape(value)}")
+        if self.args.wave or self.args.gui:
+            args.add('-debug all')
         return ' '.join(list(args) + [self.args.xelab_args])
 
     def xsim_args(self) -> str:

{simplhdl-0.2.2 → simplhdl-0.2.3}/src/simplhdl/parser.py

@@ -62,8 +62,7 @@ class ParserFactory:
             if parser.is_valid_format(filename):
                 return parser
         if filename is None:
-            logger.info("No project specification found, continue with empty project")
-            return NoParser()
+            raise ParserError("Couldn't find any project specification in current directory")
         else:
             raise ParserError(f"Couldn't find Parser for parsing '{filename}'")
 

{simplhdl-0.2.2 → simplhdl-0.2.3}/src/simplhdl/resources/templates/vivado/project.tcl.j2

@@ -76,7 +76,7 @@ foreach fileset [get_filesets -filter {FILESET_TYPE =~ *Srcs}] {
     set_property verilog_define "{{dict2str(project.Defines)}}" $fileset
 }
 {% endif %}
-{% for file in project.DefaultDesign.Files() if 'implementation' in file[UsedIn] %}
+{% for file in files %}
 {% if file.FileType == VerilogIncludeFile %}
 add_files "{{file.Path|replace('\\', '/')}}"
 {% elif file.FileType == SystemVerilogSourceFile %}

{simplhdl-0.2.2 → simplhdl-0.2.3}/src/simplhdl/resources/templates/vivado/run.tcl.j2

@@ -35,8 +35,13 @@ switch $step {
 
 }
 
-set runs [list [current_run -synthesis] [current_run -implementation]]
-launch_runs [current_run] {*}[split $launch_args]
+if {$step == "synthesis"} {
+    set runs [list [current_run -synthesis]]
+    launch_runs [current_run -synthesis]
+} else {
+    set runs [list [current_run -synthesis] [current_run -implementation]]
+    launch_runs [current_run] {*}[split $launch_args]
+}
 
 # wait_on_run renamed to wait_on_runs from Vivado 2022.1
 if {[package vsatisfies 1.[version -s] 1.2022.1]} {

{simplhdl-0.2.2 → simplhdl-0.2.3}/src/simplhdl/resources/templates/xsim/Makefile.j2

@@ -19,7 +19,7 @@ simulate: elaborate
 
 
 gui: elaborate
-	$(XSIM) $(XSIM_FLAGS) $(TOPLEVELS)
+	$(XSIM) $(XSIM_FLAGS) $(TOPLEVELS) -gui
 
 
 elaborate: compile

simplhdl-0.2.2/src/simplhdl/__init__.py

@@ -1 +0,0 @@
-__version__ = "0.2.2"