SimplHDL 0.2.1__tar.gz → 0.2.3__tar.gz

{simplhdl-0.2.1 → simplhdl-0.2.3}/PKG-INFO

@@ -1,6 +1,6 @@
 Metadata-Version: 2.1
 Name: SimplHDL
-Version: 0.2.1
+Version: 0.2.3
 Summary: A framework for simulating and implementing HDL designs
 Author-email: Rasmus Grøndahl Olsen <simplhdl@gmail.com>
 Maintainer-email: Rasmus Grøndahl Olsen <simplhdl@gmail.com>

{simplhdl-0.2.1 → simplhdl-0.2.3}/src/SimplHDL.egg-info/PKG-INFO

@@ -1,6 +1,6 @@
 Metadata-Version: 2.1
 Name: SimplHDL
-Version: 0.2.1
+Version: 0.2.3
 Summary: A framework for simulating and implementing HDL designs
 Author-email: Rasmus Grøndahl Olsen <simplhdl@gmail.com>
 Maintainer-email: Rasmus Grøndahl Olsen <simplhdl@gmail.com>

simplhdl-0.2.3/src/simplhdl/__init__.py

@@ -0,0 +1 @@
+__version__ = "0.2.3"

{simplhdl-0.2.1 → simplhdl-0.2.3}/src/simplhdl/flows/quartusflow.py

@@ -17,7 +17,8 @@ from ..utils import sh, generate_from_template
 from ..pyedaa import (QuartusIPSpecificationFile, VerilogIncludeFile, VerilogSourceFile,
                       SystemVerilogSourceFile, VHDLSourceFile, ConstraintFile,
                       EDIFNetlistFile, NetlistFile, SettingFile, QuartusSignalTapFile,
-                      QuartusIniFile, QuartusQIPSpecificationFile, QuartusQSYSSpecificationFile)
+                      QuartusIniFile, QuartusQIPSpecificationFile, QuartusQSYSSpecificationFile,
+                      HDLSearchPath, VerilogIncludeSearchPath)
 from ..pyedaa.project import Project
 from ..pyedaa.attributes import UsedIn
 
@@ -97,6 +98,8 @@ class QuartusFlow(ImplementationFlow):
         template = environment.get_template('project.tcl.j2')
         project_updated = generate_from_template(
             template, self.builddir,
+            HDLSearchPath=HDLSearchPath,
+            VerilogIncludeSearchPath=VerilogIncludeSearchPath,
             VerilogIncludeFile=VerilogIncludeFile,
             VerilogSourceFile=VerilogSourceFile,
             SystemVerilogSourceFile=SystemVerilogSourceFile,

{simplhdl-0.2.1 → simplhdl-0.2.3}/src/simplhdl/flows/questasim/questasimflow.py

@@ -168,11 +168,11 @@ class QuestaSimFlow(SimulationFlow):
             args.add(f"-g{name}={escape(value)}")
         for name, value in self.project.Parameters.items():
             args.add(f"-g{name}={escape(value)}")
-        if self.args.debug:
+        if self.args.gui or self.args.debug:
             args.add('+acc')
             args.add('-debugdb')
             args.add('-fsmdebug')
-        elif self.args.gui or self.args.do or self.args.wavedump or self.cocotb.enabled:
+        elif self.args.do or self.args.wavedump or self.cocotb.enabled:
             args.add('+acc=npr')
         return ' '.join(list(args) + [self.args.vopt_args])
 
@@ -259,6 +259,9 @@ class QuestaSimFlow(SimulationFlow):
                 command.append('-visualizer')
             command.append('-gui')
         elif self.args.step:
+            if step == "elaborate":
+                command.append('-optimize')
+                return command
             command.append(f'-{step}')
 
         if self.args.do:

{simplhdl-0.2.1 → simplhdl-0.2.3}/src/simplhdl/flows/simulationflow.py

@@ -56,6 +56,8 @@ class SimulationFlow(FlowBase):
             os.environ['MODULE'] = self.cocotb.module()
 
     def get_globals(self) -> Dict[str, Any]:
+        incdirs = self.project.DefaultDesign.DefaultFileSet.IncludeDirs(usedin='simulation', isrecursive=True)
+        incdirpaths = {f.Path.absolute() for f in incdirs}
         globals = dict()
         globals['libraries'] = (list(self.project.DefaultDesign.VHDLLibraries.values()))
         globals['external_libraries'] = list(self.project.DefaultDesign.ExternalVHDLLibraries.values())
@@ -65,7 +67,7 @@ class SimulationFlow(FlowBase):
         globals['cocotbtop'] = self.cocotb.top
         globals['cocotbhdltype'] = self.cocotb.duttype
         globals['cocotbdut'] = self.cocotb.dut
-        globals['incdirs'] = {f.Path.parent for f in self.project.DefaultDesign.DefaultFileSet.Files(VerilogIncludeFile)}  # noqa E501
+        globals['incdirs'] = incdirpaths
         globals['VerilogSourceFile'] = VerilogSourceFile
         globals['SystemVerilogSourceFile'] = SystemVerilogSourceFile
         globals['VHDLSourceFile'] = VHDLSourceFile
@@ -139,7 +141,7 @@ class SimulationFlow(FlowBase):
                 hashfile=self.hashfile.name)
             template = environment.get_template('fileset.j2')
             output = base.with_suffix('.fileset')
-            includes = {f.Path.parent.absolute() for f in files if isinstance(f, VerilogIncludeFile)}
+            includes = self.get_globals()['incdirs']
             files = [f.Path.absolute() for f in files if not isinstance(f, VerilogIncludeFile)]
             generate_from_template(template, output, args=args, includes=includes, files=files)
             generated.append(output)

{simplhdl-0.2.1 → simplhdl-0.2.3}/src/simplhdl/flows/vivadoflow.py

@@ -83,6 +83,15 @@ class VivadoFlow(FlowBase):
         sh(command, cwd=self.builddir, output=True)
         raise SystemExit
 
+    def get_files(self):
+        files = []
+        seen = []
+        for f in self.project.DefaultDesign.Files():
+            if 'implementation' in f[UsedIn] and f.Path not in seen:
+                seen.append(f.Path)
+                files.append(f)
+        return files
+
     def setup(self):
         self.is_tool_setup()
         os.makedirs(self.builddir, exist_ok=True)
@@ -94,6 +103,7 @@ class VivadoFlow(FlowBase):
             trim_blocks=True)
         template = environment.get_template('project.tcl.j2')
         generate_from_template(template, self.builddir,
+                               files=self.get_files(),
                                dict2str=dict2str,
                                VerilogIncludeFile=VerilogIncludeFile,
                                VerilogSourceFile=VerilogSourceFile,
@@ -119,12 +129,6 @@ class VivadoFlow(FlowBase):
         name = self.project.Name
         command = f"vivado {name}.xpr -mode batch -notrace -source run.tcl -tclargs {step}".split()
         sh(command, cwd=self.builddir, output=True)
-        # jsonfile = self.builddir.joinpath('runs.json')
-        # with jsonfile.open() as f:
-        #     runs: Dict[str, List[str]] = json.load(f)
-        # for name, run in runs.items():
-        #     for script in run:
-        #         sh(['bash', 'launch_run.sh', script], output=True, cwd=self.builddir)
 
     def run(self) -> None:
         if self.args.archive:

{simplhdl-0.2.1 → simplhdl-0.2.3}/src/simplhdl/flows/xsim/xsimflow.py

@@ -133,6 +133,8 @@ class XsimFlow(SimulationFlow):
         args.add(f"-v {self.args.verbose if self.args.verbose < 2 else 2}")
         for name, value in self.project.Defines.items():
             args.add(f"-d {name}={escape(value)}")
+        if self.is_uvm():
+            args.add('-L uvm')
         return ' '.join(list(args) + [self.args.xvlog_args]).strip()
 
     def xvhdl_args(self) -> str:
@@ -150,6 +152,8 @@ class XsimFlow(SimulationFlow):
             args.add(f"--generic_top {name}={escape(value)}")
         for name, value in self.project.Parameters.items():
             args.add(f"--generic_top {name}={escape(value)}")
+        if self.args.wave or self.args.gui:
+            args.add('-debug all')
         return ' '.join(list(args) + [self.args.xelab_args])
 
     def xsim_args(self) -> str:

{simplhdl-0.2.1 → simplhdl-0.2.3}/src/simplhdl/generators/spd.py

@@ -170,9 +170,11 @@ class QuartusIP(GeneratorBase):
 
         return filename
 
-    def run(self, flow: FlowBase):
+    def run(self, flow: FlowBase) -> None:
         os.makedirs(self.builddir, exist_ok=True)
-        for ipfile in self.project.DefaultDesign.DefaultFileSet.Files(fileType=QuartusIPSpecificationFile):
+        ipfiles = list(self.project.DefaultDesign.DefaultFileSet.Files(fileType=QuartusIPSpecificationFile))
+        ipfiles = filter_duplicated_files(ipfiles)
+        for ipfile in ipfiles:
             if ipfile.FileType == QuartusQIPSpecificationFile:
                 continue
             newipfile = self.unpack_ip(ipfile)
@@ -183,3 +185,27 @@ class QuartusIP(GeneratorBase):
                     # Add fileset to parent, then set parent to fileset to make a chain
                     parent._fileSets[fileset.Name] = fileset
                     parent = fileset
+
+
+def filter_duplicated_files(files: List[File]) -> List[File]:
+    """
+    Filter out duplicated files from a list of files. If a file appears more than once,
+    the last one will override the previous ones.
+
+    Args:
+        files (List[File]): The list of files to filter.
+
+    Returns:
+        List[File]: A list of unique files.
+
+    Example:
+        >>> filter_duplicated_files([File('/path1/file1'), File('/path2/file1'), File('/path/file2')]
+        [File('/other/path/to/file1'), File('/path/to/file2')]
+    """
+    unique_files = set(files)
+    filtered_files = dict()
+    for file in unique_files:
+        if file.Path.name in filtered_files:
+            logger.warning(f"Duplicate files - {file.Path} will override {filtered_files[file.Path.name].Path}")
+        filtered_files[file.Path.name] = file
+    return list(filtered_files.values())

{simplhdl-0.2.1 → simplhdl-0.2.3}/src/simplhdl/parser.py

@@ -62,8 +62,7 @@ class ParserFactory:
             if parser.is_valid_format(filename):
                 return parser
         if filename is None:
-            logger.info("No project specification found, continue with empty project")
-            return NoParser()
+            raise ParserError("Couldn't find any project specification in current directory")
         else:
             raise ParserError(f"Couldn't find Parser for parsing '{filename}'")
 

{simplhdl-0.2.1 → simplhdl-0.2.3}/src/simplhdl/pyedaa/__init__.py

@@ -34,6 +34,10 @@ class HDLIncludeFile(SourceFile):
     pass
 
 
+class HDLSearchPath(HDLIncludeFile):
+    pass
+
+
 class HDLSourceFile(pm.HDLSourceFile, FileMixIn):
     _library: HDLLibrary
 
@@ -60,6 +64,10 @@ class HDLSourceFile(pm.HDLSourceFile, FileMixIn):
         self._library = value
 
 
+class VerilogIncludeSearchPath(HDLSearchPath):
+    pass
+
+
 class VerilogIncludeFile(HDLIncludeFile, pm.HumanReadableContent):
     pass
 

{simplhdl-0.2.1 → simplhdl-0.2.3}/src/simplhdl/pyedaa/design.py

@@ -64,5 +64,6 @@ class Design(pm.Design):
     def VHDLLibraries(self) -> Dict[str, VHDLLibrary]:
         libraries = dict()
         libraries.update(self._vhdlLibraries)
-        libraries.update(self.DefaultFileSet.VHDLLibraries)
+        if self.DefaultFileSet:
+            libraries.update(self.DefaultFileSet.VHDLLibraries)
         return libraries

{simplhdl-0.2.1 → simplhdl-0.2.3}/src/simplhdl/pyedaa/fileset.py

@@ -1,6 +1,6 @@
 import pyEDAA.ProjectModel as pm  # type: ignore
 from simplhdl.pyedaa.attributes import UsedIn
-from simplhdl.pyedaa import File
+from simplhdl.pyedaa import File, HDLSearchPath, VerilogIncludeSearchPath, VerilogIncludeFile
 
 from typing import Dict, Generator, List, Optional
 
@@ -73,3 +73,17 @@ class FileSet(pm.FileSet):
         for fileset in self.FileSets.values():
             dependencies += fileset.Dependencies(usedin=usedin, isrecursive=True)
         return dependencies
+
+    def IncludeDirs(self, usedin: Optional[str] = None, isrecursive: bool = False) -> List[HDLSearchPath]:
+        dirs = list()
+        if isrecursive:
+            for _, fileset in self.FileSets.items():
+                dirs += fileset.IncludeDirs(usedin=usedin, isrecursive=True)
+        if usedin:
+            items = [i for i in self._files if usedin in i[UsedIn]]
+        for item in items:
+            if isinstance(item, VerilogIncludeFile):
+                dirs.append(VerilogIncludeSearchPath(item.Path.parent.absolute()))
+            elif isinstance(item, HDLSearchPath):
+                dirs.append(HDLSearchPath(item.Path.parent.absolute()))
+        return dirs

{simplhdl-0.2.1 → simplhdl-0.2.3}/src/simplhdl/resources/templates/quartus/project.tcl.j2

@@ -12,8 +12,11 @@ set_parameter -name {{generic}} {{value}}
 set_global_assignment -name VERILOG_MACRO "{{define}}={{value}}"
 {% endfor %}
 {% for file in project.DefaultDesign.Files() if 'implementation' in file[UsedIn] %}
-{% if file.FileType == VerilogIncludeFile %}
+{% if file.FileType == HDLSearchPath %}
+set_global_assignment -name SEARCH_PATH "{{file.Path}}"
+{% elif file.FileType == VerilogIncludeFile %}
 set_global_assignment -name VERILOG_INCLUDE_FILE "{{file.Path}}"
+set_global_assignment -name SEARCH_PATH "{{file.Path.parent}}"
 {% elif file.FileType == SystemVerilogSourceFile %}
 set_global_assignment -library {{file.Library}} -name SYSTEMVERILOG_FILE "{{file.Path}}"
 {% elif file.FileType == VerilogSourceFile %}

{simplhdl-0.2.1 → simplhdl-0.2.3}/src/simplhdl/resources/templates/vivado/project.tcl.j2

@@ -76,7 +76,7 @@ foreach fileset [get_filesets -filter {FILESET_TYPE =~ *Srcs}] {
     set_property verilog_define "{{dict2str(project.Defines)}}" $fileset
 }
 {% endif %}
-{% for file in project.DefaultDesign.Files() if 'implementation' in file[UsedIn] %}
+{% for file in files %}
 {% if file.FileType == VerilogIncludeFile %}
 add_files "{{file.Path|replace('\\', '/')}}"
 {% elif file.FileType == SystemVerilogSourceFile %}

{simplhdl-0.2.1 → simplhdl-0.2.3}/src/simplhdl/resources/templates/vivado/run.tcl.j2

@@ -35,8 +35,13 @@ switch $step {
 
 }
 
-set runs [list [current_run -synthesis] [current_run -implementation]]
-launch_runs [current_run] {*}[split $launch_args]
+if {$step == "synthesis"} {
+    set runs [list [current_run -synthesis]]
+    launch_runs [current_run -synthesis]
+} else {
+    set runs [list [current_run -synthesis] [current_run -implementation]]
+    launch_runs [current_run] {*}[split $launch_args]
+}
 
 # wait_on_run renamed to wait_on_runs from Vivado 2022.1
 if {[package vsatisfies 1.[version -s] 1.2022.1]} {

{simplhdl-0.2.1 → simplhdl-0.2.3}/src/simplhdl/resources/templates/xsim/Makefile.j2

@@ -19,7 +19,7 @@ simulate: elaborate
 
 
 gui: elaborate
-	$(XSIM) $(XSIM_FLAGS) $(TOPLEVELS)
+	$(XSIM) $(XSIM_FLAGS) $(TOPLEVELS) -gui
 
 
 elaborate: compile

simplhdl-0.2.1/src/simplhdl/__init__.py

@@ -1 +0,0 @@
-__version__ = "0.2.1"