SimplHDL 0.2.1__tar.gz → 0.2.2__tar.gz

{simplhdl-0.2.1 → simplhdl-0.2.2}/PKG-INFO

@@ -1,6 +1,6 @@
 Metadata-Version: 2.1
 Name: SimplHDL
-Version: 0.2.1
+Version: 0.2.2
 Summary: A framework for simulating and implementing HDL designs
 Author-email: Rasmus Grøndahl Olsen <simplhdl@gmail.com>
 Maintainer-email: Rasmus Grøndahl Olsen <simplhdl@gmail.com>

{simplhdl-0.2.1 → simplhdl-0.2.2}/src/SimplHDL.egg-info/PKG-INFO

@@ -1,6 +1,6 @@
 Metadata-Version: 2.1
 Name: SimplHDL
-Version: 0.2.1
+Version: 0.2.2
 Summary: A framework for simulating and implementing HDL designs
 Author-email: Rasmus Grøndahl Olsen <simplhdl@gmail.com>
 Maintainer-email: Rasmus Grøndahl Olsen <simplhdl@gmail.com>

simplhdl-0.2.2/src/simplhdl/__init__.py

@@ -0,0 +1 @@
+__version__ = "0.2.2"

{simplhdl-0.2.1 → simplhdl-0.2.2}/src/simplhdl/flows/quartusflow.py

@@ -17,7 +17,8 @@ from ..utils import sh, generate_from_template
 from ..pyedaa import (QuartusIPSpecificationFile, VerilogIncludeFile, VerilogSourceFile,
                       SystemVerilogSourceFile, VHDLSourceFile, ConstraintFile,
                       EDIFNetlistFile, NetlistFile, SettingFile, QuartusSignalTapFile,
-                      QuartusIniFile, QuartusQIPSpecificationFile, QuartusQSYSSpecificationFile)
+                      QuartusIniFile, QuartusQIPSpecificationFile, QuartusQSYSSpecificationFile,
+                      HDLSearchPath, VerilogIncludeSearchPath)
 from ..pyedaa.project import Project
 from ..pyedaa.attributes import UsedIn
 
@@ -97,6 +98,8 @@ class QuartusFlow(ImplementationFlow):
         template = environment.get_template('project.tcl.j2')
         project_updated = generate_from_template(
             template, self.builddir,
+            HDLSearchPath=HDLSearchPath,
+            VerilogIncludeSearchPath=VerilogIncludeSearchPath,
             VerilogIncludeFile=VerilogIncludeFile,
             VerilogSourceFile=VerilogSourceFile,
             SystemVerilogSourceFile=SystemVerilogSourceFile,

{simplhdl-0.2.1 → simplhdl-0.2.2}/src/simplhdl/flows/simulationflow.py

@@ -56,6 +56,8 @@ class SimulationFlow(FlowBase):
             os.environ['MODULE'] = self.cocotb.module()
 
     def get_globals(self) -> Dict[str, Any]:
+        incdirs = self.project.DefaultDesign.DefaultFileSet.IncludeDirs(usedin='simulation', isrecursive=True)
+        incdirpaths = {f.Path.absolute() for f in incdirs}
         globals = dict()
         globals['libraries'] = (list(self.project.DefaultDesign.VHDLLibraries.values()))
         globals['external_libraries'] = list(self.project.DefaultDesign.ExternalVHDLLibraries.values())
@@ -65,7 +67,7 @@ class SimulationFlow(FlowBase):
         globals['cocotbtop'] = self.cocotb.top
         globals['cocotbhdltype'] = self.cocotb.duttype
         globals['cocotbdut'] = self.cocotb.dut
-        globals['incdirs'] = {f.Path.parent for f in self.project.DefaultDesign.DefaultFileSet.Files(VerilogIncludeFile)}  # noqa E501
+        globals['incdirs'] = incdirpaths
         globals['VerilogSourceFile'] = VerilogSourceFile
         globals['SystemVerilogSourceFile'] = SystemVerilogSourceFile
         globals['VHDLSourceFile'] = VHDLSourceFile
@@ -139,7 +141,7 @@ class SimulationFlow(FlowBase):
                 hashfile=self.hashfile.name)
             template = environment.get_template('fileset.j2')
             output = base.with_suffix('.fileset')
-            includes = {f.Path.parent.absolute() for f in files if isinstance(f, VerilogIncludeFile)}
+            includes = self.get_globals()['incdirs']
             files = [f.Path.absolute() for f in files if not isinstance(f, VerilogIncludeFile)]
             generate_from_template(template, output, args=args, includes=includes, files=files)
             generated.append(output)

{simplhdl-0.2.1 → simplhdl-0.2.2}/src/simplhdl/generators/spd.py

@@ -170,9 +170,11 @@ class QuartusIP(GeneratorBase):
 
         return filename
 
-    def run(self, flow: FlowBase):
+    def run(self, flow: FlowBase) -> None:
         os.makedirs(self.builddir, exist_ok=True)
-        for ipfile in self.project.DefaultDesign.DefaultFileSet.Files(fileType=QuartusIPSpecificationFile):
+        ipfiles = list(self.project.DefaultDesign.DefaultFileSet.Files(fileType=QuartusIPSpecificationFile))
+        ipfiles = filter_duplicated_files(ipfiles)
+        for ipfile in ipfiles:
             if ipfile.FileType == QuartusQIPSpecificationFile:
                 continue
             newipfile = self.unpack_ip(ipfile)
@@ -183,3 +185,27 @@ class QuartusIP(GeneratorBase):
                     # Add fileset to parent, then set parent to fileset to make a chain
                     parent._fileSets[fileset.Name] = fileset
                     parent = fileset
+
+
+def filter_duplicated_files(files: List[File]) -> List[File]:
+    """
+    Filter out duplicated files from a list of files. If a file appears more than once,
+    the last one will override the previous ones.
+
+    Args:
+        files (List[File]): The list of files to filter.
+
+    Returns:
+        List[File]: A list of unique files.
+
+    Example:
+        >>> filter_duplicated_files([File('/path1/file1'), File('/path2/file1'), File('/path/file2')]
+        [File('/other/path/to/file1'), File('/path/to/file2')]
+    """
+    unique_files = set(files)
+    filtered_files = dict()
+    for file in unique_files:
+        if file.Path.name in filtered_files:
+            logger.warning(f"Duplicate files - {file.Path} will override {filtered_files[file.Path.name].Path}")
+        filtered_files[file.Path.name] = file
+    return list(filtered_files.values())

{simplhdl-0.2.1 → simplhdl-0.2.2}/src/simplhdl/pyedaa/__init__.py

@@ -34,6 +34,10 @@ class HDLIncludeFile(SourceFile):
     pass
 
 
+class HDLSearchPath(HDLIncludeFile):
+    pass
+
+
 class HDLSourceFile(pm.HDLSourceFile, FileMixIn):
     _library: HDLLibrary
 
@@ -60,6 +64,10 @@ class HDLSourceFile(pm.HDLSourceFile, FileMixIn):
         self._library = value
 
 
+class VerilogIncludeSearchPath(HDLSearchPath):
+    pass
+
+
 class VerilogIncludeFile(HDLIncludeFile, pm.HumanReadableContent):
     pass
 

{simplhdl-0.2.1 → simplhdl-0.2.2}/src/simplhdl/pyedaa/design.py

@@ -64,5 +64,6 @@ class Design(pm.Design):
     def VHDLLibraries(self) -> Dict[str, VHDLLibrary]:
         libraries = dict()
         libraries.update(self._vhdlLibraries)
-        libraries.update(self.DefaultFileSet.VHDLLibraries)
+        if self.DefaultFileSet:
+            libraries.update(self.DefaultFileSet.VHDLLibraries)
         return libraries

{simplhdl-0.2.1 → simplhdl-0.2.2}/src/simplhdl/pyedaa/fileset.py

@@ -1,6 +1,6 @@
 import pyEDAA.ProjectModel as pm  # type: ignore
 from simplhdl.pyedaa.attributes import UsedIn
-from simplhdl.pyedaa import File
+from simplhdl.pyedaa import File, HDLSearchPath, VerilogIncludeSearchPath, VerilogIncludeFile
 
 from typing import Dict, Generator, List, Optional
 
@@ -73,3 +73,17 @@ class FileSet(pm.FileSet):
         for fileset in self.FileSets.values():
             dependencies += fileset.Dependencies(usedin=usedin, isrecursive=True)
         return dependencies
+
+    def IncludeDirs(self, usedin: Optional[str] = None, isrecursive: bool = False) -> List[HDLSearchPath]:
+        dirs = list()
+        if isrecursive:
+            for _, fileset in self.FileSets.items():
+                dirs += fileset.IncludeDirs(usedin=usedin, isrecursive=True)
+        if usedin:
+            items = [i for i in self._files if usedin in i[UsedIn]]
+        for item in items:
+            if isinstance(item, VerilogIncludeFile):
+                dirs.append(VerilogIncludeSearchPath(item.Path.parent.absolute()))
+            elif isinstance(item, HDLSearchPath):
+                dirs.append(HDLSearchPath(item.Path.parent.absolute()))
+        return dirs

{simplhdl-0.2.1 → simplhdl-0.2.2}/src/simplhdl/resources/templates/quartus/project.tcl.j2

@@ -12,8 +12,11 @@ set_parameter -name {{generic}} {{value}}
 set_global_assignment -name VERILOG_MACRO "{{define}}={{value}}"
 {% endfor %}
 {% for file in project.DefaultDesign.Files() if 'implementation' in file[UsedIn] %}
-{% if file.FileType == VerilogIncludeFile %}
+{% if file.FileType == HDLSearchPath %}
+set_global_assignment -name SEARCH_PATH "{{file.Path}}"
+{% elif file.FileType == VerilogIncludeFile %}
 set_global_assignment -name VERILOG_INCLUDE_FILE "{{file.Path}}"
+set_global_assignment -name SEARCH_PATH "{{file.Path.parent}}"
 {% elif file.FileType == SystemVerilogSourceFile %}
 set_global_assignment -library {{file.Library}} -name SYSTEMVERILOG_FILE "{{file.Path}}"
 {% elif file.FileType == VerilogSourceFile %}

simplhdl-0.2.1/src/simplhdl/__init__.py

@@ -1 +0,0 @@
-__version__ = "0.2.1"