SimplHDL 0.13.4__tar.gz → 0.13.6__tar.gz

{simplhdl-0.13.4/src/simplhdl.egg-info → simplhdl-0.13.6}/PKG-INFO

@@ -1,6 +1,6 @@
 Metadata-Version: 2.4
 Name: simplhdl
-Version: 0.13.4
+Version: 0.13.6
 Summary: A framework for simulating and implementing HDL designs
 Author-email: Rasmus Grøndahl Olsen <simplhdl@gmail.com>
 Maintainer-email: Rasmus Grøndahl Olsen <simplhdl@gmail.com>

{simplhdl-0.13.4 → simplhdl-0.13.6}/src/simplhdl/__init__.py

@@ -1,6 +1,6 @@
 from __future__ import annotations
 
-__version__ = "0.13.4"
+__version__ = "0.13.6"
 
 from .__main__ import parse_arguments
 from .project.design import *

{simplhdl-0.13.4 → simplhdl-0.13.6}/src/simplhdl/cocotb.py

@@ -27,6 +27,50 @@ if TYPE_CHECKING:
 logger = logging.getLogger(__name__)
 
 
+def get_lib_name_path(interface: str, simulator: str) -> Path:
+    output = sh(["cocotb-config", "--lib-name-path", interface, simulator]).strip()
+    path = Path(output)
+    if not path.exists():
+        raise FileNotFoundError(f"{path}: not found")
+    return path
+
+
+def get_lib_entry(interface: str, simulator: str) -> str:
+    output = sh(["cocotb-config", "--lib-entry", interface, simulator]).strip()
+    return output
+
+
+def get_libpython() -> str:
+    output = sh(["cocotb-config", "--libpython"]).strip()
+    path = Path(output)
+    if not path.exists():
+        raise FileNotFoundError(f"{path}: not found")
+    return path
+
+
+def get_pygpi_entry_point() -> str:
+    if Version(version("cocotb")) >= Version("2.1.0"):
+        output = sh(["cocotb-config", "--pygpi-entry-point"]).strip()
+        return output
+    return ""
+
+
+def get_pythonbin() -> str:
+    output = sh(["cocotb-config", "--python-bin"]).strip()
+    path = Path(output)
+    if not path.exists():
+        raise FileNotFoundError(f"{path}: not found")
+    return path
+
+
+def get_gpi_users() -> str:
+    return f"{get_libpython()};{get_pygpi_entry_point()}"
+
+
+def get_gpi_extra(interface: str, simulator: str) -> str:
+    return f"{get_lib_name_path(interface, simulator)}:cocotb{interface}_entry_point"
+
+
 class Cocotb:
     def __init__(self, project: Project, seed: int) -> None:
         self.project = project
@@ -41,29 +85,16 @@ class Cocotb:
         self.has_vhdl = project.defaultDesign.files(type=VhdlFile, usedin=UsedIn.SIMULATION) != []
 
     def lib_name_path(self, simulator: str, interface: str) -> Path:
-        output = sh(["cocotb-config", "--lib-name-path", interface, simulator])
-        path = Path(output)
-        if not path.exists():
-            raise FileNotFoundError(f"{path}: not found")
-        return path
+        return get_lib_name_path(interface, simulator)
 
     def libpython(self) -> str:
-        output = sh(["cocotb-config", "--libpython"])
-        path = Path(output)
-        if not path.exists():
-            raise FileNotFoundError(f"{path}: not found")
-        return path
+        return get_libpython()
 
     def pygpi_entry_point(self) -> str:
-        output = sh(["cocotb-config", "--pygpi-entry-point"])
-        return output.strip()
+        return get_pygpi_entry_point()
 
     def pythonbin(self) -> str:
-        output = sh(["cocotb-config", "--python-bin"])
-        path = Path(output)
-        if not path.exists():
-            raise FileNotFoundError(f"{path}: not found")
-        return path
+        return get_pythonbin()
 
     def module(self) -> str | None:
         if not self.enabled:
@@ -174,28 +205,27 @@ class Cocotb:
         if cocotb_version >= Version("2.1.0"):
             e["COCOTB_TEST_MODULES"] = self.top
             e["COCOTB_TOPLEVEL"] = self.dut
-            e["PYGPI_PYTHON_BIN"] = self.pythonbin()
+            e["PYGPI_PYTHON_BIN"] = get_pythonbin()
             e["COCOTB_RANDOM_SEED"] = str(self.seed)
-            e["GPI_USERS"] = f"{self.libpython()};{self.pygpi_entry_point()}"
+            e["GPI_USERS"] = get_gpi_users()
         elif cocotb_version >= Version("2.0.0"):
             e["COCOTB_TEST_MODULES"] = self.top
             e["COCOTB_TOPLEVEL"] = self.dut
-            e["PYGPI_PYTHON_BIN"] = self.pythonbin()
+            e["PYGPI_PYTHON_BIN"] = get_pythonbin()
             e["COCOTB_RANDOM_SEED"] = str(self.seed)
-            e["LIBPYTHON_LOC"] = self.libpython()
+            e["LIBPYTHON_LOC"] = get_libpython()
         else:
             e["MODULE"] = self.top
             e["TOPLEVEL"] = self.dut
-            e["LIBPYTHON_LOC"] = self.libpython()
+            e["LIBPYTHON_LOC"] = get_libpython()
         e["PYTHONPYCACHEPREFIX"] = "./pycache"
         e["GPI_EXTRA"] = ""
         if self.has_verilog and self.has_vhdl:
             if self.duttype == VhdlFile:
-                lib_name_path = self.lib_name_path("questa", "vpi")
-                e["GPI_EXTRA"] = f"{lib_name_path}:cocotbvpi_entry_point"
+                interface = "vpi"
             elif self.duttype == VerilogFile:
-                lib_name_path = self.lib_name_path("questa", "fli")
-                e["GPI_EXTRA"] = f"{lib_name_path}:cocotbfli_entry_point"
+                interface = "fli"
+            e["GPI_EXTRA"] = get_gpi_extra(interface, "questa")
         if "PYTHONPATH" in e:
             e["PYTHONPATH"] = self.pythonpath + os.pathsep + e.get("PYTHONPATH")
         else:

{simplhdl-0.13.4 → simplhdl-0.13.6}/src/simplhdl/plugin/simulationflow.py

@@ -1,9 +1,5 @@
 from __future__ import annotations
 
-try:
-    from importlib.resources import files as resources_files
-except ImportError:
-    from importlib_resources import files as resources_files
 import logging
 import os
 import shutil
@@ -13,20 +9,30 @@ from typing import Any, Callable, Generator, Tuple
 
 from jinja2 import Environment, FileSystemLoader
 
-from ..cocotb import Cocotb
+from .._compat import resources_files
+from ..cocotb import (
+    Cocotb,
+    get_gpi_extra,
+    get_gpi_users,
+    get_lib_entry,
+    get_lib_name_path,
+    get_libpython,
+    get_pygpi_entry_point,
+    get_pythonbin,
+)
 from ..project.files import (
+    CFile,
+    CppFile,
     File,
     HdlSearchPath,
-    MemoryHexFile,
+    MemoryFile,
     SystemVerilogFile,
+    UsedIn,
     VerilogFile,
     VerilogIncludeFile,
     VhdlFile,
-    CFile,
-    CppFile,
-    UsedIn,
 )
-from ..project.fileset import Fileset, FilesetOrder, FileOrder
+from ..project.fileset import FileOrder, Fileset, FilesetOrder
 from ..project.project import Project
 from ..utils import (
     append_suffix,
@@ -81,6 +87,13 @@ class SimulationFlow(FlowBase):
         globals["defaultlib"] = "work"
         globals["toplevels"] = " ".join(self.cocotb.toplevels)
         globals["pythonpath"] = self.cocotb.pythonpath
+        globals["get_gpi_users"] = get_gpi_users
+        globals["get_gpi_extra"] = get_gpi_extra
+        globals["get_lib_entry"] = get_lib_entry
+        globals["get_lib_name_path"] = get_lib_name_path
+        globals["get_libpython"] = get_libpython
+        globals["get_pythonbin"] = get_pythonbin
+        globals["get_pygpi_entry_point"] = get_pygpi_entry_point
         globals["cocotbtop"] = self.cocotb.top
         globals["cocotbhdltype"] = self.cocotb.duttype
         globals["cocotbdut"] = self.cocotb.dut
@@ -185,7 +198,7 @@ class SimulationFlow(FlowBase):
         return generated
 
     def copy_memory_files(self):
-        for file in self.project.defaultDesign.files(MemoryHexFile):
+        for file in self.project.defaultDesign.files(MemoryFile):
             shutil.copy(file.path.absolute(), self.builddir.absolute())
 
     def is_uvm(self):

{simplhdl-0.13.4 → simplhdl-0.13.6}/src/simplhdl/project/files.py

@@ -325,6 +325,9 @@ class SimulationFile(File):
 class IPSpecificationFile(File): ...
 
 
+class MemoryFile(File): ...
+
+
 @FileFactory.register(extension=".sdc")
 class SdcFile(ConstraintFile): ...
 
@@ -431,11 +434,11 @@ class HdlSearchPath(VerilogIncludeFile):
 
 
 @FileFactory.register(extension=".hex")
-class MemoryHexFile(File): ...
+class MemoryHexFile(MemoryFile): ...
 
 
 @FileFactory.register(extension=".mif")
-class MemoryInitFile(File): ...
+class MemoryInitFile(MemoryFile): ...
 
 
 @FileFactory.register(extension="modelsim.ini")

{simplhdl-0.13.4 → simplhdl-0.13.6/src/simplhdl.egg-info}/PKG-INFO

@@ -1,6 +1,6 @@
 Metadata-Version: 2.4
 Name: simplhdl
-Version: 0.13.4
+Version: 0.13.6
 Summary: A framework for simulating and implementing HDL designs
 Author-email: Rasmus Grøndahl Olsen <simplhdl@gmail.com>
 Maintainer-email: Rasmus Grøndahl Olsen <simplhdl@gmail.com>

{simplhdl-0.13.4 → simplhdl-0.13.6}/src/simplhdl_modelsim/resources/templates/modelsim/cocotb.mk.j2

@@ -21,7 +21,7 @@ else
   export PYTHONPATH := {{pythonpath}}:$(PYTHONPATH)
 endif
 export LIBPYTHON_LOC := $(shell cocotb-config --libpython)
-
+export GPI_USERS := {{get_gpi_users()}}
 export PYGPI_PYTHON_BIN := $(shell cocotb-config --python-bin)
 export COCOTB_TEST_MODULES := {{cocotbtop}}
 export COCOTB_TOPLEVEL := {{cocotbdut}}

{simplhdl-0.13.4 → simplhdl-0.13.6}/src/simplhdl_peakrdl/systemrdl.py

@@ -1,3 +1,5 @@
+from __future__ import annotations
+
 import logging
 import os
 
@@ -9,11 +11,15 @@ except ImportError:
     import tomli as tomllib
 
 from pathlib import Path
-from typing import List
 
 from peakrdl_html import HTMLExporter
 from peakrdl_pyuvm.exporter import PyUVMExporter
-from peakrdl_regblock.cpuif.axi4lite import AXI4Lite_Cpuif_flattened
+from peakrdl_regblock.cpuif.apb3 import APB3_Cpuif, APB3_Cpuif_flattened
+from peakrdl_regblock.cpuif.apb4 import APB4_Cpuif, APB4_Cpuif_flattened
+from peakrdl_regblock.cpuif.avalon import Avalon_Cpuif, Avalon_Cpuif_flattened
+from peakrdl_regblock.cpuif.axi4lite import AXI4Lite_Cpuif, AXI4Lite_Cpuif_flattened
+from peakrdl_regblock.cpuif.obi import OBI_Cpuif, OBI_Cpuif_flattened
+from peakrdl_regblock.cpuif.passthrough import PassthroughCpuif
 from peakrdl_regblock.exporter import RegblockExporter
 from peakrdl_regblock.udps import ALL_UDPS
 from systemrdl import RDLCompileError, RDLCompiler, RDLListener, RDLWalker
@@ -32,12 +38,12 @@ from simplhdl.project.files import (
 
 logger = logging.getLogger(__name__)
 
-seennodetypes: List[AddrmapNode] = []
-leafnodetypes: List[AddrmapNode] = []
-hierachynodetypes: List[AddrmapNode] = []
-leafnodes: List[AddrmapNode] = []
-hierachynodes: List[AddrmapNode] = []
-nodes: List[AddrmapNode] = []
+seennodetypes: list[AddrmapNode] = []
+leafnodetypes: list[AddrmapNode] = []
+hierachynodetypes: list[AddrmapNode] = []
+leafnodes: list[AddrmapNode] = []
+hierachynodes: list[AddrmapNode] = []
+nodes: list[AddrmapNode] = []
 
 
 class Environment(jinja2.Environment):
@@ -66,7 +72,7 @@ class Listener(RDLListener):
                 hierachynodetypes.append(node)
 
 
-def get_template_dirs() -> List[Path]:
+def get_template_dirs() -> list[Path]:
     string = os.getenv("SIMPLHDL_SYSTEMRDL_TEMPLATES")
     if string:
         templates = {Path(p).resolve() for p in string.split(":")}
@@ -74,10 +80,10 @@ def get_template_dirs() -> List[Path]:
             if not t.is_dir():
                 logger.error(f"Directory {t} does not exist")
                 raise SystemError
+        return list(templates)
     else:
-        logger.error("SIMPLHDL_SYSTEMRDL_TEMPLATES is not set, no templates found")
-        raise SystemError
-    return list(templates)
+        logger.debug("SIMPLHDL_SYSTEMRDL_TEMPLATES is not set, no templates found")
+        return []
 
 
 def get_reg_access(reg) -> str:
@@ -171,10 +177,7 @@ def is_leaf(node):
     """
     Check if node is leaf, meaning it has no children address maps
     """
-    if AddrmapNode not in [type(c) for c in node.children()]:
-        return True
-    else:
-        return False
+    return AddrmapNode not in [type(c) for c in node.children()]
 
 
 def mask(node):
@@ -201,10 +204,27 @@ class PeakRdlGenerator(GeneratorBase):
             fileset.insert_file_after(rdlfile, VhdlFile(outputfile))
 
     def peakrdl_regblock(self, node, outputdir, config) -> None:
+        cpuif_dict = {
+            "passthrough": PassthroughCpuif,
+            "apb3": APB3_Cpuif,
+            "apb3-flat": APB3_Cpuif_flattened,
+            "apb4": APB4_Cpuif,
+            "apb4-flat": APB4_Cpuif_flattened,
+            "axi4-lite": AXI4Lite_Cpuif,
+            "axi4-lite-flat": AXI4Lite_Cpuif_flattened,
+            "avalon-mm": Avalon_Cpuif,
+            "avalon-mm-flat": Avalon_Cpuif_flattened,
+            "obi": OBI_Cpuif,
+            "obi-flat": OBI_Cpuif_flattened,
+        }
+        cpuif_name = config.get("cpuif", "apb3")
+        if cpuif_name not in cpuif_dict:
+            raise ValueError(f"Unsupported CPU interface: {cpuif_name}, must be one of {list(cpuif_dict.keys())}")
+
         RegblockExporter().export(
             node=node,
             output_dir=str(outputdir.resolve()),
-            cpuif_cls=AXI4Lite_Cpuif_flattened,
+            cpuif_cls=cpuif_dict.get(cpuif_name),
             module_name=config.get("module_name", f"{node.type_name}_addrmap"),
             package_name=config.get("package_name", f"{node.type_name}_pkg"),
             address_width=config.get("address_width", 32),
@@ -222,7 +242,7 @@ class PeakRdlGenerator(GeneratorBase):
     def run(self, flow: FlowBase):  # noqa: C901
         rdlfiles = self.project.defaultDesign.files(type=SystemRdlFile, order=FileOrder.COMPILE)
         output_dir = self.builddir.joinpath("systemrdl")
-        config = dict()
+        config: dict = {}
         if os.getenv("SIMPLHDL_CONFIG"):
             tomlfile = Path(os.getenv("SIMPLHDL_CONFIG"))
             try:

{simplhdl-0.13.4 → simplhdl-0.13.6}/src/simplhdl_vcs/resources/templates/vcs/cocotb.mk.j2

@@ -4,13 +4,14 @@ ifndef PYTHONPATH
 else
   export PYTHONPATH := {{pythonpath}}:$(PYTHONPATH)
 endif
-export LIBPYTHON_LOC := $(shell cocotb-config --libpython)
+export LIBPYTHON_LOC := {{get_libpython()}}
 
-VCS_FLAGS += +warn=noVPI-CT-NS +vpi -P pli.tab -load $(shell cocotb-config --lib-name-path vpi vcs)
+VCS_FLAGS += +warn=noVPI-CT-NS +vpi -P pli.tab -load {{get_lib_name_path("vpi", "vcs")}}
 VCS_FLAGS += -debug_access+r+w+nomemcbk -debug_region+cell+encrypt -debug_acc+pp+f+dmptf
 
-export PYGPI_PYTHON_BIN := $(shell cocotb-config --python-bin)
+export PYGPI_PYTHON_BIN := {{get_pythonbin()}}
 export COCOTB_TEST_MODULES := {{cocotbtop}}
 export COCOTB_TOPLEVEL := {{cocotbdut}}
 export MODULE := {{cocotbtop}}
 export TOPLEVEL := {{cocotbdut}}
+export GPI_USERS := {{get_gpi_users()}}