SimplHDL 0.13.2__tar.gz → 0.13.4__tar.gz

{simplhdl-0.13.2/src/simplhdl.egg-info → simplhdl-0.13.4}/PKG-INFO

@@ -1,6 +1,6 @@
 Metadata-Version: 2.4
 Name: simplhdl
-Version: 0.13.2
+Version: 0.13.4
 Summary: A framework for simulating and implementing HDL designs
 Author-email: Rasmus Grøndahl Olsen <simplhdl@gmail.com>
 Maintainer-email: Rasmus Grøndahl Olsen <simplhdl@gmail.com>

{simplhdl-0.13.2 → simplhdl-0.13.4}/src/simplhdl/__init__.py

@@ -1,6 +1,6 @@
 from __future__ import annotations
 
-__version__ = "0.13.2"
+__version__ = "0.13.4"
 
 from .__main__ import parse_arguments
 from .project.design import *

{simplhdl-0.13.2 → simplhdl-0.13.4/src/simplhdl.egg-info}/PKG-INFO

@@ -1,6 +1,6 @@
 Metadata-Version: 2.4
 Name: simplhdl
-Version: 0.13.2
+Version: 0.13.4
 Summary: A framework for simulating and implementing HDL designs
 Author-email: Rasmus Grøndahl Olsen <simplhdl@gmail.com>
 Maintainer-email: Rasmus Grøndahl Olsen <simplhdl@gmail.com>

{simplhdl-0.13.2 → simplhdl-0.13.4}/src/simplhdl_icarus/resources/templates/icarus/cocotb.mk.j2

@@ -6,6 +6,7 @@ else
 endif
 export LIBPYTHON_LOC := $(shell cocotb-config --libpython)
 export PYGPI_PYTHON_BIN := $(shell cocotb-config --python-bin)
+export GPI_USERS := $(shell cocotb-config --libpython);$(shell cocotb-config --pygpi-entry-point)
 export COCOTB_TEST_MODULES := {{cocotbtop}}
 export COCOTB_TOPLEVEL := {{cocotbdut}}
 export MODULE := {{cocotbtop}}

{simplhdl-0.13.2 → simplhdl-0.13.4}/src/simplhdl_quartus/quartusexport/quartusexportflow.py

@@ -16,6 +16,7 @@ from simplhdl.project.files import (
     QuartusIpFile,
     QuartusQipFile,
     QuartusQsfFile,
+    QuartusQsysFile,
     SystemVerilogFile,
     UsedIn,
     VerilogFile,
@@ -68,7 +69,7 @@ class QuartusExportFlow(ImplementationFlow):
                 continue
             elif isinstance(file, (ConstraintFile, QuartusQipFile)):
                 pass
-            elif isinstance(file, (HdlSearchPath, QuartusIpFile)):
+            elif isinstance(file, (HdlSearchPath, QuartusIpFile, QuartusQsysFile)):
                 continue
             # Ignore files generated inside builddir when determining source root
             if not resolved.is_relative_to(self.builddir.resolve()):
@@ -99,7 +100,7 @@ class QuartusExportFlow(ImplementationFlow):
             elif isinstance(file, (ConstraintFile, QuartusQipFile)):
                 dest.parent.mkdir(parents=True, exist_ok=True)
                 shutil.copyfile(file.path, dest)
-            elif isinstance(file, (HdlSearchPath, QuartusIpFile)):
+            elif isinstance(file, (HdlSearchPath, QuartusIpFile, QuartusQsysFile)):
                 dest = file.path
             elif isinstance(file, (VerilogFile, VerilogIncludeFile, SystemVerilogFile, VhdlFile)):
                 dest.parent.mkdir(parents=True, exist_ok=True)