SimplHDL 0.1.0__tar.gz → 0.1.2__tar.gz
This diff represents the content of publicly available package versions that have been released to one of the supported registries. The information contained in this diff is provided for informational purposes only and reflects changes between package versions as they appear in their respective public registries.
- {simplhdl-0.1.0 → simplhdl-0.1.2}/PKG-INFO +1 -1
- {simplhdl-0.1.0 → simplhdl-0.1.2}/src/SimplHDL.egg-info/PKG-INFO +1 -1
- simplhdl-0.1.2/src/simplhdl/__init__.py +1 -0
- {simplhdl-0.1.0 → simplhdl-0.1.2}/src/simplhdl/flows/quartusflow.py +16 -4
- {simplhdl-0.1.0 → simplhdl-0.1.2}/src/simplhdl/flows/vivadoflow.py +3 -1
- {simplhdl-0.1.0 → simplhdl-0.1.2}/src/simplhdl/generators/ipxact.py +3 -2
- {simplhdl-0.1.0 → simplhdl-0.1.2}/src/simplhdl/generators/spd.py +13 -1
- {simplhdl-0.1.0 → simplhdl-0.1.2}/src/simplhdl/pyedaa/__init__.py +8 -0
- {simplhdl-0.1.0 → simplhdl-0.1.2}/src/simplhdl/resources/templates/quartus/run.tcl.j2 +3 -0
- {simplhdl-0.1.0 → simplhdl-0.1.2}/src/simplhdl/resources/templates/vivado/project.tcl.j2 +2 -2
- simplhdl-0.1.0/src/simplhdl/__init__.py +0 -1
- {simplhdl-0.1.0 → simplhdl-0.1.2}/.github/workflows/publish.yml +0 -0
- {simplhdl-0.1.0 → simplhdl-0.1.2}/.gitignore +0 -0
- {simplhdl-0.1.0 → simplhdl-0.1.2}/.readthedocs.yaml +0 -0
- {simplhdl-0.1.0 → simplhdl-0.1.2}/LICENSE +0 -0
- {simplhdl-0.1.0 → simplhdl-0.1.2}/README.md +0 -0
- {simplhdl-0.1.0 → simplhdl-0.1.2}/docs/_static/simplhdl_dark.png +0 -0
- {simplhdl-0.1.0 → simplhdl-0.1.2}/docs/_static/simplhdl_light.png +0 -0
- {simplhdl-0.1.0 → simplhdl-0.1.2}/docs/_static/simplhdl_light_1.png +0 -0
- {simplhdl-0.1.0 → simplhdl-0.1.2}/docs/conf.py +0 -0
- {simplhdl-0.1.0 → simplhdl-0.1.2}/docs/drawing.svg +0 -0
- {simplhdl-0.1.0 → simplhdl-0.1.2}/docs/flows/ghdl.rst +0 -0
- {simplhdl-0.1.0 → simplhdl-0.1.2}/docs/flows/icarus.rst +0 -0
- {simplhdl-0.1.0 → simplhdl-0.1.2}/docs/flows/quartus.rst +0 -0
- {simplhdl-0.1.0 → simplhdl-0.1.2}/docs/flows/questasim.rst +0 -0
- {simplhdl-0.1.0 → simplhdl-0.1.2}/docs/flows/vcs.rst +0 -0
- {simplhdl-0.1.0 → simplhdl-0.1.2}/docs/flows/vivado.rst +0 -0
- {simplhdl-0.1.0 → simplhdl-0.1.2}/docs/flows/xsim.rst +0 -0
- {simplhdl-0.1.0 → simplhdl-0.1.2}/docs/flows.rst +0 -0
- {simplhdl-0.1.0 → simplhdl-0.1.2}/docs/index.rst +0 -0
- {simplhdl-0.1.0 → simplhdl-0.1.2}/docs/intel-ips.md +0 -0
- {simplhdl-0.1.0 → simplhdl-0.1.2}/docs/introduction.rst +0 -0
- {simplhdl-0.1.0 → simplhdl-0.1.2}/docs/plugins.rst +0 -0
- {simplhdl-0.1.0 → simplhdl-0.1.2}/docs/requirements.txt +0 -0
- {simplhdl-0.1.0 → simplhdl-0.1.2}/examples/hdl/adder/adder.yml +0 -0
- {simplhdl-0.1.0 → simplhdl-0.1.2}/examples/hdl/adder/hdl/adder.sv +0 -0
- {simplhdl-0.1.0 → simplhdl-0.1.2}/examples/hdl/adder/sim/testbench.sv +0 -0
- {simplhdl-0.1.0 → simplhdl-0.1.2}/examples/hdl/adder/sim/testbench.yml +0 -0
- {simplhdl-0.1.0 → simplhdl-0.1.2}/examples/hdl/adder/syn/build.yml +0 -0
- {simplhdl-0.1.0 → simplhdl-0.1.2}/examples/hdl/adder/syn/placement.xdc +0 -0
- {simplhdl-0.1.0 → simplhdl-0.1.2}/examples/hdl/adder/syn/timing.xdc +0 -0
- {simplhdl-0.1.0 → simplhdl-0.1.2}/examples/hdl/adder/syn/top.sv +0 -0
- {simplhdl-0.1.0 → simplhdl-0.1.2}/examples/hdl/alu/alu.yml +0 -0
- {simplhdl-0.1.0 → simplhdl-0.1.2}/examples/hdl/alu/hdl/add.sv +0 -0
- {simplhdl-0.1.0 → simplhdl-0.1.2}/examples/hdl/alu/hdl/alu.sv +0 -0
- {simplhdl-0.1.0 → simplhdl-0.1.2}/examples/hdl/alu/hdl/mul.sv +0 -0
- {simplhdl-0.1.0 → simplhdl-0.1.2}/examples/hdl/alu/hdl/sub.sv +0 -0
- {simplhdl-0.1.0 → simplhdl-0.1.2}/examples/hdl/alu/sim/pyuvm/alu_vip/__init__.py +0 -0
- {simplhdl-0.1.0 → simplhdl-0.1.2}/examples/hdl/alu/sim/pyuvm/alu_vip/agent.py +0 -0
- {simplhdl-0.1.0 → simplhdl-0.1.2}/examples/hdl/alu/sim/pyuvm/alu_vip/aluif.py +0 -0
- {simplhdl-0.1.0 → simplhdl-0.1.2}/examples/hdl/alu/sim/pyuvm/alu_vip/driver.py +0 -0
- {simplhdl-0.1.0 → simplhdl-0.1.2}/examples/hdl/alu/sim/pyuvm/alu_vip/monitor.py +0 -0
- {simplhdl-0.1.0 → simplhdl-0.1.2}/examples/hdl/alu/sim/pyuvm/alu_vip/sequenceitem.py +0 -0
- {simplhdl-0.1.0 → simplhdl-0.1.2}/examples/hdl/alu/sim/pyuvm/alu_vip/sequencer.py +0 -0
- {simplhdl-0.1.0 → simplhdl-0.1.2}/examples/hdl/alu/sim/pyuvm/clock_vip/__init__.py +0 -0
- {simplhdl-0.1.0 → simplhdl-0.1.2}/examples/hdl/alu/sim/pyuvm/clock_vip/agent.py +0 -0
- {simplhdl-0.1.0 → simplhdl-0.1.2}/examples/hdl/alu/sim/pyuvm/clock_vip/clockif.py +0 -0
- {simplhdl-0.1.0 → simplhdl-0.1.2}/examples/hdl/alu/sim/pyuvm/pyuvm.yml +0 -0
- {simplhdl-0.1.0 → simplhdl-0.1.2}/examples/hdl/alu/sim/pyuvm/test/__init__.py +0 -0
- {simplhdl-0.1.0 → simplhdl-0.1.2}/examples/hdl/alu/sim/pyuvm/test/env.py +0 -0
- {simplhdl-0.1.0 → simplhdl-0.1.2}/examples/hdl/alu/sim/pyuvm/test/seq_lib.py +0 -0
- {simplhdl-0.1.0 → simplhdl-0.1.2}/examples/hdl/alu/sim/pyuvm/test/test.py +0 -0
- {simplhdl-0.1.0 → simplhdl-0.1.2}/examples/hdl/alu/sim/pyuvm/testbench.py +0 -0
- {simplhdl-0.1.0 → simplhdl-0.1.2}/examples/hdl/alu/sim/uvm/alu_vip/agent.svh +0 -0
- {simplhdl-0.1.0 → simplhdl-0.1.2}/examples/hdl/alu/sim/uvm/alu_vip/alu_vip.sv +0 -0
- {simplhdl-0.1.0 → simplhdl-0.1.2}/examples/hdl/alu/sim/uvm/alu_vip/alu_vip.yml +0 -0
- {simplhdl-0.1.0 → simplhdl-0.1.2}/examples/hdl/alu/sim/uvm/alu_vip/driver.svh +0 -0
- {simplhdl-0.1.0 → simplhdl-0.1.2}/examples/hdl/alu/sim/uvm/alu_vip/env.svh +0 -0
- {simplhdl-0.1.0 → simplhdl-0.1.2}/examples/hdl/alu/sim/uvm/alu_vip/monitor.svh +0 -0
- {simplhdl-0.1.0 → simplhdl-0.1.2}/examples/hdl/alu/sim/uvm/alu_vip/sequence_item.svh +0 -0
- {simplhdl-0.1.0 → simplhdl-0.1.2}/examples/hdl/alu/sim/uvm/tb_env/seq_lib/add_seq.svh +0 -0
- {simplhdl-0.1.0 → simplhdl-0.1.2}/examples/hdl/alu/sim/uvm/tb_env/seq_lib/base_seq.svh +0 -0
- {simplhdl-0.1.0 → simplhdl-0.1.2}/examples/hdl/alu/sim/uvm/tb_env/tb_env.sv +0 -0
- {simplhdl-0.1.0 → simplhdl-0.1.2}/examples/hdl/alu/sim/uvm/tb_env/tb_env.yml +0 -0
- {simplhdl-0.1.0 → simplhdl-0.1.2}/examples/hdl/alu/sim/uvm/tb_env/test/base_test.svh +0 -0
- {simplhdl-0.1.0 → simplhdl-0.1.2}/examples/hdl/alu/sim/uvm/tb_env/test/test_add.svh +0 -0
- {simplhdl-0.1.0 → simplhdl-0.1.2}/examples/hdl/alu/sim/uvm/testbench/alu_if.sv +0 -0
- {simplhdl-0.1.0 → simplhdl-0.1.2}/examples/hdl/alu/sim/uvm/testbench/testbench.sv +0 -0
- {simplhdl-0.1.0 → simplhdl-0.1.2}/examples/hdl/alu/sim/uvm/testbench/testbench.yml +0 -0
- {simplhdl-0.1.0 → simplhdl-0.1.2}/examples/hdl/alu/sim/uvm/testcases/test_add/test_add.yml +0 -0
- {simplhdl-0.1.0 → simplhdl-0.1.2}/examples/hdl/alu/syn/build.yml +0 -0
- {simplhdl-0.1.0 → simplhdl-0.1.2}/examples/hdl/alu/syn/placement.xdc +0 -0
- {simplhdl-0.1.0 → simplhdl-0.1.2}/examples/hdl/alu/syn/timing.xdc +0 -0
- {simplhdl-0.1.0 → simplhdl-0.1.2}/examples/hdl/hello/build.sbt +0 -0
- {simplhdl-0.1.0 → simplhdl-0.1.2}/examples/hdl/hello/hello.yml +0 -0
- {simplhdl-0.1.0 → simplhdl-0.1.2}/examples/hdl/hello/src/main/scala/Hello.scala +0 -0
- {simplhdl-0.1.0 → simplhdl-0.1.2}/examples/hdl/hello/syn/build.yml +0 -0
- {simplhdl-0.1.0 → simplhdl-0.1.2}/examples/plugins/simple_parser/setup.py +0 -0
- {simplhdl-0.1.0 → simplhdl-0.1.2}/examples/plugins/simple_parser/src/simple_parser/__init__.py +0 -0
- {simplhdl-0.1.0 → simplhdl-0.1.2}/examples/plugins/simple_parser/src/simple_parser/simple_parser.py +0 -0
- {simplhdl-0.1.0 → simplhdl-0.1.2}/pyproject.toml +0 -0
- {simplhdl-0.1.0 → simplhdl-0.1.2}/setup.cfg +0 -0
- {simplhdl-0.1.0 → simplhdl-0.1.2}/src/SimplHDL.egg-info/SOURCES.txt +0 -0
- {simplhdl-0.1.0 → simplhdl-0.1.2}/src/SimplHDL.egg-info/dependency_links.txt +0 -0
- {simplhdl-0.1.0 → simplhdl-0.1.2}/src/SimplHDL.egg-info/entry_points.txt +0 -0
- {simplhdl-0.1.0 → simplhdl-0.1.2}/src/SimplHDL.egg-info/requires.txt +0 -0
- {simplhdl-0.1.0 → simplhdl-0.1.2}/src/SimplHDL.egg-info/top_level.txt +0 -0
- {simplhdl-0.1.0 → simplhdl-0.1.2}/src/simplhdl/__main__.py +0 -0
- {simplhdl-0.1.0 → simplhdl-0.1.2}/src/simplhdl/cocotb.py +0 -0
- {simplhdl-0.1.0 → simplhdl-0.1.2}/src/simplhdl/flow.py +0 -0
- {simplhdl-0.1.0 → simplhdl-0.1.2}/src/simplhdl/flows/__init__.py +0 -0
- {simplhdl-0.1.0 → simplhdl-0.1.2}/src/simplhdl/flows/flake8/flake8flow.py +0 -0
- {simplhdl-0.1.0 → simplhdl-0.1.2}/src/simplhdl/flows/implementationflow.py +0 -0
- {simplhdl-0.1.0 → simplhdl-0.1.2}/src/simplhdl/flows/lint/lintflow.py +0 -0
- {simplhdl-0.1.0 → simplhdl-0.1.2}/src/simplhdl/flows/modelsimflow.py +0 -0
- {simplhdl-0.1.0 → simplhdl-0.1.2}/src/simplhdl/flows/quartusdse/__init__.py +0 -0
- {simplhdl-0.1.0 → simplhdl-0.1.2}/src/simplhdl/flows/quartusdse/quartusdseflow.py +0 -0
- {simplhdl-0.1.0 → simplhdl-0.1.2}/src/simplhdl/flows/questasim/__init__.py +0 -0
- {simplhdl-0.1.0 → simplhdl-0.1.2}/src/simplhdl/flows/questasim/questasimflow.py +0 -0
- {simplhdl-0.1.0 → simplhdl-0.1.2}/src/simplhdl/flows/rivierapro/__init__.py +0 -0
- {simplhdl-0.1.0 → simplhdl-0.1.2}/src/simplhdl/flows/rivierapro/rivieraproflow.py +0 -0
- {simplhdl-0.1.0 → simplhdl-0.1.2}/src/simplhdl/flows/simulationflow.py +0 -0
- {simplhdl-0.1.0 → simplhdl-0.1.2}/src/simplhdl/flows/vcs/__init__.py +0 -0
- {simplhdl-0.1.0 → simplhdl-0.1.2}/src/simplhdl/flows/vcs/vcsflow.py +0 -0
- {simplhdl-0.1.0 → simplhdl-0.1.2}/src/simplhdl/flows/verible/__init__.py +0 -0
- {simplhdl-0.1.0 → simplhdl-0.1.2}/src/simplhdl/flows/verible/veribleflow.py +0 -0
- {simplhdl-0.1.0 → simplhdl-0.1.2}/src/simplhdl/flows/vsg/__init__.py +0 -0
- {simplhdl-0.1.0 → simplhdl-0.1.2}/src/simplhdl/flows/vsg/vsgflow.py +0 -0
- {simplhdl-0.1.0 → simplhdl-0.1.2}/src/simplhdl/flows/xsim/__init__.py +0 -0
- {simplhdl-0.1.0 → simplhdl-0.1.2}/src/simplhdl/flows/xsim/xsimflow.py +0 -0
- {simplhdl-0.1.0 → simplhdl-0.1.2}/src/simplhdl/generator.py +0 -0
- {simplhdl-0.1.0 → simplhdl-0.1.2}/src/simplhdl/generators/__init__.py +0 -0
- {simplhdl-0.1.0 → simplhdl-0.1.2}/src/simplhdl/generators/chisel.py +0 -0
- {simplhdl-0.1.0 → simplhdl-0.1.2}/src/simplhdl/generators/systemrdl.py +0 -0
- {simplhdl-0.1.0 → simplhdl-0.1.2}/src/simplhdl/info.py +0 -0
- {simplhdl-0.1.0 → simplhdl-0.1.2}/src/simplhdl/parser.py +0 -0
- {simplhdl-0.1.0 → simplhdl-0.1.2}/src/simplhdl/parsers/__init__.py +0 -0
- {simplhdl-0.1.0 → simplhdl-0.1.2}/src/simplhdl/parsers/fusesocparser.py +0 -0
- {simplhdl-0.1.0 → simplhdl-0.1.2}/src/simplhdl/parsers/simplhdlparser.py +0 -0
- {simplhdl-0.1.0 → simplhdl-0.1.2}/src/simplhdl/plugins.py +0 -0
- {simplhdl-0.1.0 → simplhdl-0.1.2}/src/simplhdl/pyedaa/attributes.py +0 -0
- {simplhdl-0.1.0 → simplhdl-0.1.2}/src/simplhdl/pyedaa/design.py +0 -0
- {simplhdl-0.1.0 → simplhdl-0.1.2}/src/simplhdl/pyedaa/fileset.py +0 -0
- {simplhdl-0.1.0 → simplhdl-0.1.2}/src/simplhdl/pyedaa/filetypes.py +0 -0
- {simplhdl-0.1.0 → simplhdl-0.1.2}/src/simplhdl/pyedaa/project.py +0 -0
- {simplhdl-0.1.0 → simplhdl-0.1.2}/src/simplhdl/pyedaa/vhdllibrary.py +0 -0
- {simplhdl-0.1.0 → simplhdl-0.1.2}/src/simplhdl/repo.py +0 -0
- {simplhdl-0.1.0 → simplhdl-0.1.2}/src/simplhdl/resources/__init__.py +0 -0
- {simplhdl-0.1.0 → simplhdl-0.1.2}/src/simplhdl/resources/templates/__init__.py +0 -0
- {simplhdl-0.1.0 → simplhdl-0.1.2}/src/simplhdl/resources/templates/flake8/__init__.py +0 -0
- {simplhdl-0.1.0 → simplhdl-0.1.2}/src/simplhdl/resources/templates/flake8/setup.cfg.j2 +0 -0
- {simplhdl-0.1.0 → simplhdl-0.1.2}/src/simplhdl/resources/templates/quartus/__init__.py +0 -0
- {simplhdl-0.1.0 → simplhdl-0.1.2}/src/simplhdl/resources/templates/quartus/project.tcl.j2 +0 -0
- {simplhdl-0.1.0 → simplhdl-0.1.2}/src/simplhdl/resources/templates/questasim/Makefile.j2 +0 -0
- {simplhdl-0.1.0 → simplhdl-0.1.2}/src/simplhdl/resources/templates/questasim/__init__.py +0 -0
- {simplhdl-0.1.0 → simplhdl-0.1.2}/src/simplhdl/resources/templates/questasim/cocotb.mk.j2 +0 -0
- {simplhdl-0.1.0 → simplhdl-0.1.2}/src/simplhdl/resources/templates/questasim/dependencies.mk.j2 +0 -0
- {simplhdl-0.1.0 → simplhdl-0.1.2}/src/simplhdl/resources/templates/questasim/files.j2 +0 -0
- {simplhdl-0.1.0 → simplhdl-0.1.2}/src/simplhdl/resources/templates/questasim/fileset.j2 +0 -0
- {simplhdl-0.1.0 → simplhdl-0.1.2}/src/simplhdl/resources/templates/questasim/gui.do.j2 +0 -0
- {simplhdl-0.1.0 → simplhdl-0.1.2}/src/simplhdl/resources/templates/questasim/project.mk.j2 +0 -0
- {simplhdl-0.1.0 → simplhdl-0.1.2}/src/simplhdl/resources/templates/questasim/run.do.j2 +0 -0
- {simplhdl-0.1.0 → simplhdl-0.1.2}/src/simplhdl/resources/templates/rivierapro/Makefile.j2 +0 -0
- {simplhdl-0.1.0 → simplhdl-0.1.2}/src/simplhdl/resources/templates/rivierapro/__init__.py +0 -0
- {simplhdl-0.1.0 → simplhdl-0.1.2}/src/simplhdl/resources/templates/rivierapro/cocotb.mk.j2 +0 -0
- {simplhdl-0.1.0 → simplhdl-0.1.2}/src/simplhdl/resources/templates/rivierapro/dependencies.mk.j2 +0 -0
- {simplhdl-0.1.0 → simplhdl-0.1.2}/src/simplhdl/resources/templates/rivierapro/files.j2 +0 -0
- {simplhdl-0.1.0 → simplhdl-0.1.2}/src/simplhdl/resources/templates/rivierapro/fileset.j2 +0 -0
- {simplhdl-0.1.0 → simplhdl-0.1.2}/src/simplhdl/resources/templates/rivierapro/project.mk.j2 +0 -0
- {simplhdl-0.1.0 → simplhdl-0.1.2}/src/simplhdl/resources/templates/vcs/Makefile.j2 +0 -0
- {simplhdl-0.1.0 → simplhdl-0.1.2}/src/simplhdl/resources/templates/vcs/__init__.py +0 -0
- {simplhdl-0.1.0 → simplhdl-0.1.2}/src/simplhdl/resources/templates/vcs/cocotb.mk.j2 +0 -0
- {simplhdl-0.1.0 → simplhdl-0.1.2}/src/simplhdl/resources/templates/vcs/dependencies.mk.j2 +0 -0
- {simplhdl-0.1.0 → simplhdl-0.1.2}/src/simplhdl/resources/templates/vcs/files.j2 +0 -0
- {simplhdl-0.1.0 → simplhdl-0.1.2}/src/simplhdl/resources/templates/vcs/fileset.j2 +0 -0
- {simplhdl-0.1.0 → simplhdl-0.1.2}/src/simplhdl/resources/templates/vcs/pli.tab.j2 +0 -0
- {simplhdl-0.1.0 → simplhdl-0.1.2}/src/simplhdl/resources/templates/vcs/project.mk.j2 +0 -0
- {simplhdl-0.1.0 → simplhdl-0.1.2}/src/simplhdl/resources/templates/vcs/synopsys_sim.setup.j2 +0 -0
- {simplhdl-0.1.0 → simplhdl-0.1.2}/src/simplhdl/resources/templates/vcs/vcs.parameters.j2 +0 -0
- {simplhdl-0.1.0 → simplhdl-0.1.2}/src/simplhdl/resources/templates/verible/__init__.py +0 -0
- {simplhdl-0.1.0 → simplhdl-0.1.2}/src/simplhdl/resources/templates/verible/rules.cfg.j2 +0 -0
- {simplhdl-0.1.0 → simplhdl-0.1.2}/src/simplhdl/resources/templates/vivado/__init__.py +0 -0
- {simplhdl-0.1.0 → simplhdl-0.1.2}/src/simplhdl/resources/templates/vivado/launch_run.sh.j2 +0 -0
- {simplhdl-0.1.0 → simplhdl-0.1.2}/src/simplhdl/resources/templates/vivado/run.tcl.j2 +0 -0
- {simplhdl-0.1.0 → simplhdl-0.1.2}/src/simplhdl/resources/templates/vivado/steps.tcl.j2 +0 -0
- {simplhdl-0.1.0 → simplhdl-0.1.2}/src/simplhdl/resources/templates/vsg/__init__.py +0 -0
- {simplhdl-0.1.0 → simplhdl-0.1.2}/src/simplhdl/resources/templates/vsg/files.json.j2 +0 -0
- {simplhdl-0.1.0 → simplhdl-0.1.2}/src/simplhdl/resources/templates/vsg/rules.yml.j2 +0 -0
- {simplhdl-0.1.0 → simplhdl-0.1.2}/src/simplhdl/resources/templates/xsim/Makefile.j2 +0 -0
- {simplhdl-0.1.0 → simplhdl-0.1.2}/src/simplhdl/resources/templates/xsim/__init__.py +0 -0
- {simplhdl-0.1.0 → simplhdl-0.1.2}/src/simplhdl/resources/templates/xsim/cocotb.mk.j2 +0 -0
- {simplhdl-0.1.0 → simplhdl-0.1.2}/src/simplhdl/resources/templates/xsim/dependencies.mk.j2 +0 -0
- {simplhdl-0.1.0 → simplhdl-0.1.2}/src/simplhdl/resources/templates/xsim/files.j2 +0 -0
- {simplhdl-0.1.0 → simplhdl-0.1.2}/src/simplhdl/resources/templates/xsim/fileset.j2 +0 -0
- {simplhdl-0.1.0 → simplhdl-0.1.2}/src/simplhdl/resources/templates/xsim/project.mk.j2 +0 -0
- {simplhdl-0.1.0 → simplhdl-0.1.2}/src/simplhdl/simplhdl.py +0 -0
- {simplhdl-0.1.0 → simplhdl-0.1.2}/src/simplhdl/tools.py +0 -0
- {simplhdl-0.1.0 → simplhdl-0.1.2}/src/simplhdl/utils.py +0 -0
- {simplhdl-0.1.0 → simplhdl-0.1.2}/tests/test_dummy.py +0 -0
- {simplhdl-0.1.0 → simplhdl-0.1.2}/tox.ini +0 -0
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@@ -0,0 +1 @@
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1
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+
__version__ = "0.1.2"
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@@ -34,7 +34,7 @@ class QuartusFlow(ImplementationFlow):
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34
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'-s',
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35
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'--step',
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action='store',
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37
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-
choices=['synthesis', 'implement', 'finalize', 'compile'],
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37
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+
choices=['project', 'synthesis', 'implement', 'finalize', 'compile'],
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default='compile',
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help="flow step to run"
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40
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)
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@@ -45,8 +45,12 @@ class QuartusFlow(ImplementationFlow):
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)
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46
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parser.add_argument(
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'--archive',
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48
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-
choices=[
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49
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-
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+
choices=[
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'project',
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'project-service-request',
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'project-source'
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],
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help="Archive Quartus project, settings and results"
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)
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def __init__(self, name, args: Namespace, project: Project, builddir: Path):
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@@ -64,7 +68,15 @@ class QuartusFlow(ImplementationFlow):
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64
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def archive(self) -> None:
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name = self.project.Name
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-
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71
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+
if self.args.archive == 'project':
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72
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fileset = 'full_db'
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73
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elif self.args.archive == 'project-service-request':
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74
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fileset = 'sr'
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75
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elif self.args.archive == 'project-source':
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76
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fileset = 'basic'
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else:
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78
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raise Exception("Unknown value for argument --archive: {self.args.archive}")
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79
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command = f"quartus_sh --archive -use_file_set {fileset} -revision {name} -no_discover -output {name}.qar {name}" # noqa
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68
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sh(command.split(), output=True, cwd=self.builddir)
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raise SystemExit
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70
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@@ -14,7 +14,7 @@ from ..resources.templates import vivado as templates
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14
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from ..utils import sh, generate_from_template, dict2str
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from ..pyedaa import (VivadoIPSpecificationFile, VerilogIncludeFile, VerilogSourceFile,
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SystemVerilogSourceFile, VHDLSourceFile, ConstraintFile,
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17
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-
EDIFNetlistFile, NetlistFile)
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17
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+
EDIFNetlistFile, NetlistFile, VivadoBDTclFile, VivadoProjectStepFile)
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from ..pyedaa.project import Project
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from ..pyedaa.attributes import UsedIn
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@@ -101,6 +101,8 @@ class VivadoFlow(FlowBase):
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VHDLSourceFile=VHDLSourceFile,
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ConstraintFile=ConstraintFile,
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VivadoIPSpecificationFile=VivadoIPSpecificationFile,
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VivadoProjectStepFile=VivadoProjectStepFile,
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VivadoBDTclFile=VivadoBDTclFile,
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EDIFNetlistFile=EDIFNetlistFile,
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NetlistFile=NetlistFile,
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project=self.project,
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@@ -185,8 +185,9 @@ class VivadoIP(GeneratorBase):
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for fileset in filesets:
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corefiles += component.files(fileset)
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for file_element in corefiles:
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-
file
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-
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# Get the .xml file next to the .xci file
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file = component.filepath(file_element).with_suffix('.xml')
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if file.exists():
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files += self.get_files(file)
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for view in component.views('.*simulation.*'):
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filesets = component.filesets(view)
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@@ -123,7 +123,19 @@ class QuartusIP(GeneratorBase):
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123
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md5file = dest.with_suffix('.md5')
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ipdir.mkdir(exist_ok=True)
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if filename.FileType == QuartusQSYSSpecificationFile:
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-
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+
update = True
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dir = filename.Path.with_suffix('')
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if dir.exists():
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if md5file.exists():
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update = not md5check(filename.Path, dir, filename=md5file)
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if update:
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copy(str(filename.Path), str(dest.with_suffix('.qsys')))
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md5write(filename.Path, filename=md5file)
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if dir.exists():
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copytree(str(dir), str(dest.with_suffix('')), dirs_exist_ok=True)
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md5write(filename.Path, dir, filename=md5file)
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logger.debug(f"Copy {filename.Path} to {dest}")
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+
filename._path = dest.with_suffix('.qsys').absolute()
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elif filename.FileType == QuartusIPCompressedSpecificationFile:
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update = True
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@@ -158,6 +158,14 @@ class VivadoIPSpecificationFile(IPSpecificationFile):
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158
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pass
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159
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160
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161
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class VivadoBDTclFile(TCLSourceFile):
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162
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pass
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164
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165
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class VivadoProjectStepFile(TCLSourceFile):
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pass
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167
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class SystemRDLSourceFile(File):
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pass
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@@ -99,10 +99,10 @@ add_files "{{file.Path|replace('\\', '/')}}"
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read_edif "{{file.Path|replace('\\', '/')}}"
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{% elif file.Path.suffix == '.bd' %}
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read_bd "{{file.Path|replace('\\', '/')}}"
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-
{% elif file.
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{% elif file.FileType == VivadoBDTclFile %}
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send_msg_id {SimplHDL PRJ-3} {INFO} "Sourcing BD tcl file {{file.Path|replace('\\', '/')}}: this might take some time."
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source_script "{{file.Path|replace('\\', '/')}}"
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-
{% elif file.
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{% elif file.FileType == VivadoProjectStepFile %}
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add_files -fileset utils_1 "{{file.Path|replace('\\', '/')}}"
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global step
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set step {project}
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{simplhdl-0.1.0 → simplhdl-0.1.2}/examples/plugins/simple_parser/src/simple_parser/__init__.py
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