SimplHDL 0.1.0__tar.gz → 0.1.2__tar.gz

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Files changed (190) hide show
  1. {simplhdl-0.1.0 → simplhdl-0.1.2}/PKG-INFO +1 -1
  2. {simplhdl-0.1.0 → simplhdl-0.1.2}/src/SimplHDL.egg-info/PKG-INFO +1 -1
  3. simplhdl-0.1.2/src/simplhdl/__init__.py +1 -0
  4. {simplhdl-0.1.0 → simplhdl-0.1.2}/src/simplhdl/flows/quartusflow.py +16 -4
  5. {simplhdl-0.1.0 → simplhdl-0.1.2}/src/simplhdl/flows/vivadoflow.py +3 -1
  6. {simplhdl-0.1.0 → simplhdl-0.1.2}/src/simplhdl/generators/ipxact.py +3 -2
  7. {simplhdl-0.1.0 → simplhdl-0.1.2}/src/simplhdl/generators/spd.py +13 -1
  8. {simplhdl-0.1.0 → simplhdl-0.1.2}/src/simplhdl/pyedaa/__init__.py +8 -0
  9. {simplhdl-0.1.0 → simplhdl-0.1.2}/src/simplhdl/resources/templates/quartus/run.tcl.j2 +3 -0
  10. {simplhdl-0.1.0 → simplhdl-0.1.2}/src/simplhdl/resources/templates/vivado/project.tcl.j2 +2 -2
  11. simplhdl-0.1.0/src/simplhdl/__init__.py +0 -1
  12. {simplhdl-0.1.0 → simplhdl-0.1.2}/.github/workflows/publish.yml +0 -0
  13. {simplhdl-0.1.0 → simplhdl-0.1.2}/.gitignore +0 -0
  14. {simplhdl-0.1.0 → simplhdl-0.1.2}/.readthedocs.yaml +0 -0
  15. {simplhdl-0.1.0 → simplhdl-0.1.2}/LICENSE +0 -0
  16. {simplhdl-0.1.0 → simplhdl-0.1.2}/README.md +0 -0
  17. {simplhdl-0.1.0 → simplhdl-0.1.2}/docs/_static/simplhdl_dark.png +0 -0
  18. {simplhdl-0.1.0 → simplhdl-0.1.2}/docs/_static/simplhdl_light.png +0 -0
  19. {simplhdl-0.1.0 → simplhdl-0.1.2}/docs/_static/simplhdl_light_1.png +0 -0
  20. {simplhdl-0.1.0 → simplhdl-0.1.2}/docs/conf.py +0 -0
  21. {simplhdl-0.1.0 → simplhdl-0.1.2}/docs/drawing.svg +0 -0
  22. {simplhdl-0.1.0 → simplhdl-0.1.2}/docs/flows/ghdl.rst +0 -0
  23. {simplhdl-0.1.0 → simplhdl-0.1.2}/docs/flows/icarus.rst +0 -0
  24. {simplhdl-0.1.0 → simplhdl-0.1.2}/docs/flows/quartus.rst +0 -0
  25. {simplhdl-0.1.0 → simplhdl-0.1.2}/docs/flows/questasim.rst +0 -0
  26. {simplhdl-0.1.0 → simplhdl-0.1.2}/docs/flows/vcs.rst +0 -0
  27. {simplhdl-0.1.0 → simplhdl-0.1.2}/docs/flows/vivado.rst +0 -0
  28. {simplhdl-0.1.0 → simplhdl-0.1.2}/docs/flows/xsim.rst +0 -0
  29. {simplhdl-0.1.0 → simplhdl-0.1.2}/docs/flows.rst +0 -0
  30. {simplhdl-0.1.0 → simplhdl-0.1.2}/docs/index.rst +0 -0
  31. {simplhdl-0.1.0 → simplhdl-0.1.2}/docs/intel-ips.md +0 -0
  32. {simplhdl-0.1.0 → simplhdl-0.1.2}/docs/introduction.rst +0 -0
  33. {simplhdl-0.1.0 → simplhdl-0.1.2}/docs/plugins.rst +0 -0
  34. {simplhdl-0.1.0 → simplhdl-0.1.2}/docs/requirements.txt +0 -0
  35. {simplhdl-0.1.0 → simplhdl-0.1.2}/examples/hdl/adder/adder.yml +0 -0
  36. {simplhdl-0.1.0 → simplhdl-0.1.2}/examples/hdl/adder/hdl/adder.sv +0 -0
  37. {simplhdl-0.1.0 → simplhdl-0.1.2}/examples/hdl/adder/sim/testbench.sv +0 -0
  38. {simplhdl-0.1.0 → simplhdl-0.1.2}/examples/hdl/adder/sim/testbench.yml +0 -0
  39. {simplhdl-0.1.0 → simplhdl-0.1.2}/examples/hdl/adder/syn/build.yml +0 -0
  40. {simplhdl-0.1.0 → simplhdl-0.1.2}/examples/hdl/adder/syn/placement.xdc +0 -0
  41. {simplhdl-0.1.0 → simplhdl-0.1.2}/examples/hdl/adder/syn/timing.xdc +0 -0
  42. {simplhdl-0.1.0 → simplhdl-0.1.2}/examples/hdl/adder/syn/top.sv +0 -0
  43. {simplhdl-0.1.0 → simplhdl-0.1.2}/examples/hdl/alu/alu.yml +0 -0
  44. {simplhdl-0.1.0 → simplhdl-0.1.2}/examples/hdl/alu/hdl/add.sv +0 -0
  45. {simplhdl-0.1.0 → simplhdl-0.1.2}/examples/hdl/alu/hdl/alu.sv +0 -0
  46. {simplhdl-0.1.0 → simplhdl-0.1.2}/examples/hdl/alu/hdl/mul.sv +0 -0
  47. {simplhdl-0.1.0 → simplhdl-0.1.2}/examples/hdl/alu/hdl/sub.sv +0 -0
  48. {simplhdl-0.1.0 → simplhdl-0.1.2}/examples/hdl/alu/sim/pyuvm/alu_vip/__init__.py +0 -0
  49. {simplhdl-0.1.0 → simplhdl-0.1.2}/examples/hdl/alu/sim/pyuvm/alu_vip/agent.py +0 -0
  50. {simplhdl-0.1.0 → simplhdl-0.1.2}/examples/hdl/alu/sim/pyuvm/alu_vip/aluif.py +0 -0
  51. {simplhdl-0.1.0 → simplhdl-0.1.2}/examples/hdl/alu/sim/pyuvm/alu_vip/driver.py +0 -0
  52. {simplhdl-0.1.0 → simplhdl-0.1.2}/examples/hdl/alu/sim/pyuvm/alu_vip/monitor.py +0 -0
  53. {simplhdl-0.1.0 → simplhdl-0.1.2}/examples/hdl/alu/sim/pyuvm/alu_vip/sequenceitem.py +0 -0
  54. {simplhdl-0.1.0 → simplhdl-0.1.2}/examples/hdl/alu/sim/pyuvm/alu_vip/sequencer.py +0 -0
  55. {simplhdl-0.1.0 → simplhdl-0.1.2}/examples/hdl/alu/sim/pyuvm/clock_vip/__init__.py +0 -0
  56. {simplhdl-0.1.0 → simplhdl-0.1.2}/examples/hdl/alu/sim/pyuvm/clock_vip/agent.py +0 -0
  57. {simplhdl-0.1.0 → simplhdl-0.1.2}/examples/hdl/alu/sim/pyuvm/clock_vip/clockif.py +0 -0
  58. {simplhdl-0.1.0 → simplhdl-0.1.2}/examples/hdl/alu/sim/pyuvm/pyuvm.yml +0 -0
  59. {simplhdl-0.1.0 → simplhdl-0.1.2}/examples/hdl/alu/sim/pyuvm/test/__init__.py +0 -0
  60. {simplhdl-0.1.0 → simplhdl-0.1.2}/examples/hdl/alu/sim/pyuvm/test/env.py +0 -0
  61. {simplhdl-0.1.0 → simplhdl-0.1.2}/examples/hdl/alu/sim/pyuvm/test/seq_lib.py +0 -0
  62. {simplhdl-0.1.0 → simplhdl-0.1.2}/examples/hdl/alu/sim/pyuvm/test/test.py +0 -0
  63. {simplhdl-0.1.0 → simplhdl-0.1.2}/examples/hdl/alu/sim/pyuvm/testbench.py +0 -0
  64. {simplhdl-0.1.0 → simplhdl-0.1.2}/examples/hdl/alu/sim/uvm/alu_vip/agent.svh +0 -0
  65. {simplhdl-0.1.0 → simplhdl-0.1.2}/examples/hdl/alu/sim/uvm/alu_vip/alu_vip.sv +0 -0
  66. {simplhdl-0.1.0 → simplhdl-0.1.2}/examples/hdl/alu/sim/uvm/alu_vip/alu_vip.yml +0 -0
  67. {simplhdl-0.1.0 → simplhdl-0.1.2}/examples/hdl/alu/sim/uvm/alu_vip/driver.svh +0 -0
  68. {simplhdl-0.1.0 → simplhdl-0.1.2}/examples/hdl/alu/sim/uvm/alu_vip/env.svh +0 -0
  69. {simplhdl-0.1.0 → simplhdl-0.1.2}/examples/hdl/alu/sim/uvm/alu_vip/monitor.svh +0 -0
  70. {simplhdl-0.1.0 → simplhdl-0.1.2}/examples/hdl/alu/sim/uvm/alu_vip/sequence_item.svh +0 -0
  71. {simplhdl-0.1.0 → simplhdl-0.1.2}/examples/hdl/alu/sim/uvm/tb_env/seq_lib/add_seq.svh +0 -0
  72. {simplhdl-0.1.0 → simplhdl-0.1.2}/examples/hdl/alu/sim/uvm/tb_env/seq_lib/base_seq.svh +0 -0
  73. {simplhdl-0.1.0 → simplhdl-0.1.2}/examples/hdl/alu/sim/uvm/tb_env/tb_env.sv +0 -0
  74. {simplhdl-0.1.0 → simplhdl-0.1.2}/examples/hdl/alu/sim/uvm/tb_env/tb_env.yml +0 -0
  75. {simplhdl-0.1.0 → simplhdl-0.1.2}/examples/hdl/alu/sim/uvm/tb_env/test/base_test.svh +0 -0
  76. {simplhdl-0.1.0 → simplhdl-0.1.2}/examples/hdl/alu/sim/uvm/tb_env/test/test_add.svh +0 -0
  77. {simplhdl-0.1.0 → simplhdl-0.1.2}/examples/hdl/alu/sim/uvm/testbench/alu_if.sv +0 -0
  78. {simplhdl-0.1.0 → simplhdl-0.1.2}/examples/hdl/alu/sim/uvm/testbench/testbench.sv +0 -0
  79. {simplhdl-0.1.0 → simplhdl-0.1.2}/examples/hdl/alu/sim/uvm/testbench/testbench.yml +0 -0
  80. {simplhdl-0.1.0 → simplhdl-0.1.2}/examples/hdl/alu/sim/uvm/testcases/test_add/test_add.yml +0 -0
  81. {simplhdl-0.1.0 → simplhdl-0.1.2}/examples/hdl/alu/syn/build.yml +0 -0
  82. {simplhdl-0.1.0 → simplhdl-0.1.2}/examples/hdl/alu/syn/placement.xdc +0 -0
  83. {simplhdl-0.1.0 → simplhdl-0.1.2}/examples/hdl/alu/syn/timing.xdc +0 -0
  84. {simplhdl-0.1.0 → simplhdl-0.1.2}/examples/hdl/hello/build.sbt +0 -0
  85. {simplhdl-0.1.0 → simplhdl-0.1.2}/examples/hdl/hello/hello.yml +0 -0
  86. {simplhdl-0.1.0 → simplhdl-0.1.2}/examples/hdl/hello/src/main/scala/Hello.scala +0 -0
  87. {simplhdl-0.1.0 → simplhdl-0.1.2}/examples/hdl/hello/syn/build.yml +0 -0
  88. {simplhdl-0.1.0 → simplhdl-0.1.2}/examples/plugins/simple_parser/setup.py +0 -0
  89. {simplhdl-0.1.0 → simplhdl-0.1.2}/examples/plugins/simple_parser/src/simple_parser/__init__.py +0 -0
  90. {simplhdl-0.1.0 → simplhdl-0.1.2}/examples/plugins/simple_parser/src/simple_parser/simple_parser.py +0 -0
  91. {simplhdl-0.1.0 → simplhdl-0.1.2}/pyproject.toml +0 -0
  92. {simplhdl-0.1.0 → simplhdl-0.1.2}/setup.cfg +0 -0
  93. {simplhdl-0.1.0 → simplhdl-0.1.2}/src/SimplHDL.egg-info/SOURCES.txt +0 -0
  94. {simplhdl-0.1.0 → simplhdl-0.1.2}/src/SimplHDL.egg-info/dependency_links.txt +0 -0
  95. {simplhdl-0.1.0 → simplhdl-0.1.2}/src/SimplHDL.egg-info/entry_points.txt +0 -0
  96. {simplhdl-0.1.0 → simplhdl-0.1.2}/src/SimplHDL.egg-info/requires.txt +0 -0
  97. {simplhdl-0.1.0 → simplhdl-0.1.2}/src/SimplHDL.egg-info/top_level.txt +0 -0
  98. {simplhdl-0.1.0 → simplhdl-0.1.2}/src/simplhdl/__main__.py +0 -0
  99. {simplhdl-0.1.0 → simplhdl-0.1.2}/src/simplhdl/cocotb.py +0 -0
  100. {simplhdl-0.1.0 → simplhdl-0.1.2}/src/simplhdl/flow.py +0 -0
  101. {simplhdl-0.1.0 → simplhdl-0.1.2}/src/simplhdl/flows/__init__.py +0 -0
  102. {simplhdl-0.1.0 → simplhdl-0.1.2}/src/simplhdl/flows/flake8/flake8flow.py +0 -0
  103. {simplhdl-0.1.0 → simplhdl-0.1.2}/src/simplhdl/flows/implementationflow.py +0 -0
  104. {simplhdl-0.1.0 → simplhdl-0.1.2}/src/simplhdl/flows/lint/lintflow.py +0 -0
  105. {simplhdl-0.1.0 → simplhdl-0.1.2}/src/simplhdl/flows/modelsimflow.py +0 -0
  106. {simplhdl-0.1.0 → simplhdl-0.1.2}/src/simplhdl/flows/quartusdse/__init__.py +0 -0
  107. {simplhdl-0.1.0 → simplhdl-0.1.2}/src/simplhdl/flows/quartusdse/quartusdseflow.py +0 -0
  108. {simplhdl-0.1.0 → simplhdl-0.1.2}/src/simplhdl/flows/questasim/__init__.py +0 -0
  109. {simplhdl-0.1.0 → simplhdl-0.1.2}/src/simplhdl/flows/questasim/questasimflow.py +0 -0
  110. {simplhdl-0.1.0 → simplhdl-0.1.2}/src/simplhdl/flows/rivierapro/__init__.py +0 -0
  111. {simplhdl-0.1.0 → simplhdl-0.1.2}/src/simplhdl/flows/rivierapro/rivieraproflow.py +0 -0
  112. {simplhdl-0.1.0 → simplhdl-0.1.2}/src/simplhdl/flows/simulationflow.py +0 -0
  113. {simplhdl-0.1.0 → simplhdl-0.1.2}/src/simplhdl/flows/vcs/__init__.py +0 -0
  114. {simplhdl-0.1.0 → simplhdl-0.1.2}/src/simplhdl/flows/vcs/vcsflow.py +0 -0
  115. {simplhdl-0.1.0 → simplhdl-0.1.2}/src/simplhdl/flows/verible/__init__.py +0 -0
  116. {simplhdl-0.1.0 → simplhdl-0.1.2}/src/simplhdl/flows/verible/veribleflow.py +0 -0
  117. {simplhdl-0.1.0 → simplhdl-0.1.2}/src/simplhdl/flows/vsg/__init__.py +0 -0
  118. {simplhdl-0.1.0 → simplhdl-0.1.2}/src/simplhdl/flows/vsg/vsgflow.py +0 -0
  119. {simplhdl-0.1.0 → simplhdl-0.1.2}/src/simplhdl/flows/xsim/__init__.py +0 -0
  120. {simplhdl-0.1.0 → simplhdl-0.1.2}/src/simplhdl/flows/xsim/xsimflow.py +0 -0
  121. {simplhdl-0.1.0 → simplhdl-0.1.2}/src/simplhdl/generator.py +0 -0
  122. {simplhdl-0.1.0 → simplhdl-0.1.2}/src/simplhdl/generators/__init__.py +0 -0
  123. {simplhdl-0.1.0 → simplhdl-0.1.2}/src/simplhdl/generators/chisel.py +0 -0
  124. {simplhdl-0.1.0 → simplhdl-0.1.2}/src/simplhdl/generators/systemrdl.py +0 -0
  125. {simplhdl-0.1.0 → simplhdl-0.1.2}/src/simplhdl/info.py +0 -0
  126. {simplhdl-0.1.0 → simplhdl-0.1.2}/src/simplhdl/parser.py +0 -0
  127. {simplhdl-0.1.0 → simplhdl-0.1.2}/src/simplhdl/parsers/__init__.py +0 -0
  128. {simplhdl-0.1.0 → simplhdl-0.1.2}/src/simplhdl/parsers/fusesocparser.py +0 -0
  129. {simplhdl-0.1.0 → simplhdl-0.1.2}/src/simplhdl/parsers/simplhdlparser.py +0 -0
  130. {simplhdl-0.1.0 → simplhdl-0.1.2}/src/simplhdl/plugins.py +0 -0
  131. {simplhdl-0.1.0 → simplhdl-0.1.2}/src/simplhdl/pyedaa/attributes.py +0 -0
  132. {simplhdl-0.1.0 → simplhdl-0.1.2}/src/simplhdl/pyedaa/design.py +0 -0
  133. {simplhdl-0.1.0 → simplhdl-0.1.2}/src/simplhdl/pyedaa/fileset.py +0 -0
  134. {simplhdl-0.1.0 → simplhdl-0.1.2}/src/simplhdl/pyedaa/filetypes.py +0 -0
  135. {simplhdl-0.1.0 → simplhdl-0.1.2}/src/simplhdl/pyedaa/project.py +0 -0
  136. {simplhdl-0.1.0 → simplhdl-0.1.2}/src/simplhdl/pyedaa/vhdllibrary.py +0 -0
  137. {simplhdl-0.1.0 → simplhdl-0.1.2}/src/simplhdl/repo.py +0 -0
  138. {simplhdl-0.1.0 → simplhdl-0.1.2}/src/simplhdl/resources/__init__.py +0 -0
  139. {simplhdl-0.1.0 → simplhdl-0.1.2}/src/simplhdl/resources/templates/__init__.py +0 -0
  140. {simplhdl-0.1.0 → simplhdl-0.1.2}/src/simplhdl/resources/templates/flake8/__init__.py +0 -0
  141. {simplhdl-0.1.0 → simplhdl-0.1.2}/src/simplhdl/resources/templates/flake8/setup.cfg.j2 +0 -0
  142. {simplhdl-0.1.0 → simplhdl-0.1.2}/src/simplhdl/resources/templates/quartus/__init__.py +0 -0
  143. {simplhdl-0.1.0 → simplhdl-0.1.2}/src/simplhdl/resources/templates/quartus/project.tcl.j2 +0 -0
  144. {simplhdl-0.1.0 → simplhdl-0.1.2}/src/simplhdl/resources/templates/questasim/Makefile.j2 +0 -0
  145. {simplhdl-0.1.0 → simplhdl-0.1.2}/src/simplhdl/resources/templates/questasim/__init__.py +0 -0
  146. {simplhdl-0.1.0 → simplhdl-0.1.2}/src/simplhdl/resources/templates/questasim/cocotb.mk.j2 +0 -0
  147. {simplhdl-0.1.0 → simplhdl-0.1.2}/src/simplhdl/resources/templates/questasim/dependencies.mk.j2 +0 -0
  148. {simplhdl-0.1.0 → simplhdl-0.1.2}/src/simplhdl/resources/templates/questasim/files.j2 +0 -0
  149. {simplhdl-0.1.0 → simplhdl-0.1.2}/src/simplhdl/resources/templates/questasim/fileset.j2 +0 -0
  150. {simplhdl-0.1.0 → simplhdl-0.1.2}/src/simplhdl/resources/templates/questasim/gui.do.j2 +0 -0
  151. {simplhdl-0.1.0 → simplhdl-0.1.2}/src/simplhdl/resources/templates/questasim/project.mk.j2 +0 -0
  152. {simplhdl-0.1.0 → simplhdl-0.1.2}/src/simplhdl/resources/templates/questasim/run.do.j2 +0 -0
  153. {simplhdl-0.1.0 → simplhdl-0.1.2}/src/simplhdl/resources/templates/rivierapro/Makefile.j2 +0 -0
  154. {simplhdl-0.1.0 → simplhdl-0.1.2}/src/simplhdl/resources/templates/rivierapro/__init__.py +0 -0
  155. {simplhdl-0.1.0 → simplhdl-0.1.2}/src/simplhdl/resources/templates/rivierapro/cocotb.mk.j2 +0 -0
  156. {simplhdl-0.1.0 → simplhdl-0.1.2}/src/simplhdl/resources/templates/rivierapro/dependencies.mk.j2 +0 -0
  157. {simplhdl-0.1.0 → simplhdl-0.1.2}/src/simplhdl/resources/templates/rivierapro/files.j2 +0 -0
  158. {simplhdl-0.1.0 → simplhdl-0.1.2}/src/simplhdl/resources/templates/rivierapro/fileset.j2 +0 -0
  159. {simplhdl-0.1.0 → simplhdl-0.1.2}/src/simplhdl/resources/templates/rivierapro/project.mk.j2 +0 -0
  160. {simplhdl-0.1.0 → simplhdl-0.1.2}/src/simplhdl/resources/templates/vcs/Makefile.j2 +0 -0
  161. {simplhdl-0.1.0 → simplhdl-0.1.2}/src/simplhdl/resources/templates/vcs/__init__.py +0 -0
  162. {simplhdl-0.1.0 → simplhdl-0.1.2}/src/simplhdl/resources/templates/vcs/cocotb.mk.j2 +0 -0
  163. {simplhdl-0.1.0 → simplhdl-0.1.2}/src/simplhdl/resources/templates/vcs/dependencies.mk.j2 +0 -0
  164. {simplhdl-0.1.0 → simplhdl-0.1.2}/src/simplhdl/resources/templates/vcs/files.j2 +0 -0
  165. {simplhdl-0.1.0 → simplhdl-0.1.2}/src/simplhdl/resources/templates/vcs/fileset.j2 +0 -0
  166. {simplhdl-0.1.0 → simplhdl-0.1.2}/src/simplhdl/resources/templates/vcs/pli.tab.j2 +0 -0
  167. {simplhdl-0.1.0 → simplhdl-0.1.2}/src/simplhdl/resources/templates/vcs/project.mk.j2 +0 -0
  168. {simplhdl-0.1.0 → simplhdl-0.1.2}/src/simplhdl/resources/templates/vcs/synopsys_sim.setup.j2 +0 -0
  169. {simplhdl-0.1.0 → simplhdl-0.1.2}/src/simplhdl/resources/templates/vcs/vcs.parameters.j2 +0 -0
  170. {simplhdl-0.1.0 → simplhdl-0.1.2}/src/simplhdl/resources/templates/verible/__init__.py +0 -0
  171. {simplhdl-0.1.0 → simplhdl-0.1.2}/src/simplhdl/resources/templates/verible/rules.cfg.j2 +0 -0
  172. {simplhdl-0.1.0 → simplhdl-0.1.2}/src/simplhdl/resources/templates/vivado/__init__.py +0 -0
  173. {simplhdl-0.1.0 → simplhdl-0.1.2}/src/simplhdl/resources/templates/vivado/launch_run.sh.j2 +0 -0
  174. {simplhdl-0.1.0 → simplhdl-0.1.2}/src/simplhdl/resources/templates/vivado/run.tcl.j2 +0 -0
  175. {simplhdl-0.1.0 → simplhdl-0.1.2}/src/simplhdl/resources/templates/vivado/steps.tcl.j2 +0 -0
  176. {simplhdl-0.1.0 → simplhdl-0.1.2}/src/simplhdl/resources/templates/vsg/__init__.py +0 -0
  177. {simplhdl-0.1.0 → simplhdl-0.1.2}/src/simplhdl/resources/templates/vsg/files.json.j2 +0 -0
  178. {simplhdl-0.1.0 → simplhdl-0.1.2}/src/simplhdl/resources/templates/vsg/rules.yml.j2 +0 -0
  179. {simplhdl-0.1.0 → simplhdl-0.1.2}/src/simplhdl/resources/templates/xsim/Makefile.j2 +0 -0
  180. {simplhdl-0.1.0 → simplhdl-0.1.2}/src/simplhdl/resources/templates/xsim/__init__.py +0 -0
  181. {simplhdl-0.1.0 → simplhdl-0.1.2}/src/simplhdl/resources/templates/xsim/cocotb.mk.j2 +0 -0
  182. {simplhdl-0.1.0 → simplhdl-0.1.2}/src/simplhdl/resources/templates/xsim/dependencies.mk.j2 +0 -0
  183. {simplhdl-0.1.0 → simplhdl-0.1.2}/src/simplhdl/resources/templates/xsim/files.j2 +0 -0
  184. {simplhdl-0.1.0 → simplhdl-0.1.2}/src/simplhdl/resources/templates/xsim/fileset.j2 +0 -0
  185. {simplhdl-0.1.0 → simplhdl-0.1.2}/src/simplhdl/resources/templates/xsim/project.mk.j2 +0 -0
  186. {simplhdl-0.1.0 → simplhdl-0.1.2}/src/simplhdl/simplhdl.py +0 -0
  187. {simplhdl-0.1.0 → simplhdl-0.1.2}/src/simplhdl/tools.py +0 -0
  188. {simplhdl-0.1.0 → simplhdl-0.1.2}/src/simplhdl/utils.py +0 -0
  189. {simplhdl-0.1.0 → simplhdl-0.1.2}/tests/test_dummy.py +0 -0
  190. {simplhdl-0.1.0 → simplhdl-0.1.2}/tox.ini +0 -0
@@ -1,6 +1,6 @@
1
1
  Metadata-Version: 2.1
2
2
  Name: SimplHDL
3
- Version: 0.1.0
3
+ Version: 0.1.2
4
4
  Summary: A framework for simulating and implementing HDL designs
5
5
  Author-email: Rasmus Grøndahl Olsen <simplhdl@gmail.com>
6
6
  Maintainer-email: Rasmus Grøndahl Olsen <simplhdl@gmail.com>
@@ -1,6 +1,6 @@
1
1
  Metadata-Version: 2.1
2
2
  Name: SimplHDL
3
- Version: 0.1.0
3
+ Version: 0.1.2
4
4
  Summary: A framework for simulating and implementing HDL designs
5
5
  Author-email: Rasmus Grøndahl Olsen <simplhdl@gmail.com>
6
6
  Maintainer-email: Rasmus Grøndahl Olsen <simplhdl@gmail.com>
@@ -0,0 +1 @@
1
+ __version__ = "0.1.2"
@@ -34,7 +34,7 @@ class QuartusFlow(ImplementationFlow):
34
34
  '-s',
35
35
  '--step',
36
36
  action='store',
37
- choices=['synthesis', 'implement', 'finalize', 'compile'],
37
+ choices=['project', 'synthesis', 'implement', 'finalize', 'compile'],
38
38
  default='compile',
39
39
  help="flow step to run"
40
40
  )
@@ -45,8 +45,12 @@ class QuartusFlow(ImplementationFlow):
45
45
  )
46
46
  parser.add_argument(
47
47
  '--archive',
48
- choices=['project'],
49
- help="Archive Quartus project and results"
48
+ choices=[
49
+ 'project',
50
+ 'project-service-request',
51
+ 'project-source'
52
+ ],
53
+ help="Archive Quartus project, settings and results"
50
54
  )
51
55
 
52
56
  def __init__(self, name, args: Namespace, project: Project, builddir: Path):
@@ -64,7 +68,15 @@ class QuartusFlow(ImplementationFlow):
64
68
 
65
69
  def archive(self) -> None:
66
70
  name = self.project.Name
67
- command = f"quartus_sh --archive -use_file_set full_db -revision {name} -no_discover -output {name}.qar {name}"
71
+ if self.args.archive == 'project':
72
+ fileset = 'full_db'
73
+ elif self.args.archive == 'project-service-request':
74
+ fileset = 'sr'
75
+ elif self.args.archive == 'project-source':
76
+ fileset = 'basic'
77
+ else:
78
+ raise Exception("Unknown value for argument --archive: {self.args.archive}")
79
+ command = f"quartus_sh --archive -use_file_set {fileset} -revision {name} -no_discover -output {name}.qar {name}" # noqa
68
80
  sh(command.split(), output=True, cwd=self.builddir)
69
81
  raise SystemExit
70
82
 
@@ -14,7 +14,7 @@ from ..resources.templates import vivado as templates
14
14
  from ..utils import sh, generate_from_template, dict2str
15
15
  from ..pyedaa import (VivadoIPSpecificationFile, VerilogIncludeFile, VerilogSourceFile,
16
16
  SystemVerilogSourceFile, VHDLSourceFile, ConstraintFile,
17
- EDIFNetlistFile, NetlistFile)
17
+ EDIFNetlistFile, NetlistFile, VivadoBDTclFile, VivadoProjectStepFile)
18
18
  from ..pyedaa.project import Project
19
19
  from ..pyedaa.attributes import UsedIn
20
20
 
@@ -101,6 +101,8 @@ class VivadoFlow(FlowBase):
101
101
  VHDLSourceFile=VHDLSourceFile,
102
102
  ConstraintFile=ConstraintFile,
103
103
  VivadoIPSpecificationFile=VivadoIPSpecificationFile,
104
+ VivadoProjectStepFile=VivadoProjectStepFile,
105
+ VivadoBDTclFile=VivadoBDTclFile,
104
106
  EDIFNetlistFile=EDIFNetlistFile,
105
107
  NetlistFile=NetlistFile,
106
108
  project=self.project,
@@ -185,8 +185,9 @@ class VivadoIP(GeneratorBase):
185
185
  for fileset in filesets:
186
186
  corefiles += component.files(fileset)
187
187
  for file_element in corefiles:
188
- file = component.filepath(file_element)
189
- if file.exists() and file.suffix == '.xml':
188
+ # Get the .xml file next to the .xci file
189
+ file = component.filepath(file_element).with_suffix('.xml')
190
+ if file.exists():
190
191
  files += self.get_files(file)
191
192
  for view in component.views('.*simulation.*'):
192
193
  filesets = component.filesets(view)
@@ -123,7 +123,19 @@ class QuartusIP(GeneratorBase):
123
123
  md5file = dest.with_suffix('.md5')
124
124
  ipdir.mkdir(exist_ok=True)
125
125
  if filename.FileType == QuartusQSYSSpecificationFile:
126
- pass
126
+ update = True
127
+ dir = filename.Path.with_suffix('')
128
+ if dir.exists():
129
+ if md5file.exists():
130
+ update = not md5check(filename.Path, dir, filename=md5file)
131
+ if update:
132
+ copy(str(filename.Path), str(dest.with_suffix('.qsys')))
133
+ md5write(filename.Path, filename=md5file)
134
+ if dir.exists():
135
+ copytree(str(dir), str(dest.with_suffix('')), dirs_exist_ok=True)
136
+ md5write(filename.Path, dir, filename=md5file)
137
+ logger.debug(f"Copy {filename.Path} to {dest}")
138
+ filename._path = dest.with_suffix('.qsys').absolute()
127
139
 
128
140
  elif filename.FileType == QuartusIPCompressedSpecificationFile:
129
141
  update = True
@@ -158,6 +158,14 @@ class VivadoIPSpecificationFile(IPSpecificationFile):
158
158
  pass
159
159
 
160
160
 
161
+ class VivadoBDTclFile(TCLSourceFile):
162
+ pass
163
+
164
+
165
+ class VivadoProjectStepFile(TCLSourceFile):
166
+ pass
167
+
168
+
161
169
  class SystemRDLSourceFile(File):
162
170
  pass
163
171
 
@@ -6,6 +6,9 @@ set step [lindex $argv 0]
6
6
  project_open {{project.Name}}
7
7
 
8
8
  switch $step {
9
+ project {
10
+ puts "\nINFO: Project creation was successful.\n"
11
+ }
9
12
  compile {
10
13
  if {[catch {execute_flow -compile} result]} {
11
14
  puts "\nResult: $result\n"
@@ -99,10 +99,10 @@ add_files "{{file.Path|replace('\\', '/')}}"
99
99
  read_edif "{{file.Path|replace('\\', '/')}}"
100
100
  {% elif file.Path.suffix == '.bd' %}
101
101
  read_bd "{{file.Path|replace('\\', '/')}}"
102
- {% elif file.Path.name.endswith('.bd.tcl') %}
102
+ {% elif file.FileType == VivadoBDTclFile %}
103
103
  send_msg_id {SimplHDL PRJ-3} {INFO} "Sourcing BD tcl file {{file.Path|replace('\\', '/')}}: this might take some time."
104
104
  source_script "{{file.Path|replace('\\', '/')}}"
105
- {% elif file.Path.name.endswith('.steps.tcl') %}
105
+ {% elif file.FileType == VivadoProjectStepFile %}
106
106
  add_files -fileset utils_1 "{{file.Path|replace('\\', '/')}}"
107
107
  global step
108
108
  set step {project}
@@ -1 +0,0 @@
1
- __version__ = "0.1.0"
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