SimplHDL 0.0.7__tar.gz → 0.1.0__tar.gz

{simplhdl-0.0.7 → simplhdl-0.1.0}/PKG-INFO

@@ -1,6 +1,6 @@
 Metadata-Version: 2.1
 Name: SimplHDL
-Version: 0.0.7
+Version: 0.1.0
 Summary: A framework for simulating and implementing HDL designs
 Author-email: Rasmus Grøndahl Olsen <simplhdl@gmail.com>
 Maintainer-email: Rasmus Grøndahl Olsen <simplhdl@gmail.com>

{simplhdl-0.0.7 → simplhdl-0.1.0}/src/SimplHDL.egg-info/PKG-INFO

@@ -1,6 +1,6 @@
 Metadata-Version: 2.1
 Name: SimplHDL
-Version: 0.0.7
+Version: 0.1.0
 Summary: A framework for simulating and implementing HDL designs
 Author-email: Rasmus Grøndahl Olsen <simplhdl@gmail.com>
 Maintainer-email: Rasmus Grøndahl Olsen <simplhdl@gmail.com>

{simplhdl-0.0.7 → simplhdl-0.1.0}/src/SimplHDL.egg-info/SOURCES.txt

@@ -149,6 +149,7 @@ src/simplhdl/resources/templates/questasim/files.j2
 src/simplhdl/resources/templates/questasim/fileset.j2
 src/simplhdl/resources/templates/questasim/gui.do.j2
 src/simplhdl/resources/templates/questasim/project.mk.j2
+src/simplhdl/resources/templates/questasim/run.do.j2
 src/simplhdl/resources/templates/rivierapro/Makefile.j2
 src/simplhdl/resources/templates/rivierapro/__init__.py
 src/simplhdl/resources/templates/rivierapro/cocotb.mk.j2

simplhdl-0.1.0/src/simplhdl/__init__.py

@@ -0,0 +1 @@
+__version__ = "0.1.0"

{simplhdl-0.0.7 → simplhdl-0.1.0}/src/simplhdl/flows/questasim/questasimflow.py

@@ -31,10 +31,22 @@ class QuestaSimFlow(SimulationFlow):
         )
         parser.add_argument(
             '-w',
-            '--wave',
+            '--wavedump',
             action='store_true',
             help="Dump waveforms"
         )
+        parser.add_argument(
+            '--waveformat',
+            action='store',
+            choices=['wlf', 'vcd', 'evcd'],
+            default='wlf',
+            help="Wave file format"
+        )
+        parser.add_argument(
+            '--debug',
+            action='store_true',
+            help="Enable full debug capabilities"
+        )
         parser.add_argument(
             '--gui',
             action='store_true',
@@ -111,13 +123,16 @@ class QuestaSimFlow(SimulationFlow):
         globals['vcom_args'] = self.vcom_args()
         globals['vopt_args'] = self.vopt_args()
         globals['vsim_args'] = self.vsim_args()
+        globals['wavedump'] = self.args.wavedump
+        globals['waveformat'] = self.args.waveformat
         return globals
 
     def get_project_templates(self, environment) -> List[Template]:
         return [
             environment.get_template('Makefile.j2'),
             environment.get_template('project.mk.j2'),
-            environment.get_template('gui.do.j2')
+            environment.get_template('gui.do.j2'),
+            environment.get_template('run.do.j2')
         ]
 
     def get_cocotb_templates(self, environment):
@@ -144,6 +159,8 @@ class QuestaSimFlow(SimulationFlow):
         args = set()
         if self.args.verbose == 0:
             args.add('-quiet')
+        for name in self.get_libraries().keys():
+            args.add(f"-L {name}")
         for name, value in self.project.Defines.items():
             args.add(f"+define+{name}={escape(value)}")
         return ' '.join(list(args) + [self.args.vlog_args])
@@ -170,7 +187,11 @@ class QuestaSimFlow(SimulationFlow):
             args.add(f"-g{name}={escape(value)}")
         for name, value in self.project.Parameters.items():
             args.add(f"-g{name}={escape(value)}")
-        if self.args.gui or self.args.do or self.args.wave or self.cocotb.enabled:
+        if self.args.debug:
+            args.add('+acc')
+            args.add('-debugdb')
+            args.add('-fsmdebug')
+        elif self.args.gui or self.args.do or self.args.wavedump or self.cocotb.enabled:
             args.add('+acc=npr')
         return ' '.join(list(args) + [self.args.vopt_args])
 
@@ -188,6 +209,8 @@ class QuestaSimFlow(SimulationFlow):
             args.add('-onfinish final')
         else:
             args.add('-onfinish exit')
+        if self.args.debug:
+            args.add('-debugDB')
 
         return ' '.join(list(args) + [self.args.vsim_args])
 

{simplhdl-0.0.7 → simplhdl-0.1.0}/src/simplhdl/flows/simulationflow.py

@@ -4,6 +4,7 @@ except ImportError:
     from importlib_resources import files as resources_files
 import os
 import logging
+import shutil
 
 from typing import Callable, Generator, List, Dict, Tuple, Any
 from jinja2 import Environment, FileSystemLoader
@@ -15,8 +16,10 @@ from simplhdl.pyedaa.project import Project
 from simplhdl.pyedaa.attributes import UsedIn
 from simplhdl.cocotb import Cocotb
 from simplhdl.pyedaa.fileset import FileSet
-from simplhdl.pyedaa import (File, VerilogSourceFile, VerilogIncludeFile,
-                             SystemVerilogSourceFile, VHDLSourceFile)
+from simplhdl.pyedaa import (
+    File, VerilogSourceFile, VerilogIncludeFile, SystemVerilogSourceFile, VHDLSourceFile,
+    MemoryInitFile
+)
 from simplhdl.utils import generate_from_template, md5sum, md5check, md5write, append_suffix
 
 logger = logging.getLogger(__name__)
@@ -75,6 +78,7 @@ class SimulationFlow(FlowBase):
         for template in self.get_project_templates(env) + self.get_cocotb_templates(env):
             generate_from_template(template, self.builddir, self.get_globals())
         self.generate_make_rules(env)
+        self.copy_memory_files()
         self.is_filesets_changed()
 
     def generate_make_rules(self, environment):
@@ -138,6 +142,10 @@ class SimulationFlow(FlowBase):
             generated.append(output)
         return generated
 
+    def copy_memory_files(self):
+        for file in self.project.DefaultDesign.Files(MemoryInitFile):
+            shutil.copy(file.Path.absolute(), self.builddir.absolute())
+
     def is_uvm(self):
         for plusarg in self.project.PlusArgs.keys():
             if plusarg.startswith('UVM_'):

{simplhdl-0.0.7 → simplhdl-0.1.0}/src/simplhdl/flows/vsg/vsgflow.py

@@ -102,14 +102,13 @@ class VsgFlow(FlowBase):
         if user_files:
             if self.rules:
                 command += f"-c {self.rules}".split()
-            command += ['-f'] + self.args.files
+            command += ['-f'] + [str(f.absolute()) for f in self.args.files]
         elif project_files:
             command += f"-c {self.rules} files.json".split()
         else:
             raise FlowError("No VHDL files")
 
         try:
-            logger.debug(command)
             sh(command, cwd=self.builddir, output=True)
         except CalledShError as e:
             print(e)

{simplhdl-0.0.7 → simplhdl-0.1.0}/src/simplhdl/generators/spd.py

@@ -11,12 +11,13 @@ from shutil import copy, copytree
 from ..pyedaa import (
     File, SystemVerilogSourceFile, VHDLSourceFile, VerilogSourceFile,
     QuartusIPSpecificationFile, HDLLibrary, ConstraintFile, HDLSourceFile,
-    QuartusIPCompressedSpecificationFile, QuartusQSYSSpecificationFile
+    QuartusIPCompressedSpecificationFile, QuartusQSYSSpecificationFile,
+    MemoryInitFile
 )
 from ..pyedaa.fileset import FileSet
 from ..flow import FlowBase, FlowCategory, FlowTools
 from ..generator import GeneratorFactory, GeneratorBase, GeneratorError
-from ..utils import md5write, md5check
+from ..utils import md5write, md5check, sh
 
 logger = logging.getLogger(__name__)
 
@@ -29,6 +30,7 @@ FILETYPE_MAP = {
     'VHDL': VHDLSourceFile,
     'VHDL_ENCRYPT': VHDLSourceFile,
     'SDC_ENTITY': ConstraintFile,
+    'HEX': MemoryInitFile
 }
 
 TOOL_MAP = {
@@ -51,7 +53,10 @@ class Spd:
         self.simulators = set()
         spdfile = filename.parent.joinpath(filename.stem, filename.name).with_suffix('.spd')
         if not spdfile.exists():
-            raise FileNotFoundError(f"{spdfile}: doesn't exits")
+            command = f"qsys-generate --simulation=VERILOG {filename.absolute()}".split()
+            sh(command, cwd=filename.parent)
+            if not spdfile.exists():
+                raise FileNotFoundError(f"{spdfile}: doesn't exits")
         self.tree = parse(spdfile)
         self.root = self.tree.getroot()
         self.location = spdfile.parent.absolute()

{simplhdl-0.0.7 → simplhdl-0.1.0}/src/simplhdl/pyedaa/__init__.py

@@ -168,3 +168,9 @@ class ScalaBuildFile(File):
 
 class ChiselBuildFile(ScalaBuildFile):
     pass
+
+
+class MemoryInitFile(File):
+    def _registerAttributes(self):
+        super()._registerAttributes()
+        FileMixIn._registerAttributes(self)

{simplhdl-0.0.7 → simplhdl-0.1.0}/src/simplhdl/resources/templates/quartus/project.tcl.j2

@@ -15,11 +15,11 @@ set_global_assignment -name VERILOG_MACRO "{{define}}={{value}}"
 {% if file.FileType == VerilogIncludeFile %}
 set_global_assignment -name VERILOG_INCLUDE_FILE "{{file.Path}}"
 {% elif file.FileType == SystemVerilogSourceFile %}
-set_global_assignment -name SYSTEMVERILOG_FILE "{{file.Path}}"
+set_global_assignment -library {{file.Library}} -name SYSTEMVERILOG_FILE "{{file.Path}}"
 {% elif file.FileType == VerilogSourceFile %}
-set_global_assignment -name VERILOG_FILE "{{file.Path}}"
+set_global_assignment -library {{file.Library}} -name VERILOG_FILE "{{file.Path}}"
 {% elif file.FileType == VHDLSourceFile %}
-set_global_assignment -name VHDL_FILE "{{file.Path}}"
+set_global_assignment -library {{file.Library}} -name VHDL_FILE "{{file.Path}}"
 {% elif file.FileType == ConstraintFile %}
 set_global_assignment -name SDC_FILE "{{file.Path}}"
 {% elif file.FileType == TCLSourceFile %}

{simplhdl-0.0.7 → simplhdl-0.1.0}/src/simplhdl/resources/templates/questasim/Makefile.j2

@@ -23,7 +23,7 @@ export VSIM_COMMAND := $(VSIM) $(VSIM_FLAGS) $(VOPT_DESIGN)
 .PHONY: clean compile simulate gui
 
 ifeq ($(DO_CMD),)
-DO_CMD := -do "run -all; quit"
+DO_CMD := -do run.do
 else
 GUI_DO_CMD := $(DO_CMD)
 endif

{simplhdl-0.0.7/src/simplhdl/resources/templates/rivierapro → simplhdl-0.1.0/src/simplhdl/resources/templates/questasim}/project.mk.j2

@@ -5,10 +5,12 @@ VERILOG_FILESETS := $(addsuffix .com,$(wildcard *verilog.fileset))
 
 {% set libpaths = [] %}
 {% for library in libraries %}
-{{ libpaths.append(library.Path) or '' }}
-{{library.Path}}:
+{% set libpath = library.Path or library.Name %}
+{{ libpaths.append(libpath) or ''}}
+
+{{libpath}}:
 	$(VLIB) {{library.Name}}
-	$(VMAP) {{library.Name}} {{library.Path}}
+	$(VMAP) {{library.Name}} {{libpath}}
 
 {% endfor %}
 

simplhdl-0.1.0/src/simplhdl/resources/templates/questasim/run.do.j2

@@ -0,0 +1,14 @@
+{% if wavedump %}
+{% if waveformat == 'vcd' %}
+vcd file vsim.vcd
+vcd add -r /*
+{% elif waveformat == 'evcd' %}
+vcd file vsim.evcd
+vcd add -dumpports -r /*
+{% elif waveformat == 'wlf' %}
+log -r /*
+{% endif %}
+{% endif %}
+
+run -all
+quit

simplhdl-0.0.7/src/simplhdl/__init__.py

@@ -1 +0,0 @@
-__version__ = "0.0.7"