SimplHDL 0.0.6__tar.gz → 0.1.0__tar.gz

{simplhdl-0.0.6 → simplhdl-0.1.0}/PKG-INFO

@@ -1,6 +1,6 @@
 Metadata-Version: 2.1
 Name: SimplHDL
-Version: 0.0.6
+Version: 0.1.0
 Summary: A framework for simulating and implementing HDL designs
 Author-email: Rasmus Grøndahl Olsen <simplhdl@gmail.com>
 Maintainer-email: Rasmus Grøndahl Olsen <simplhdl@gmail.com>
@@ -53,6 +53,8 @@ Requires-Dist: jinja2
 Requires-Dist: GitPython
 Requires-Dist: rich
 Requires-Dist: vsg
+Requires-Dist: flake8
+Requires-Dist: black
 
 ## Introduction
 

{simplhdl-0.0.6 → simplhdl-0.1.0}/pyproject.toml

@@ -22,6 +22,8 @@ dependencies = [
     "GitPython",
     "rich",
     "vsg",
+    "flake8",
+    "black",
 ]
 requires-python = ">=3.8"
 authors = [

{simplhdl-0.0.6 → simplhdl-0.1.0}/src/SimplHDL.egg-info/PKG-INFO

@@ -1,6 +1,6 @@
 Metadata-Version: 2.1
 Name: SimplHDL
-Version: 0.0.6
+Version: 0.1.0
 Summary: A framework for simulating and implementing HDL designs
 Author-email: Rasmus Grøndahl Olsen <simplhdl@gmail.com>
 Maintainer-email: Rasmus Grøndahl Olsen <simplhdl@gmail.com>
@@ -53,6 +53,8 @@ Requires-Dist: jinja2
 Requires-Dist: GitPython
 Requires-Dist: rich
 Requires-Dist: vsg
+Requires-Dist: flake8
+Requires-Dist: black
 
 ## Introduction
 

{simplhdl-0.0.6 → simplhdl-0.1.0}/src/SimplHDL.egg-info/SOURCES.txt

@@ -103,6 +103,8 @@ src/simplhdl/flows/modelsimflow.py
 src/simplhdl/flows/quartusflow.py
 src/simplhdl/flows/simulationflow.py
 src/simplhdl/flows/vivadoflow.py
+src/simplhdl/flows/flake8/flake8flow.py
+src/simplhdl/flows/lint/lintflow.py
 src/simplhdl/flows/quartusdse/__init__.py
 src/simplhdl/flows/quartusdse/quartusdseflow.py
 src/simplhdl/flows/questasim/__init__.py
@@ -134,6 +136,8 @@ src/simplhdl/pyedaa/project.py
 src/simplhdl/pyedaa/vhdllibrary.py
 src/simplhdl/resources/__init__.py
 src/simplhdl/resources/templates/__init__.py
+src/simplhdl/resources/templates/flake8/__init__.py
+src/simplhdl/resources/templates/flake8/setup.cfg.j2
 src/simplhdl/resources/templates/quartus/__init__.py
 src/simplhdl/resources/templates/quartus/project.tcl.j2
 src/simplhdl/resources/templates/quartus/run.tcl.j2
@@ -145,6 +149,7 @@ src/simplhdl/resources/templates/questasim/files.j2
 src/simplhdl/resources/templates/questasim/fileset.j2
 src/simplhdl/resources/templates/questasim/gui.do.j2
 src/simplhdl/resources/templates/questasim/project.mk.j2
+src/simplhdl/resources/templates/questasim/run.do.j2
 src/simplhdl/resources/templates/rivierapro/Makefile.j2
 src/simplhdl/resources/templates/rivierapro/__init__.py
 src/simplhdl/resources/templates/rivierapro/cocotb.mk.j2

{simplhdl-0.0.6 → simplhdl-0.1.0}/src/SimplHDL.egg-info/requires.txt

@@ -7,6 +7,8 @@ jinja2
 GitPython
 rich
 vsg
+flake8
+black
 
 [:python_version < "3.9"]
 importlib-resources

simplhdl-0.1.0/src/simplhdl/__init__.py

@@ -0,0 +1 @@
+__version__ = "0.1.0"

{simplhdl-0.0.6 → simplhdl-0.1.0}/src/simplhdl/cocotb.py

@@ -85,7 +85,6 @@ class Cocotb:
                         lines = f.readlines()
                         for line in lines:
                             if re.search(rf'^\s*module\s+{name}(\s+|\(|;|$)', line):
-                                print(file.Path)
                                 if file.Library.Name == lib:
                                     logger.info(f"Cocotb dut '{self.dut}' is Verilog")
                                     return VerilogSourceFile

simplhdl-0.1.0/src/simplhdl/flows/flake8/flake8flow.py

@@ -0,0 +1,83 @@
+try:
+    from importlib.resources import files as resources_files
+except ImportError:
+    from importlib_resources import files as resources_files
+import os
+import shutil
+import logging
+from argparse import Namespace
+from pathlib import Path
+from jinja2 import Environment, FileSystemLoader
+
+from simplhdl.resources.templates import flake8 as templates
+from simplhdl.utils import sh, CalledShError, generate_from_template
+from simplhdl.flow import FlowFactory, FlowBase
+from simplhdl.pyedaa.project import Project
+from simplhdl.pyedaa import PythonSourceFile
+
+logger = logging.getLogger(__name__)
+
+
+@FlowFactory.register('flake8')
+class Flake8Flow(FlowBase):
+
+    @classmethod
+    def parse_args(self, subparsers) -> None:
+        parser = subparsers.add_parser('flake8', help='Lint Flow for Python code')
+        parser.add_argument(
+            '--fix',
+            action='store_true',
+            help="Fix style formatting (Note: this modifies the source)"
+        )
+        parser.add_argument(
+            '-f', '--files',
+            type=lambda p: Path(p).absolute(),
+            nargs='+',
+            default=[],
+            help="Manually specify file list"
+        )
+
+    def __init__(self, name, args: Namespace, project: Project, builddir: Path):
+        super().__init__(name, args, project, builddir)
+        self.templates = templates
+
+    def setup(self):
+        os.makedirs(self.builddir, exist_ok=True)
+        if self.args.files:
+            self.files = [Path(f) for f in self.args.files if Path(f).suffix == '.py']
+        else:
+            self.files = [f.Path for f in self.project.DefaultDesign.DefaultFileSet.Files(PythonSourceFile)]
+
+    def generate(self):
+        config = os.getenv('SIMPLHDL_FLAKE8_RULES')
+        if config:
+            shutil.copy(config, self.builddir.joinpath('setup.cfg'))
+        else:
+            templatedir = resources_files(self.templates)
+            environment = Environment(
+                loader=FileSystemLoader(templatedir),
+                trim_blocks=True)
+            template = environment.get_template('setup.cfg.j2')
+            generate_from_template(template, self.builddir)
+
+    def execute(self):
+        if self.args.fix:
+            for file in self.files:
+                sh(['black', str(file.absolute())])
+        else:
+            command = ['flake8'] + [str(f.absolute()) for f in self.files]
+            try:
+                sh(command, cwd=self.builddir, output=True)
+            except CalledShError as e:
+                print(e)
+                raise SystemError
+
+            # flake = flake8.get_style_guide()
+            # report = flake.check_files(self.files)
+            # if report.get_statistics('E'):
+            #     raise SystemError
+
+    def run(self) -> None:
+        self.setup()
+        self.generate()
+        self.execute()

simplhdl-0.1.0/src/simplhdl/flows/lint/lintflow.py

@@ -0,0 +1,72 @@
+import os
+import logging
+from argparse import Namespace
+from pathlib import Path
+
+from simplhdl.flow import FlowFactory, FlowBase
+from simplhdl.pyedaa.project import Project
+from simplhdl.flows.verible.veribleflow import VeribleFlow
+from simplhdl.flows.vsg.vsgflow import VsgFlow
+from simplhdl.flows.flake8.flake8flow import Flake8Flow
+
+logger = logging.getLogger(__name__)
+
+
+@FlowFactory.register('lint')
+class LintFlow(FlowBase):
+
+    @classmethod
+    def parse_args(self, subparsers) -> None:
+        parser = subparsers.add_parser('lint', help='Lint Flow for Design and Verification code')
+        parser.add_argument(
+            '--fix',
+            action='store_true',
+            help="Fix style formatting (Note: this modifies the source)"
+        )
+        parser.add_argument(
+            '-f', '--files',
+            type=lambda p: Path(p).absolute(),
+            nargs='+',
+            default=[],
+            help="Manually specify file list"
+        )
+
+    def __init__(self, name, args: Namespace, project: Project, builddir: Path):
+        super().__init__(name, args, project, builddir)
+
+    def setup(self):
+        os.makedirs(self.builddir, exist_ok=True)
+
+    def generate(self):
+        pass
+
+    def execute(self):
+        verible_args = Namespace(rules=None, files=self.args.files, fix=self.args.fix)
+        verible = VeribleFlow('verible', verible_args, self.project, self.builddir)
+        vsg_args = Namespace(rules=None, files=self.args.files, fix=self.args.fix, output_format='syntastic')
+        vsg = VsgFlow('vsg', vsg_args, self.project, self.builddir)
+        flake_args = Namespace(files=self.args.files, fix=self.args.fix)
+        flake = Flake8Flow('flake8', flake_args, self.project, self.builddir)
+        system_error = False
+        try:
+            verible.run()
+        except SystemError:
+            system_error = True
+
+        try:
+            vsg.run()
+        except SystemError:
+            system_error = True
+
+        try:
+            flake.run()
+        except SystemError:
+            system_error = True
+
+        if system_error:
+            raise SystemError
+
+    def run(self) -> None:
+        self.setup()
+        self.generate()
+        self.execute()

{simplhdl-0.0.6 → simplhdl-0.1.0}/src/simplhdl/flows/questasim/questasimflow.py

@@ -31,10 +31,22 @@ class QuestaSimFlow(SimulationFlow):
         )
         parser.add_argument(
             '-w',
-            '--wave',
+            '--wavedump',
             action='store_true',
             help="Dump waveforms"
         )
+        parser.add_argument(
+            '--waveformat',
+            action='store',
+            choices=['wlf', 'vcd', 'evcd'],
+            default='wlf',
+            help="Wave file format"
+        )
+        parser.add_argument(
+            '--debug',
+            action='store_true',
+            help="Enable full debug capabilities"
+        )
         parser.add_argument(
             '--gui',
             action='store_true',
@@ -111,13 +123,16 @@ class QuestaSimFlow(SimulationFlow):
         globals['vcom_args'] = self.vcom_args()
         globals['vopt_args'] = self.vopt_args()
         globals['vsim_args'] = self.vsim_args()
+        globals['wavedump'] = self.args.wavedump
+        globals['waveformat'] = self.args.waveformat
         return globals
 
     def get_project_templates(self, environment) -> List[Template]:
         return [
             environment.get_template('Makefile.j2'),
             environment.get_template('project.mk.j2'),
-            environment.get_template('gui.do.j2')
+            environment.get_template('gui.do.j2'),
+            environment.get_template('run.do.j2')
         ]
 
     def get_cocotb_templates(self, environment):
@@ -144,6 +159,8 @@ class QuestaSimFlow(SimulationFlow):
         args = set()
         if self.args.verbose == 0:
             args.add('-quiet')
+        for name in self.get_libraries().keys():
+            args.add(f"-L {name}")
         for name, value in self.project.Defines.items():
             args.add(f"+define+{name}={escape(value)}")
         return ' '.join(list(args) + [self.args.vlog_args])
@@ -170,7 +187,11 @@ class QuestaSimFlow(SimulationFlow):
             args.add(f"-g{name}={escape(value)}")
         for name, value in self.project.Parameters.items():
             args.add(f"-g{name}={escape(value)}")
-        if self.args.gui or self.args.do or self.args.wave or self.cocotb.enabled:
+        if self.args.debug:
+            args.add('+acc')
+            args.add('-debugdb')
+            args.add('-fsmdebug')
+        elif self.args.gui or self.args.do or self.args.wavedump or self.cocotb.enabled:
             args.add('+acc=npr')
         return ' '.join(list(args) + [self.args.vopt_args])
 
@@ -188,6 +209,8 @@ class QuestaSimFlow(SimulationFlow):
             args.add('-onfinish final')
         else:
             args.add('-onfinish exit')
+        if self.args.debug:
+            args.add('-debugDB')
 
         return ' '.join(list(args) + [self.args.vsim_args])
 

{simplhdl-0.0.6 → simplhdl-0.1.0}/src/simplhdl/flows/simulationflow.py

@@ -4,6 +4,7 @@ except ImportError:
     from importlib_resources import files as resources_files
 import os
 import logging
+import shutil
 
 from typing import Callable, Generator, List, Dict, Tuple, Any
 from jinja2 import Environment, FileSystemLoader
@@ -15,9 +16,11 @@ from simplhdl.pyedaa.project import Project
 from simplhdl.pyedaa.attributes import UsedIn
 from simplhdl.cocotb import Cocotb
 from simplhdl.pyedaa.fileset import FileSet
-from simplhdl.pyedaa import (File, VerilogSourceFile, VerilogIncludeFile,
-                             SystemVerilogSourceFile, VHDLSourceFile)
-from simplhdl.utils import generate_from_template, md5sum, append_suffix
+from simplhdl.pyedaa import (
+    File, VerilogSourceFile, VerilogIncludeFile, SystemVerilogSourceFile, VHDLSourceFile,
+    MemoryInitFile
+)
+from simplhdl.utils import generate_from_template, md5sum, md5check, md5write, append_suffix
 
 logger = logging.getLogger(__name__)
 
@@ -28,10 +31,11 @@ class SimulationFlow(FlowBase):
         super().__init__(name, args, project, builddir)
         self.category = FlowCategory.SIMULATION
         self.hdl_language = None
-        self.cocotb = Cocotb(project)
         self.templates = None
+        self.hashfile = self.builddir.joinpath('filesets.hash')
 
     def run(self) -> None:
+        self.cocotb = Cocotb(self.project)
         self.validate()
         self.configure()
         self.generate()
@@ -74,6 +78,8 @@ class SimulationFlow(FlowBase):
         for template in self.get_project_templates(env) + self.get_cocotb_templates(env):
             generate_from_template(template, self.builddir, self.get_globals())
         self.generate_make_rules(env)
+        self.copy_memory_files()
+        self.is_filesets_changed()
 
     def generate_make_rules(self, environment):
         walker = FileSetWalker()
@@ -126,7 +132,8 @@ class SimulationFlow(FlowBase):
                 template,
                 base.with_suffix('.files'),
                 target=base.with_suffix('.fileset').name,
-                files=[f.Path.absolute() for f in files])
+                files=[f.Path.absolute() for f in files],
+                hashfile=self.hashfile.name)
             template = environment.get_template('fileset.j2')
             output = base.with_suffix('.fileset')
             includes = {f.Path.parent.absolute() for f in files if isinstance(f, VerilogIncludeFile)}
@@ -135,6 +142,10 @@ class SimulationFlow(FlowBase):
             generated.append(output)
         return generated
 
+    def copy_memory_files(self):
+        for file in self.project.DefaultDesign.Files(MemoryInitFile):
+            shutil.copy(file.Path.absolute(), self.builddir.absolute())
+
     def is_uvm(self):
         for plusarg in self.project.PlusArgs.keys():
             if plusarg.startswith('UVM_'):
@@ -159,6 +170,20 @@ class SimulationFlow(FlowBase):
         libraries.update(self.project.DefaultDesign.ExternalVHDLLibraries)
         return libraries
 
+    def is_filesets_changed(self) -> bool:
+        """
+        Check if there are any changes in filesets since last run.
+        """
+        filesets = []
+        walker = FileSetWalker()
+        for fileset in walker.walk(self.project.DefaultDesign.DefaultFileSet):
+            filesets += [Path(f.Name) for f in FileSetWalker().walk(fileset) if Path(f.Name).is_file()]
+        if self.hashfile.is_file() and md5check(*filesets, filename=self.hashfile):
+            return True
+        else:
+            md5write(*filesets, filename=self.hashfile)
+            return False
+
 
 class FileSetWalker:
 

{simplhdl-0.0.6 → simplhdl-0.1.0}/src/simplhdl/flows/verible/veribleflow.py

@@ -23,11 +23,11 @@ class VeribleFlow(FlowBase):
     @classmethod
     def parse_args(self, subparsers) -> None:
         parser = subparsers.add_parser('verible-verilog-lint', help='Verible Lint Flow')
-        # parser.add_argument(
-        #     '--fix',
-        #     action='store_true',
-        #     help="Fix style formatting (Note: this modifies the source)"
-        # )
+        parser.add_argument(
+            '--fix',
+            action='store_true',
+            help="Fix style formatting (Note: this modifies the source)"
+        )
         parser.add_argument(
             '-r', '--rules',
             action='store',
@@ -49,29 +49,30 @@ class VeribleFlow(FlowBase):
         os.makedirs(self.builddir, exist_ok=True)
 
     def generate(self):
-        templatedir = resources_files(self.templates)
-        environment = Environment(
-            loader=FileSystemLoader(templatedir),
-            trim_blocks=True)
-        template = environment.get_template('rules.cfg.j2')
-        generate_from_template(template, self.builddir)
-
-    def execute(self):
-        errors = False
-        command = ["verible-verilog-lint"]
         if self.args.rules:
-            rules = self.args.rules
+            self.rules = self.args.rules
         elif os.getenv('SIMPLHDL_VERIBLE_RULES'):
-            rules = self.args.rules
+            self.rules = self.args.rules
         else:
-            rules = 'rules.cfg'
+            templatedir = resources_files(self.templates)
+            environment = Environment(
+                loader=FileSystemLoader(templatedir),
+                trim_blocks=True)
+            template = environment.get_template('rules.cfg.j2')
+            generate_from_template(template, self.builddir)
+            self.rules = 'rules.cfg'
 
-        command += f"--check_syntax=false --rules_config {rules}".split()
+    def execute(self):
+        errors = False
+        command = [
+            "verible-verilog-lint",
+            "--check_syntax=false",
+            "--ruleset=all",
+            "--rules_config", self.rules
+        ]
 
-        # if self.args.fix:
-        #     command.append("--fix")
-        # else:
-        #     command += f"-ap -of {self.args.output_format}".split()
+        if self.args.fix:
+            command += ["--autofix=inplace"]
 
         file_types = [VerilogIncludeFile, VerilogSourceFile, SystemVerilogSourceFile]
         files = [f for f in self.project.DefaultDesign.Files() if f.FileType in file_types]

{simplhdl-0.0.6 → simplhdl-0.1.0}/src/simplhdl/flows/vsg/vsgflow.py

@@ -8,13 +8,14 @@ from argparse import Namespace
 from pathlib import Path
 from jinja2 import Environment, FileSystemLoader
 
-from simplhdl.flow import FlowFactory, FlowBase
+from simplhdl.flow import FlowFactory, FlowBase, FlowError
 from simplhdl.resources.templates import vsg as templates
 from simplhdl.utils import sh, CalledShError, generate_from_template
 from simplhdl.pyedaa import VHDLSourceFile
 from simplhdl.pyedaa.project import Project
 from simplhdl.pyedaa.attributes import UsedIn
 
+
 logger = logging.getLogger(__name__)
 
 
@@ -31,7 +32,7 @@ class VsgFlow(FlowBase):
                 'syntastic',
                 'summary'
             ],
-            default='vsg',
+            default=None,
             help="Display output format"
         )
         parser.add_argument(
@@ -55,6 +56,8 @@ class VsgFlow(FlowBase):
     def __init__(self, name, args: Namespace, project: Project, builddir: Path):
         super().__init__(name, args, project, builddir)
         self.templates = templates
+        # file limit to change output for to summary
+        self.file_limit: int = 5
 
     def setup(self):
         os.makedirs(self.builddir, exist_ok=True)
@@ -69,32 +72,43 @@ class VsgFlow(FlowBase):
                                VHDLSourceFile=VHDLSourceFile,
                                project=self.project,
                                UsedIn=UsedIn)
-        template = environment.get_template('rules.yml.j2')
-        generate_from_template(template, self.builddir)
-
-    def execute(self):
-        command = ["vsg"]
         if self.args.rules:
-            rules = self.args.rules
+            self.rules = self.args.rules
         elif os.getenv('SIMPLHDL_VSG_RULES'):
-            rules = self.args.rules
+            self.rules = self.args.rules
         else:
-            rules = 'rules.yml'
+            template = environment.get_template('rules.yml.j2')
+            generate_from_template(template, self.builddir)
+            self.rules = 'rules.yml'
+
+    def execute(self):
+        command = ["vsg"]
+        user_files = len(self.args.files)
+        project_files = len(list(self.project.DefaultDesign.DefaultFileSet.Files(VHDLSourceFile)))
 
         if self.args.fix:
             command.append("--fix")
+        elif self.args.output_format is None:
+            if user_files > self.file_limit:
+                format = "summary"
+            elif project_files > self.file_limit and not user_files:
+                format = "summary"
+            else:
+                format = "vsg"
+            command += f"-ap -of {format}".split()
         else:
             command += f"-ap -of {self.args.output_format}".split()
 
-        if self.args.files:
-            if rules:
-                command += f"-c {rules}".split()
-            command += ['-f'] + self.args.files
+        if user_files:
+            if self.rules:
+                command += f"-c {self.rules}".split()
+            command += ['-f'] + [str(f.absolute()) for f in self.args.files]
+        elif project_files:
+            command += f"-c {self.rules} files.json".split()
         else:
-            command += f"-c {rules} files.json".split()
+            raise FlowError("No VHDL files")
 
         try:
-            logger.debug(command)
             sh(command, cwd=self.builddir, output=True)
         except CalledShError as e:
             print(e)

{simplhdl-0.0.6 → simplhdl-0.1.0}/src/simplhdl/generators/spd.py

@@ -11,12 +11,13 @@ from shutil import copy, copytree
 from ..pyedaa import (
     File, SystemVerilogSourceFile, VHDLSourceFile, VerilogSourceFile,
     QuartusIPSpecificationFile, HDLLibrary, ConstraintFile, HDLSourceFile,
-    QuartusIPCompressedSpecificationFile, QuartusQSYSSpecificationFile
+    QuartusIPCompressedSpecificationFile, QuartusQSYSSpecificationFile,
+    MemoryInitFile
 )
 from ..pyedaa.fileset import FileSet
 from ..flow import FlowBase, FlowCategory, FlowTools
 from ..generator import GeneratorFactory, GeneratorBase, GeneratorError
-from ..utils import md5write, md5check
+from ..utils import md5write, md5check, sh
 
 logger = logging.getLogger(__name__)
 
@@ -29,6 +30,7 @@ FILETYPE_MAP = {
     'VHDL': VHDLSourceFile,
     'VHDL_ENCRYPT': VHDLSourceFile,
     'SDC_ENTITY': ConstraintFile,
+    'HEX': MemoryInitFile
 }
 
 TOOL_MAP = {
@@ -51,7 +53,10 @@ class Spd:
         self.simulators = set()
         spdfile = filename.parent.joinpath(filename.stem, filename.name).with_suffix('.spd')
         if not spdfile.exists():
-            raise FileNotFoundError(f"{spdfile}: doesn't exits")
+            command = f"qsys-generate --simulation=VERILOG {filename.absolute()}".split()
+            sh(command, cwd=filename.parent)
+            if not spdfile.exists():
+                raise FileNotFoundError(f"{spdfile}: doesn't exits")
         self.tree = parse(spdfile)
         self.root = self.tree.getroot()
         self.location = spdfile.parent.absolute()

{simplhdl-0.0.6 → simplhdl-0.1.0}/src/simplhdl/parser.py

@@ -1,3 +1,5 @@
+import logging
+
 from pathlib import Path
 from typing import Callable
 from abc import ABCMeta, abstractmethod
@@ -6,6 +8,8 @@ from argparse import Namespace
 from .pyedaa.fileset import FileSet
 from .pyedaa.project import Project
 
+logger = logging.getLogger(__name__)
+
 
 class ParserBase(metaclass=ABCMeta):
 
@@ -21,6 +25,17 @@ class ParserBase(metaclass=ABCMeta):
         pass
 
 
+class NoParser(ParserBase):
+    """
+    This parser always returns an empty fileset
+    """
+    def is_valid_format(self, filename: Path) -> bool:
+        return True
+
+    def parse(self, filename: Path, project: Project, args: Namespace) -> 'FileSet':
+        return FileSet('Empty')
+
+
 class ParserFactory:
     """
     Factory for creating parsers
@@ -47,7 +62,8 @@ class ParserFactory:
             if parser.is_valid_format(filename):
                 return parser
         if filename is None:
-            raise ParserError("Couldn't find Parser for parsing, try using the --projectspec <filename>")
+            logger.info("No project specification found, continue with empty project")
+            return NoParser()
         else:
             raise ParserError(f"Couldn't find Parser for parsing '{filename}'")
 

{simplhdl-0.0.6 → simplhdl-0.1.0}/src/simplhdl/plugins.py

@@ -30,6 +30,8 @@ def load_builtin_plugins() -> None:
     import_module('simplhdl.flows.quartusdse.quartusdseflow')
     import_module('simplhdl.flows.vsg.vsgflow')
     import_module('simplhdl.flows.verible.veribleflow')
+    import_module('simplhdl.flows.lint.lintflow')
+    import_module('simplhdl.flows.flake8.flake8flow')
     packages = chain(
         iter_namespace(simplhdl.parsers),
         iter_namespace(simplhdl.flows),

{simplhdl-0.0.6 → simplhdl-0.1.0}/src/simplhdl/pyedaa/__init__.py

@@ -73,7 +73,11 @@ class VHDLSourceFile(HDLSourceFile, pm.HumanReadableContent):
     pass
 
 
-class CocotbPythonFile(pm.CocotbPythonFile, FileMixIn):
+class PythonSourceFile(pm.PythonSourceFile):
+    pass
+
+
+class CocotbPythonFile(PythonSourceFile, FileMixIn):
     def _registerAttributes(self):
         super()._registerAttributes()
         FileMixIn._registerAttributes(self)
@@ -164,3 +168,9 @@ class ScalaBuildFile(File):
 
 class ChiselBuildFile(ScalaBuildFile):
     pass
+
+
+class MemoryInitFile(File):
+    def _registerAttributes(self):
+        super()._registerAttributes()
+        FileMixIn._registerAttributes(self)