SimplHDL 0.0.6__tar.gz → 0.0.7__tar.gz
This diff represents the content of publicly available package versions that have been released to one of the supported registries. The information contained in this diff is provided for informational purposes only and reflects changes between package versions as they appear in their respective public registries.
- {simplhdl-0.0.6 → simplhdl-0.0.7}/PKG-INFO +3 -1
- {simplhdl-0.0.6 → simplhdl-0.0.7}/pyproject.toml +2 -0
- {simplhdl-0.0.6 → simplhdl-0.0.7}/src/SimplHDL.egg-info/PKG-INFO +3 -1
- {simplhdl-0.0.6 → simplhdl-0.0.7}/src/SimplHDL.egg-info/SOURCES.txt +4 -0
- {simplhdl-0.0.6 → simplhdl-0.0.7}/src/SimplHDL.egg-info/requires.txt +2 -0
- simplhdl-0.0.7/src/simplhdl/__init__.py +1 -0
- {simplhdl-0.0.6 → simplhdl-0.0.7}/src/simplhdl/cocotb.py +0 -1
- simplhdl-0.0.7/src/simplhdl/flows/flake8/flake8flow.py +83 -0
- simplhdl-0.0.7/src/simplhdl/flows/lint/lintflow.py +72 -0
- {simplhdl-0.0.6 → simplhdl-0.0.7}/src/simplhdl/flows/simulationflow.py +20 -3
- {simplhdl-0.0.6 → simplhdl-0.0.7}/src/simplhdl/flows/verible/veribleflow.py +24 -23
- {simplhdl-0.0.6 → simplhdl-0.0.7}/src/simplhdl/flows/vsg/vsgflow.py +29 -14
- {simplhdl-0.0.6 → simplhdl-0.0.7}/src/simplhdl/parser.py +17 -1
- {simplhdl-0.0.6 → simplhdl-0.0.7}/src/simplhdl/plugins.py +2 -0
- {simplhdl-0.0.6 → simplhdl-0.0.7}/src/simplhdl/pyedaa/__init__.py +5 -1
- simplhdl-0.0.7/src/simplhdl/resources/templates/flake8/setup.cfg.j2 +10 -0
- {simplhdl-0.0.6/src/simplhdl/resources/templates/rivierapro → simplhdl-0.0.7/src/simplhdl/resources/templates/questasim}/files.j2 +1 -0
- {simplhdl-0.0.6/src/simplhdl/resources/templates/vcs → simplhdl-0.0.7/src/simplhdl/resources/templates/rivierapro}/files.j2 +1 -0
- {simplhdl-0.0.6/src/simplhdl/resources/templates/xsim → simplhdl-0.0.7/src/simplhdl/resources/templates/vcs}/files.j2 +1 -0
- simplhdl-0.0.7/src/simplhdl/resources/templates/verible/rules.cfg.j2 +58 -0
- {simplhdl-0.0.6 → simplhdl-0.0.7}/src/simplhdl/utils.py +3 -2
- {simplhdl-0.0.6 → simplhdl-0.0.7}/tox.ini +1 -0
- simplhdl-0.0.6/src/simplhdl/__init__.py +0 -1
- {simplhdl-0.0.6 → simplhdl-0.0.7}/.github/workflows/publish.yml +0 -0
- {simplhdl-0.0.6 → simplhdl-0.0.7}/.gitignore +0 -0
- {simplhdl-0.0.6 → simplhdl-0.0.7}/.readthedocs.yaml +0 -0
- {simplhdl-0.0.6 → simplhdl-0.0.7}/LICENSE +0 -0
- {simplhdl-0.0.6 → simplhdl-0.0.7}/README.md +0 -0
- {simplhdl-0.0.6 → simplhdl-0.0.7}/docs/_static/simplhdl_dark.png +0 -0
- {simplhdl-0.0.6 → simplhdl-0.0.7}/docs/_static/simplhdl_light.png +0 -0
- {simplhdl-0.0.6 → simplhdl-0.0.7}/docs/_static/simplhdl_light_1.png +0 -0
- {simplhdl-0.0.6 → simplhdl-0.0.7}/docs/conf.py +0 -0
- {simplhdl-0.0.6 → simplhdl-0.0.7}/docs/drawing.svg +0 -0
- {simplhdl-0.0.6 → simplhdl-0.0.7}/docs/flows/ghdl.rst +0 -0
- {simplhdl-0.0.6 → simplhdl-0.0.7}/docs/flows/icarus.rst +0 -0
- {simplhdl-0.0.6 → simplhdl-0.0.7}/docs/flows/quartus.rst +0 -0
- {simplhdl-0.0.6 → simplhdl-0.0.7}/docs/flows/questasim.rst +0 -0
- {simplhdl-0.0.6 → simplhdl-0.0.7}/docs/flows/vcs.rst +0 -0
- {simplhdl-0.0.6 → simplhdl-0.0.7}/docs/flows/vivado.rst +0 -0
- {simplhdl-0.0.6 → simplhdl-0.0.7}/docs/flows/xsim.rst +0 -0
- {simplhdl-0.0.6 → simplhdl-0.0.7}/docs/flows.rst +0 -0
- {simplhdl-0.0.6 → simplhdl-0.0.7}/docs/index.rst +0 -0
- {simplhdl-0.0.6 → simplhdl-0.0.7}/docs/intel-ips.md +0 -0
- {simplhdl-0.0.6 → simplhdl-0.0.7}/docs/introduction.rst +0 -0
- {simplhdl-0.0.6 → simplhdl-0.0.7}/docs/plugins.rst +0 -0
- {simplhdl-0.0.6 → simplhdl-0.0.7}/docs/requirements.txt +0 -0
- {simplhdl-0.0.6 → simplhdl-0.0.7}/examples/hdl/adder/adder.yml +0 -0
- {simplhdl-0.0.6 → simplhdl-0.0.7}/examples/hdl/adder/hdl/adder.sv +0 -0
- {simplhdl-0.0.6 → simplhdl-0.0.7}/examples/hdl/adder/sim/testbench.sv +0 -0
- {simplhdl-0.0.6 → simplhdl-0.0.7}/examples/hdl/adder/sim/testbench.yml +0 -0
- {simplhdl-0.0.6 → simplhdl-0.0.7}/examples/hdl/adder/syn/build.yml +0 -0
- {simplhdl-0.0.6 → simplhdl-0.0.7}/examples/hdl/adder/syn/placement.xdc +0 -0
- {simplhdl-0.0.6 → simplhdl-0.0.7}/examples/hdl/adder/syn/timing.xdc +0 -0
- {simplhdl-0.0.6 → simplhdl-0.0.7}/examples/hdl/adder/syn/top.sv +0 -0
- {simplhdl-0.0.6 → simplhdl-0.0.7}/examples/hdl/alu/alu.yml +0 -0
- {simplhdl-0.0.6 → simplhdl-0.0.7}/examples/hdl/alu/hdl/add.sv +0 -0
- {simplhdl-0.0.6 → simplhdl-0.0.7}/examples/hdl/alu/hdl/alu.sv +0 -0
- {simplhdl-0.0.6 → simplhdl-0.0.7}/examples/hdl/alu/hdl/mul.sv +0 -0
- {simplhdl-0.0.6 → simplhdl-0.0.7}/examples/hdl/alu/hdl/sub.sv +0 -0
- {simplhdl-0.0.6 → simplhdl-0.0.7}/examples/hdl/alu/sim/pyuvm/alu_vip/__init__.py +0 -0
- {simplhdl-0.0.6 → simplhdl-0.0.7}/examples/hdl/alu/sim/pyuvm/alu_vip/agent.py +0 -0
- {simplhdl-0.0.6 → simplhdl-0.0.7}/examples/hdl/alu/sim/pyuvm/alu_vip/aluif.py +0 -0
- {simplhdl-0.0.6 → simplhdl-0.0.7}/examples/hdl/alu/sim/pyuvm/alu_vip/driver.py +0 -0
- {simplhdl-0.0.6 → simplhdl-0.0.7}/examples/hdl/alu/sim/pyuvm/alu_vip/monitor.py +0 -0
- {simplhdl-0.0.6 → simplhdl-0.0.7}/examples/hdl/alu/sim/pyuvm/alu_vip/sequenceitem.py +0 -0
- {simplhdl-0.0.6 → simplhdl-0.0.7}/examples/hdl/alu/sim/pyuvm/alu_vip/sequencer.py +0 -0
- {simplhdl-0.0.6 → simplhdl-0.0.7}/examples/hdl/alu/sim/pyuvm/clock_vip/__init__.py +0 -0
- {simplhdl-0.0.6 → simplhdl-0.0.7}/examples/hdl/alu/sim/pyuvm/clock_vip/agent.py +0 -0
- {simplhdl-0.0.6 → simplhdl-0.0.7}/examples/hdl/alu/sim/pyuvm/clock_vip/clockif.py +0 -0
- {simplhdl-0.0.6 → simplhdl-0.0.7}/examples/hdl/alu/sim/pyuvm/pyuvm.yml +0 -0
- {simplhdl-0.0.6 → simplhdl-0.0.7}/examples/hdl/alu/sim/pyuvm/test/__init__.py +0 -0
- {simplhdl-0.0.6 → simplhdl-0.0.7}/examples/hdl/alu/sim/pyuvm/test/env.py +0 -0
- {simplhdl-0.0.6 → simplhdl-0.0.7}/examples/hdl/alu/sim/pyuvm/test/seq_lib.py +0 -0
- {simplhdl-0.0.6 → simplhdl-0.0.7}/examples/hdl/alu/sim/pyuvm/test/test.py +0 -0
- {simplhdl-0.0.6 → simplhdl-0.0.7}/examples/hdl/alu/sim/pyuvm/testbench.py +0 -0
- {simplhdl-0.0.6 → simplhdl-0.0.7}/examples/hdl/alu/sim/uvm/alu_vip/agent.svh +0 -0
- {simplhdl-0.0.6 → simplhdl-0.0.7}/examples/hdl/alu/sim/uvm/alu_vip/alu_vip.sv +0 -0
- {simplhdl-0.0.6 → simplhdl-0.0.7}/examples/hdl/alu/sim/uvm/alu_vip/alu_vip.yml +0 -0
- {simplhdl-0.0.6 → simplhdl-0.0.7}/examples/hdl/alu/sim/uvm/alu_vip/driver.svh +0 -0
- {simplhdl-0.0.6 → simplhdl-0.0.7}/examples/hdl/alu/sim/uvm/alu_vip/env.svh +0 -0
- {simplhdl-0.0.6 → simplhdl-0.0.7}/examples/hdl/alu/sim/uvm/alu_vip/monitor.svh +0 -0
- {simplhdl-0.0.6 → simplhdl-0.0.7}/examples/hdl/alu/sim/uvm/alu_vip/sequence_item.svh +0 -0
- {simplhdl-0.0.6 → simplhdl-0.0.7}/examples/hdl/alu/sim/uvm/tb_env/seq_lib/add_seq.svh +0 -0
- {simplhdl-0.0.6 → simplhdl-0.0.7}/examples/hdl/alu/sim/uvm/tb_env/seq_lib/base_seq.svh +0 -0
- {simplhdl-0.0.6 → simplhdl-0.0.7}/examples/hdl/alu/sim/uvm/tb_env/tb_env.sv +0 -0
- {simplhdl-0.0.6 → simplhdl-0.0.7}/examples/hdl/alu/sim/uvm/tb_env/tb_env.yml +0 -0
- {simplhdl-0.0.6 → simplhdl-0.0.7}/examples/hdl/alu/sim/uvm/tb_env/test/base_test.svh +0 -0
- {simplhdl-0.0.6 → simplhdl-0.0.7}/examples/hdl/alu/sim/uvm/tb_env/test/test_add.svh +0 -0
- {simplhdl-0.0.6 → simplhdl-0.0.7}/examples/hdl/alu/sim/uvm/testbench/alu_if.sv +0 -0
- {simplhdl-0.0.6 → simplhdl-0.0.7}/examples/hdl/alu/sim/uvm/testbench/testbench.sv +0 -0
- {simplhdl-0.0.6 → simplhdl-0.0.7}/examples/hdl/alu/sim/uvm/testbench/testbench.yml +0 -0
- {simplhdl-0.0.6 → simplhdl-0.0.7}/examples/hdl/alu/sim/uvm/testcases/test_add/test_add.yml +0 -0
- {simplhdl-0.0.6 → simplhdl-0.0.7}/examples/hdl/alu/syn/build.yml +0 -0
- {simplhdl-0.0.6 → simplhdl-0.0.7}/examples/hdl/alu/syn/placement.xdc +0 -0
- {simplhdl-0.0.6 → simplhdl-0.0.7}/examples/hdl/alu/syn/timing.xdc +0 -0
- {simplhdl-0.0.6 → simplhdl-0.0.7}/examples/hdl/hello/build.sbt +0 -0
- {simplhdl-0.0.6 → simplhdl-0.0.7}/examples/hdl/hello/hello.yml +0 -0
- {simplhdl-0.0.6 → simplhdl-0.0.7}/examples/hdl/hello/src/main/scala/Hello.scala +0 -0
- {simplhdl-0.0.6 → simplhdl-0.0.7}/examples/hdl/hello/syn/build.yml +0 -0
- {simplhdl-0.0.6 → simplhdl-0.0.7}/examples/plugins/simple_parser/setup.py +0 -0
- {simplhdl-0.0.6 → simplhdl-0.0.7}/examples/plugins/simple_parser/src/simple_parser/__init__.py +0 -0
- {simplhdl-0.0.6 → simplhdl-0.0.7}/examples/plugins/simple_parser/src/simple_parser/simple_parser.py +0 -0
- {simplhdl-0.0.6 → simplhdl-0.0.7}/setup.cfg +0 -0
- {simplhdl-0.0.6 → simplhdl-0.0.7}/src/SimplHDL.egg-info/dependency_links.txt +0 -0
- {simplhdl-0.0.6 → simplhdl-0.0.7}/src/SimplHDL.egg-info/entry_points.txt +0 -0
- {simplhdl-0.0.6 → simplhdl-0.0.7}/src/SimplHDL.egg-info/top_level.txt +0 -0
- {simplhdl-0.0.6 → simplhdl-0.0.7}/src/simplhdl/__main__.py +0 -0
- {simplhdl-0.0.6 → simplhdl-0.0.7}/src/simplhdl/flow.py +0 -0
- {simplhdl-0.0.6 → simplhdl-0.0.7}/src/simplhdl/flows/__init__.py +0 -0
- {simplhdl-0.0.6 → simplhdl-0.0.7}/src/simplhdl/flows/implementationflow.py +0 -0
- {simplhdl-0.0.6 → simplhdl-0.0.7}/src/simplhdl/flows/modelsimflow.py +0 -0
- {simplhdl-0.0.6 → simplhdl-0.0.7}/src/simplhdl/flows/quartusdse/__init__.py +0 -0
- {simplhdl-0.0.6 → simplhdl-0.0.7}/src/simplhdl/flows/quartusdse/quartusdseflow.py +0 -0
- {simplhdl-0.0.6 → simplhdl-0.0.7}/src/simplhdl/flows/quartusflow.py +0 -0
- {simplhdl-0.0.6 → simplhdl-0.0.7}/src/simplhdl/flows/questasim/__init__.py +0 -0
- {simplhdl-0.0.6 → simplhdl-0.0.7}/src/simplhdl/flows/questasim/questasimflow.py +0 -0
- {simplhdl-0.0.6 → simplhdl-0.0.7}/src/simplhdl/flows/rivierapro/__init__.py +0 -0
- {simplhdl-0.0.6 → simplhdl-0.0.7}/src/simplhdl/flows/rivierapro/rivieraproflow.py +0 -0
- {simplhdl-0.0.6 → simplhdl-0.0.7}/src/simplhdl/flows/vcs/__init__.py +0 -0
- {simplhdl-0.0.6 → simplhdl-0.0.7}/src/simplhdl/flows/vcs/vcsflow.py +0 -0
- {simplhdl-0.0.6 → simplhdl-0.0.7}/src/simplhdl/flows/verible/__init__.py +0 -0
- {simplhdl-0.0.6 → simplhdl-0.0.7}/src/simplhdl/flows/vivadoflow.py +0 -0
- {simplhdl-0.0.6 → simplhdl-0.0.7}/src/simplhdl/flows/vsg/__init__.py +0 -0
- {simplhdl-0.0.6 → simplhdl-0.0.7}/src/simplhdl/flows/xsim/__init__.py +0 -0
- {simplhdl-0.0.6 → simplhdl-0.0.7}/src/simplhdl/flows/xsim/xsimflow.py +0 -0
- {simplhdl-0.0.6 → simplhdl-0.0.7}/src/simplhdl/generator.py +0 -0
- {simplhdl-0.0.6 → simplhdl-0.0.7}/src/simplhdl/generators/__init__.py +0 -0
- {simplhdl-0.0.6 → simplhdl-0.0.7}/src/simplhdl/generators/chisel.py +0 -0
- {simplhdl-0.0.6 → simplhdl-0.0.7}/src/simplhdl/generators/ipxact.py +0 -0
- {simplhdl-0.0.6 → simplhdl-0.0.7}/src/simplhdl/generators/spd.py +0 -0
- {simplhdl-0.0.6 → simplhdl-0.0.7}/src/simplhdl/generators/systemrdl.py +0 -0
- {simplhdl-0.0.6 → simplhdl-0.0.7}/src/simplhdl/info.py +0 -0
- {simplhdl-0.0.6 → simplhdl-0.0.7}/src/simplhdl/parsers/__init__.py +0 -0
- {simplhdl-0.0.6 → simplhdl-0.0.7}/src/simplhdl/parsers/fusesocparser.py +0 -0
- {simplhdl-0.0.6 → simplhdl-0.0.7}/src/simplhdl/parsers/simplhdlparser.py +0 -0
- {simplhdl-0.0.6 → simplhdl-0.0.7}/src/simplhdl/pyedaa/attributes.py +0 -0
- {simplhdl-0.0.6 → simplhdl-0.0.7}/src/simplhdl/pyedaa/design.py +0 -0
- {simplhdl-0.0.6 → simplhdl-0.0.7}/src/simplhdl/pyedaa/fileset.py +0 -0
- {simplhdl-0.0.6 → simplhdl-0.0.7}/src/simplhdl/pyedaa/filetypes.py +0 -0
- {simplhdl-0.0.6 → simplhdl-0.0.7}/src/simplhdl/pyedaa/project.py +0 -0
- {simplhdl-0.0.6 → simplhdl-0.0.7}/src/simplhdl/pyedaa/vhdllibrary.py +0 -0
- {simplhdl-0.0.6 → simplhdl-0.0.7}/src/simplhdl/repo.py +0 -0
- {simplhdl-0.0.6 → simplhdl-0.0.7}/src/simplhdl/resources/__init__.py +0 -0
- {simplhdl-0.0.6 → simplhdl-0.0.7}/src/simplhdl/resources/templates/__init__.py +0 -0
- {simplhdl-0.0.6/src/simplhdl/resources/templates/quartus → simplhdl-0.0.7/src/simplhdl/resources/templates/flake8}/__init__.py +0 -0
- {simplhdl-0.0.6/src/simplhdl/resources/templates/questasim → simplhdl-0.0.7/src/simplhdl/resources/templates/quartus}/__init__.py +0 -0
- {simplhdl-0.0.6 → simplhdl-0.0.7}/src/simplhdl/resources/templates/quartus/project.tcl.j2 +0 -0
- {simplhdl-0.0.6 → simplhdl-0.0.7}/src/simplhdl/resources/templates/quartus/run.tcl.j2 +0 -0
- {simplhdl-0.0.6 → simplhdl-0.0.7}/src/simplhdl/resources/templates/questasim/Makefile.j2 +0 -0
- {simplhdl-0.0.6/src/simplhdl/resources/templates/rivierapro → simplhdl-0.0.7/src/simplhdl/resources/templates/questasim}/__init__.py +0 -0
- {simplhdl-0.0.6 → simplhdl-0.0.7}/src/simplhdl/resources/templates/questasim/cocotb.mk.j2 +0 -0
- {simplhdl-0.0.6 → simplhdl-0.0.7}/src/simplhdl/resources/templates/questasim/dependencies.mk.j2 +0 -0
- {simplhdl-0.0.6 → simplhdl-0.0.7}/src/simplhdl/resources/templates/questasim/fileset.j2 +0 -0
- {simplhdl-0.0.6 → simplhdl-0.0.7}/src/simplhdl/resources/templates/questasim/gui.do.j2 +0 -0
- {simplhdl-0.0.6 → simplhdl-0.0.7}/src/simplhdl/resources/templates/questasim/project.mk.j2 +0 -0
- {simplhdl-0.0.6 → simplhdl-0.0.7}/src/simplhdl/resources/templates/rivierapro/Makefile.j2 +0 -0
- {simplhdl-0.0.6/src/simplhdl/resources/templates/vcs → simplhdl-0.0.7/src/simplhdl/resources/templates/rivierapro}/__init__.py +0 -0
- {simplhdl-0.0.6 → simplhdl-0.0.7}/src/simplhdl/resources/templates/rivierapro/cocotb.mk.j2 +0 -0
- {simplhdl-0.0.6 → simplhdl-0.0.7}/src/simplhdl/resources/templates/rivierapro/dependencies.mk.j2 +0 -0
- {simplhdl-0.0.6 → simplhdl-0.0.7}/src/simplhdl/resources/templates/rivierapro/fileset.j2 +0 -0
- {simplhdl-0.0.6 → simplhdl-0.0.7}/src/simplhdl/resources/templates/rivierapro/project.mk.j2 +0 -0
- {simplhdl-0.0.6 → simplhdl-0.0.7}/src/simplhdl/resources/templates/vcs/Makefile.j2 +0 -0
- {simplhdl-0.0.6/src/simplhdl/resources/templates/verible → simplhdl-0.0.7/src/simplhdl/resources/templates/vcs}/__init__.py +0 -0
- {simplhdl-0.0.6 → simplhdl-0.0.7}/src/simplhdl/resources/templates/vcs/cocotb.mk.j2 +0 -0
- {simplhdl-0.0.6 → simplhdl-0.0.7}/src/simplhdl/resources/templates/vcs/dependencies.mk.j2 +0 -0
- {simplhdl-0.0.6 → simplhdl-0.0.7}/src/simplhdl/resources/templates/vcs/fileset.j2 +0 -0
- {simplhdl-0.0.6 → simplhdl-0.0.7}/src/simplhdl/resources/templates/vcs/pli.tab.j2 +0 -0
- {simplhdl-0.0.6 → simplhdl-0.0.7}/src/simplhdl/resources/templates/vcs/project.mk.j2 +0 -0
- {simplhdl-0.0.6 → simplhdl-0.0.7}/src/simplhdl/resources/templates/vcs/synopsys_sim.setup.j2 +0 -0
- {simplhdl-0.0.6 → simplhdl-0.0.7}/src/simplhdl/resources/templates/vcs/vcs.parameters.j2 +0 -0
- {simplhdl-0.0.6/src/simplhdl/resources/templates/vivado → simplhdl-0.0.7/src/simplhdl/resources/templates/verible}/__init__.py +0 -0
- {simplhdl-0.0.6/src/simplhdl/resources/templates/vsg → simplhdl-0.0.7/src/simplhdl/resources/templates/vivado}/__init__.py +0 -0
- {simplhdl-0.0.6 → simplhdl-0.0.7}/src/simplhdl/resources/templates/vivado/launch_run.sh.j2 +0 -0
- {simplhdl-0.0.6 → simplhdl-0.0.7}/src/simplhdl/resources/templates/vivado/project.tcl.j2 +0 -0
- {simplhdl-0.0.6 → simplhdl-0.0.7}/src/simplhdl/resources/templates/vivado/run.tcl.j2 +0 -0
- {simplhdl-0.0.6 → simplhdl-0.0.7}/src/simplhdl/resources/templates/vivado/steps.tcl.j2 +0 -0
- {simplhdl-0.0.6/src/simplhdl/resources/templates/xsim → simplhdl-0.0.7/src/simplhdl/resources/templates/vsg}/__init__.py +0 -0
- {simplhdl-0.0.6 → simplhdl-0.0.7}/src/simplhdl/resources/templates/vsg/files.json.j2 +0 -0
- {simplhdl-0.0.6 → simplhdl-0.0.7}/src/simplhdl/resources/templates/vsg/rules.yml.j2 +0 -0
- {simplhdl-0.0.6 → simplhdl-0.0.7}/src/simplhdl/resources/templates/xsim/Makefile.j2 +0 -0
- /simplhdl-0.0.6/src/simplhdl/resources/templates/verible/rules.cfg.j2 → /simplhdl-0.0.7/src/simplhdl/resources/templates/xsim/__init__.py +0 -0
- {simplhdl-0.0.6 → simplhdl-0.0.7}/src/simplhdl/resources/templates/xsim/cocotb.mk.j2 +0 -0
- {simplhdl-0.0.6 → simplhdl-0.0.7}/src/simplhdl/resources/templates/xsim/dependencies.mk.j2 +0 -0
- {simplhdl-0.0.6/src/simplhdl/resources/templates/questasim → simplhdl-0.0.7/src/simplhdl/resources/templates/xsim}/files.j2 +0 -0
- {simplhdl-0.0.6 → simplhdl-0.0.7}/src/simplhdl/resources/templates/xsim/fileset.j2 +0 -0
- {simplhdl-0.0.6 → simplhdl-0.0.7}/src/simplhdl/resources/templates/xsim/project.mk.j2 +0 -0
- {simplhdl-0.0.6 → simplhdl-0.0.7}/src/simplhdl/simplhdl.py +0 -0
- {simplhdl-0.0.6 → simplhdl-0.0.7}/src/simplhdl/tools.py +0 -0
- {simplhdl-0.0.6 → simplhdl-0.0.7}/tests/test_dummy.py +0 -0
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Metadata-Version: 2.1
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Name: SimplHDL
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Version: 0.0.
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Version: 0.0.7
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Summary: A framework for simulating and implementing HDL designs
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Author-email: Rasmus Grøndahl Olsen <simplhdl@gmail.com>
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Maintainer-email: Rasmus Grøndahl Olsen <simplhdl@gmail.com>
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Requires-Dist: flake8
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## Introduction
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Metadata-Version: 2.1
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Name: SimplHDL
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Version: 0.0.
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Version: 0.0.7
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Summary: A framework for simulating and implementing HDL designs
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Author-email: Rasmus Grøndahl Olsen <simplhdl@gmail.com>
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Maintainer-email: Rasmus Grøndahl Olsen <simplhdl@gmail.com>
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Requires-Dist: flake8
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## Introduction
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src/simplhdl/flows/quartusflow.py
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src/simplhdl/flows/simulationflow.py
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src/simplhdl/flows/vivadoflow.py
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src/simplhdl/flows/flake8/flake8flow.py
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src/simplhdl/flows/lint/lintflow.py
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src/simplhdl/flows/quartusdse/__init__.py
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src/simplhdl/flows/quartusdse/quartusdseflow.py
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src/simplhdl/flows/questasim/__init__.py
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src/simplhdl/pyedaa/vhdllibrary.py
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src/simplhdl/resources/__init__.py
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src/simplhdl/resources/templates/__init__.py
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src/simplhdl/resources/templates/flake8/__init__.py
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src/simplhdl/resources/templates/flake8/setup.cfg.j2
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src/simplhdl/resources/templates/quartus/__init__.py
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src/simplhdl/resources/templates/quartus/project.tcl.j2
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src/simplhdl/resources/templates/quartus/run.tcl.j2
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__version__ = "0.0.7"
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try:
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from importlib.resources import files as resources_files
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except ImportError:
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from importlib_resources import files as resources_files
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import os
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import shutil
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import logging
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from argparse import Namespace
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from pathlib import Path
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from jinja2 import Environment, FileSystemLoader
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from simplhdl.resources.templates import flake8 as templates
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from simplhdl.utils import sh, CalledShError, generate_from_template
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from simplhdl.flow import FlowFactory, FlowBase
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from simplhdl.pyedaa.project import Project
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from simplhdl.pyedaa import PythonSourceFile
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logger = logging.getLogger(__name__)
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@FlowFactory.register('flake8')
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class Flake8Flow(FlowBase):
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@classmethod
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def parse_args(self, subparsers) -> None:
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parser = subparsers.add_parser('flake8', help='Lint Flow for Python code')
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parser.add_argument(
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'--fix',
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action='store_true',
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help="Fix style formatting (Note: this modifies the source)"
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)
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parser.add_argument(
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'-f', '--files',
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type=lambda p: Path(p).absolute(),
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nargs='+',
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default=[],
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help="Manually specify file list"
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)
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def __init__(self, name, args: Namespace, project: Project, builddir: Path):
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super().__init__(name, args, project, builddir)
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self.templates = templates
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def setup(self):
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os.makedirs(self.builddir, exist_ok=True)
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if self.args.files:
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self.files = [Path(f) for f in self.args.files if Path(f).suffix == '.py']
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else:
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self.files = [f.Path for f in self.project.DefaultDesign.DefaultFileSet.Files(PythonSourceFile)]
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def generate(self):
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config = os.getenv('SIMPLHDL_FLAKE8_RULES')
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if config:
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shutil.copy(config, self.builddir.joinpath('setup.cfg'))
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else:
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templatedir = resources_files(self.templates)
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environment = Environment(
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loader=FileSystemLoader(templatedir),
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trim_blocks=True)
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template = environment.get_template('setup.cfg.j2')
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generate_from_template(template, self.builddir)
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def execute(self):
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if self.args.fix:
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for file in self.files:
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sh(['black', str(file.absolute())])
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else:
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command = ['flake8'] + [str(f.absolute()) for f in self.files]
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try:
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sh(command, cwd=self.builddir, output=True)
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except CalledShError as e:
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print(e)
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raise SystemError
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# flake = flake8.get_style_guide()
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# report = flake.check_files(self.files)
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# if report.get_statistics('E'):
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# raise SystemError
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def run(self) -> None:
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self.setup()
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self.generate()
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self.execute()
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import os
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import logging
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from argparse import Namespace
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from pathlib import Path
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from simplhdl.flow import FlowFactory, FlowBase
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from simplhdl.pyedaa.project import Project
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from simplhdl.flows.verible.veribleflow import VeribleFlow
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from simplhdl.flows.vsg.vsgflow import VsgFlow
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from simplhdl.flows.flake8.flake8flow import Flake8Flow
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logger = logging.getLogger(__name__)
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@FlowFactory.register('lint')
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class LintFlow(FlowBase):
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@classmethod
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def parse_args(self, subparsers) -> None:
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parser = subparsers.add_parser('lint', help='Lint Flow for Design and Verification code')
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parser.add_argument(
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'--fix',
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action='store_true',
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help="Fix style formatting (Note: this modifies the source)"
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)
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parser.add_argument(
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'-f', '--files',
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type=lambda p: Path(p).absolute(),
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nargs='+',
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default=[],
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help="Manually specify file list"
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)
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def __init__(self, name, args: Namespace, project: Project, builddir: Path):
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super().__init__(name, args, project, builddir)
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def setup(self):
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os.makedirs(self.builddir, exist_ok=True)
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def generate(self):
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pass
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def execute(self):
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verible_args = Namespace(rules=None, files=self.args.files, fix=self.args.fix)
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verible = VeribleFlow('verible', verible_args, self.project, self.builddir)
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vsg_args = Namespace(rules=None, files=self.args.files, fix=self.args.fix, output_format='syntastic')
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vsg = VsgFlow('vsg', vsg_args, self.project, self.builddir)
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flake_args = Namespace(files=self.args.files, fix=self.args.fix)
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flake = Flake8Flow('flake8', flake_args, self.project, self.builddir)
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system_error = False
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try:
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verible.run()
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except SystemError:
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system_error = True
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try:
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vsg.run()
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except SystemError:
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system_error = True
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try:
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flake.run()
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except SystemError:
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system_error = True
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if system_error:
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raise SystemError
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def run(self) -> None:
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self.setup()
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self.generate()
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self.execute()
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@@ -17,7 +17,7 @@ from simplhdl.cocotb import Cocotb
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17
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from simplhdl.pyedaa.fileset import FileSet
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from simplhdl.pyedaa import (File, VerilogSourceFile, VerilogIncludeFile,
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SystemVerilogSourceFile, VHDLSourceFile)
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from simplhdl.utils import generate_from_template, md5sum, append_suffix
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from simplhdl.utils import generate_from_template, md5sum, md5check, md5write, append_suffix
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logger = logging.getLogger(__name__)
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@@ -28,10 +28,11 @@ class SimulationFlow(FlowBase):
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28
28
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super().__init__(name, args, project, builddir)
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29
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self.category = FlowCategory.SIMULATION
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self.hdl_language = None
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-
self.cocotb = Cocotb(project)
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self.templates = None
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self.hashfile = self.builddir.joinpath('filesets.hash')
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34
34
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def run(self) -> None:
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self.cocotb = Cocotb(self.project)
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35
36
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self.validate()
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self.configure()
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self.generate()
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@@ -74,6 +75,7 @@ class SimulationFlow(FlowBase):
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74
75
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for template in self.get_project_templates(env) + self.get_cocotb_templates(env):
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generate_from_template(template, self.builddir, self.get_globals())
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self.generate_make_rules(env)
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self.is_filesets_changed()
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80
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def generate_make_rules(self, environment):
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79
81
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walker = FileSetWalker()
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@@ -126,7 +128,8 @@ class SimulationFlow(FlowBase):
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126
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template,
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129
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base.with_suffix('.files'),
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target=base.with_suffix('.fileset').name,
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129
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-
files=[f.Path.absolute() for f in files]
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files=[f.Path.absolute() for f in files],
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hashfile=self.hashfile.name)
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template = environment.get_template('fileset.j2')
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output = base.with_suffix('.fileset')
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135
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includes = {f.Path.parent.absolute() for f in files if isinstance(f, VerilogIncludeFile)}
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@@ -159,6 +162,20 @@ class SimulationFlow(FlowBase):
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159
162
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libraries.update(self.project.DefaultDesign.ExternalVHDLLibraries)
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return libraries
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165
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def is_filesets_changed(self) -> bool:
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"""
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Check if there are any changes in filesets since last run.
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"""
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filesets = []
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walker = FileSetWalker()
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for fileset in walker.walk(self.project.DefaultDesign.DefaultFileSet):
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filesets += [Path(f.Name) for f in FileSetWalker().walk(fileset) if Path(f.Name).is_file()]
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if self.hashfile.is_file() and md5check(*filesets, filename=self.hashfile):
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return True
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else:
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md5write(*filesets, filename=self.hashfile)
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return False
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179
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163
180
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class FileSetWalker:
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164
181
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@@ -23,11 +23,11 @@ class VeribleFlow(FlowBase):
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23
23
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@classmethod
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24
24
|
def parse_args(self, subparsers) -> None:
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25
25
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parser = subparsers.add_parser('verible-verilog-lint', help='Verible Lint Flow')
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parser.add_argument(
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'--fix',
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action='store_true',
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|
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help="Fix style formatting (Note: this modifies the source)"
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30
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)
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|
31
31
|
parser.add_argument(
|
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32
32
|
'-r', '--rules',
|
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33
33
|
action='store',
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@@ -49,29 +49,30 @@ class VeribleFlow(FlowBase):
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49
49
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os.makedirs(self.builddir, exist_ok=True)
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50
50
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51
51
|
def generate(self):
|
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52
|
-
templatedir = resources_files(self.templates)
|
|
53
|
-
environment = Environment(
|
|
54
|
-
loader=FileSystemLoader(templatedir),
|
|
55
|
-
trim_blocks=True)
|
|
56
|
-
template = environment.get_template('rules.cfg.j2')
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|
57
|
-
generate_from_template(template, self.builddir)
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58
|
-
|
|
59
|
-
def execute(self):
|
|
60
|
-
errors = False
|
|
61
|
-
command = ["verible-verilog-lint"]
|
|
62
52
|
if self.args.rules:
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63
|
-
rules = self.args.rules
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|
53
|
+
self.rules = self.args.rules
|
|
64
54
|
elif os.getenv('SIMPLHDL_VERIBLE_RULES'):
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65
|
-
rules = self.args.rules
|
|
55
|
+
self.rules = self.args.rules
|
|
66
56
|
else:
|
|
67
|
-
|
|
57
|
+
templatedir = resources_files(self.templates)
|
|
58
|
+
environment = Environment(
|
|
59
|
+
loader=FileSystemLoader(templatedir),
|
|
60
|
+
trim_blocks=True)
|
|
61
|
+
template = environment.get_template('rules.cfg.j2')
|
|
62
|
+
generate_from_template(template, self.builddir)
|
|
63
|
+
self.rules = 'rules.cfg'
|
|
68
64
|
|
|
69
|
-
|
|
65
|
+
def execute(self):
|
|
66
|
+
errors = False
|
|
67
|
+
command = [
|
|
68
|
+
"verible-verilog-lint",
|
|
69
|
+
"--check_syntax=false",
|
|
70
|
+
"--ruleset=all",
|
|
71
|
+
"--rules_config", self.rules
|
|
72
|
+
]
|
|
70
73
|
|
|
71
|
-
|
|
72
|
-
|
|
73
|
-
# else:
|
|
74
|
-
# command += f"-ap -of {self.args.output_format}".split()
|
|
74
|
+
if self.args.fix:
|
|
75
|
+
command += ["--autofix=inplace"]
|
|
75
76
|
|
|
76
77
|
file_types = [VerilogIncludeFile, VerilogSourceFile, SystemVerilogSourceFile]
|
|
77
78
|
files = [f for f in self.project.DefaultDesign.Files() if f.FileType in file_types]
|
|
@@ -8,13 +8,14 @@ from argparse import Namespace
|
|
|
8
8
|
from pathlib import Path
|
|
9
9
|
from jinja2 import Environment, FileSystemLoader
|
|
10
10
|
|
|
11
|
-
from simplhdl.flow import FlowFactory, FlowBase
|
|
11
|
+
from simplhdl.flow import FlowFactory, FlowBase, FlowError
|
|
12
12
|
from simplhdl.resources.templates import vsg as templates
|
|
13
13
|
from simplhdl.utils import sh, CalledShError, generate_from_template
|
|
14
14
|
from simplhdl.pyedaa import VHDLSourceFile
|
|
15
15
|
from simplhdl.pyedaa.project import Project
|
|
16
16
|
from simplhdl.pyedaa.attributes import UsedIn
|
|
17
17
|
|
|
18
|
+
|
|
18
19
|
logger = logging.getLogger(__name__)
|
|
19
20
|
|
|
20
21
|
|
|
@@ -31,7 +32,7 @@ class VsgFlow(FlowBase):
|
|
|
31
32
|
'syntastic',
|
|
32
33
|
'summary'
|
|
33
34
|
],
|
|
34
|
-
default=
|
|
35
|
+
default=None,
|
|
35
36
|
help="Display output format"
|
|
36
37
|
)
|
|
37
38
|
parser.add_argument(
|
|
@@ -55,6 +56,8 @@ class VsgFlow(FlowBase):
|
|
|
55
56
|
def __init__(self, name, args: Namespace, project: Project, builddir: Path):
|
|
56
57
|
super().__init__(name, args, project, builddir)
|
|
57
58
|
self.templates = templates
|
|
59
|
+
# file limit to change output for to summary
|
|
60
|
+
self.file_limit: int = 5
|
|
58
61
|
|
|
59
62
|
def setup(self):
|
|
60
63
|
os.makedirs(self.builddir, exist_ok=True)
|
|
@@ -69,29 +72,41 @@ class VsgFlow(FlowBase):
|
|
|
69
72
|
VHDLSourceFile=VHDLSourceFile,
|
|
70
73
|
project=self.project,
|
|
71
74
|
UsedIn=UsedIn)
|
|
72
|
-
template = environment.get_template('rules.yml.j2')
|
|
73
|
-
generate_from_template(template, self.builddir)
|
|
74
|
-
|
|
75
|
-
def execute(self):
|
|
76
|
-
command = ["vsg"]
|
|
77
75
|
if self.args.rules:
|
|
78
|
-
rules = self.args.rules
|
|
76
|
+
self.rules = self.args.rules
|
|
79
77
|
elif os.getenv('SIMPLHDL_VSG_RULES'):
|
|
80
|
-
rules = self.args.rules
|
|
78
|
+
self.rules = self.args.rules
|
|
81
79
|
else:
|
|
82
|
-
|
|
80
|
+
template = environment.get_template('rules.yml.j2')
|
|
81
|
+
generate_from_template(template, self.builddir)
|
|
82
|
+
self.rules = 'rules.yml'
|
|
83
|
+
|
|
84
|
+
def execute(self):
|
|
85
|
+
command = ["vsg"]
|
|
86
|
+
user_files = len(self.args.files)
|
|
87
|
+
project_files = len(list(self.project.DefaultDesign.DefaultFileSet.Files(VHDLSourceFile)))
|
|
83
88
|
|
|
84
89
|
if self.args.fix:
|
|
85
90
|
command.append("--fix")
|
|
91
|
+
elif self.args.output_format is None:
|
|
92
|
+
if user_files > self.file_limit:
|
|
93
|
+
format = "summary"
|
|
94
|
+
elif project_files > self.file_limit and not user_files:
|
|
95
|
+
format = "summary"
|
|
96
|
+
else:
|
|
97
|
+
format = "vsg"
|
|
98
|
+
command += f"-ap -of {format}".split()
|
|
86
99
|
else:
|
|
87
100
|
command += f"-ap -of {self.args.output_format}".split()
|
|
88
101
|
|
|
89
|
-
if
|
|
90
|
-
if rules:
|
|
91
|
-
command += f"-c {rules}".split()
|
|
102
|
+
if user_files:
|
|
103
|
+
if self.rules:
|
|
104
|
+
command += f"-c {self.rules}".split()
|
|
92
105
|
command += ['-f'] + self.args.files
|
|
106
|
+
elif project_files:
|
|
107
|
+
command += f"-c {self.rules} files.json".split()
|
|
93
108
|
else:
|
|
94
|
-
|
|
109
|
+
raise FlowError("No VHDL files")
|
|
95
110
|
|
|
96
111
|
try:
|
|
97
112
|
logger.debug(command)
|
|
@@ -1,3 +1,5 @@
|
|
|
1
|
+
import logging
|
|
2
|
+
|
|
1
3
|
from pathlib import Path
|
|
2
4
|
from typing import Callable
|
|
3
5
|
from abc import ABCMeta, abstractmethod
|
|
@@ -6,6 +8,8 @@ from argparse import Namespace
|
|
|
6
8
|
from .pyedaa.fileset import FileSet
|
|
7
9
|
from .pyedaa.project import Project
|
|
8
10
|
|
|
11
|
+
logger = logging.getLogger(__name__)
|
|
12
|
+
|
|
9
13
|
|
|
10
14
|
class ParserBase(metaclass=ABCMeta):
|
|
11
15
|
|
|
@@ -21,6 +25,17 @@ class ParserBase(metaclass=ABCMeta):
|
|
|
21
25
|
pass
|
|
22
26
|
|
|
23
27
|
|
|
28
|
+
class NoParser(ParserBase):
|
|
29
|
+
"""
|
|
30
|
+
This parser always returns an empty fileset
|
|
31
|
+
"""
|
|
32
|
+
def is_valid_format(self, filename: Path) -> bool:
|
|
33
|
+
return True
|
|
34
|
+
|
|
35
|
+
def parse(self, filename: Path, project: Project, args: Namespace) -> 'FileSet':
|
|
36
|
+
return FileSet('Empty')
|
|
37
|
+
|
|
38
|
+
|
|
24
39
|
class ParserFactory:
|
|
25
40
|
"""
|
|
26
41
|
Factory for creating parsers
|
|
@@ -47,7 +62,8 @@ class ParserFactory:
|
|
|
47
62
|
if parser.is_valid_format(filename):
|
|
48
63
|
return parser
|
|
49
64
|
if filename is None:
|
|
50
|
-
|
|
65
|
+
logger.info("No project specification found, continue with empty project")
|
|
66
|
+
return NoParser()
|
|
51
67
|
else:
|
|
52
68
|
raise ParserError(f"Couldn't find Parser for parsing '{filename}'")
|
|
53
69
|
|
|
@@ -30,6 +30,8 @@ def load_builtin_plugins() -> None:
|
|
|
30
30
|
import_module('simplhdl.flows.quartusdse.quartusdseflow')
|
|
31
31
|
import_module('simplhdl.flows.vsg.vsgflow')
|
|
32
32
|
import_module('simplhdl.flows.verible.veribleflow')
|
|
33
|
+
import_module('simplhdl.flows.lint.lintflow')
|
|
34
|
+
import_module('simplhdl.flows.flake8.flake8flow')
|
|
33
35
|
packages = chain(
|
|
34
36
|
iter_namespace(simplhdl.parsers),
|
|
35
37
|
iter_namespace(simplhdl.flows),
|
|
@@ -73,7 +73,11 @@ class VHDLSourceFile(HDLSourceFile, pm.HumanReadableContent):
|
|
|
73
73
|
pass
|
|
74
74
|
|
|
75
75
|
|
|
76
|
-
class
|
|
76
|
+
class PythonSourceFile(pm.PythonSourceFile):
|
|
77
|
+
pass
|
|
78
|
+
|
|
79
|
+
|
|
80
|
+
class CocotbPythonFile(PythonSourceFile, FileMixIn):
|
|
77
81
|
def _registerAttributes(self):
|
|
78
82
|
super()._registerAttributes()
|
|
79
83
|
FileMixIn._registerAttributes(self)
|
|
@@ -0,0 +1,58 @@
|
|
|
1
|
+
+always-comb
|
|
2
|
+
+always-comb-blocking
|
|
3
|
+
+always-ff-non-blocking
|
|
4
|
+
+banned-declared-name-patterns
|
|
5
|
+
+case-missing-default
|
|
6
|
+
+constraint-name-style
|
|
7
|
+
+create-object-name-match
|
|
8
|
+
+disable-statement
|
|
9
|
+
+endif-comment
|
|
10
|
+
+enum-name-style
|
|
11
|
+
+explicit-function-lifetime
|
|
12
|
+
+explicit-function-task-parameter-type
|
|
13
|
+
+explicit-parameter-storage-type
|
|
14
|
+
+explicit-task-lifetime
|
|
15
|
+
+forbid-consecutive-null-statements
|
|
16
|
+
+forbid-defparam
|
|
17
|
+
+forbid-line-continuations
|
|
18
|
+
+forbid-negative-array-dim
|
|
19
|
+
+forbidden-macro
|
|
20
|
+
+generate-label
|
|
21
|
+
+generate-label-prefix
|
|
22
|
+
+interface-name-style
|
|
23
|
+
+invalid-system-task-function
|
|
24
|
+
+legacy-generate-region
|
|
25
|
+
+legacy-genvar-declaration
|
|
26
|
+
+line-length
|
|
27
|
+
+macro-name-style
|
|
28
|
+
+macro-string-concatenation
|
|
29
|
+
+mismatched-labels
|
|
30
|
+
+module-begin-block
|
|
31
|
+
+module-filename
|
|
32
|
+
+module-parameter
|
|
33
|
+
+module-port
|
|
34
|
+
+no-tabs
|
|
35
|
+
+no-trailing-spaces
|
|
36
|
+
+numeric-format-string-style
|
|
37
|
+
+one-module-per-file
|
|
38
|
+
+package-filename
|
|
39
|
+
+packed-dimensions-range-ordering
|
|
40
|
+
+parameter-name-style="localparam_style:ALL_CAPS;parameter_style:ALL_CAPS"
|
|
41
|
+
-parameter-type-name-style
|
|
42
|
+
+plusarg-assignment
|
|
43
|
+
+port-name-suffix
|
|
44
|
+
+positive-meaning-parameter-name
|
|
45
|
+
+posix-eof
|
|
46
|
+
-proper-parameter-declaration
|
|
47
|
+
-signal-name-style
|
|
48
|
+
+struct-union-name-style
|
|
49
|
+
+suggest-parentheses
|
|
50
|
+
-suspicious-semicolon
|
|
51
|
+
+truncated-numeric-literal
|
|
52
|
+
+typedef-enums
|
|
53
|
+
+typedef-structs-unions
|
|
54
|
+
+undersized-binary-literal
|
|
55
|
+
+unpacked-dimensions-range-ordering
|
|
56
|
+
-uvm-macro-semicolon
|
|
57
|
+
+v2001-generate-begin
|
|
58
|
+
+void-cast
|
|
@@ -2,7 +2,7 @@ import os
|
|
|
2
2
|
import sys
|
|
3
3
|
import logging
|
|
4
4
|
|
|
5
|
-
from typing import Dict, List, Optional, Union
|
|
5
|
+
from typing import Dict, List, Optional, Union, Generator
|
|
6
6
|
from pathlib import Path
|
|
7
7
|
from contextlib import contextmanager
|
|
8
8
|
from time import sleep
|
|
@@ -21,6 +21,7 @@ def sh(command: List[str], cwd: Optional[Path] = None, output=False, shell=False
|
|
|
21
21
|
if os.name == 'nt':
|
|
22
22
|
shell = True
|
|
23
23
|
|
|
24
|
+
logger.debug(' '.join(command))
|
|
24
25
|
with Popen(command, stdout=PIPE, stderr=PIPE, cwd=cwd, shell=shell) as p:
|
|
25
26
|
if output:
|
|
26
27
|
stdout: str = ''
|
|
@@ -132,7 +133,7 @@ def escape(a: str) -> str:
|
|
|
132
133
|
|
|
133
134
|
|
|
134
135
|
@contextmanager
|
|
135
|
-
def lock(directory: Path) -> Path:
|
|
136
|
+
def lock(directory: Path) -> Generator[Path, None, None]:
|
|
136
137
|
while not mkdir(directory):
|
|
137
138
|
sleep(1)
|
|
138
139
|
try:
|
|
@@ -1 +0,0 @@
|
|
|
1
|
-
__version__ = "0.0.6"
|
|
File without changes
|
|
File without changes
|
|
File without changes
|
|
File without changes
|
|
File without changes
|
|
File without changes
|
|
File without changes
|
|
File without changes
|