SimplHDL 0.0.4__tar.gz → 0.0.6__tar.gz

{SimplHDL-0.0.4 → simplhdl-0.0.6}/PKG-INFO

@@ -1,6 +1,6 @@
 Metadata-Version: 2.1
 Name: SimplHDL
-Version: 0.0.4
+Version: 0.0.6
 Summary: A framework for simulating and implementing HDL designs
 Author-email: Rasmus Grøndahl Olsen <simplhdl@gmail.com>
 Maintainer-email: Rasmus Grøndahl Olsen <simplhdl@gmail.com>
@@ -51,6 +51,8 @@ Requires-Dist: types-PyYAML
 Requires-Dist: argcomplete
 Requires-Dist: jinja2
 Requires-Dist: GitPython
+Requires-Dist: rich
+Requires-Dist: vsg
 
 ## Introduction
 

{SimplHDL-0.0.4 → simplhdl-0.0.6}/pyproject.toml

@@ -20,6 +20,8 @@ dependencies = [
     "argcomplete",
     "jinja2",
     "GitPython",
+    "rich",
+    "vsg",
 ]
 requires-python = ">=3.8"
 authors = [

{SimplHDL-0.0.4 → simplhdl-0.0.6}/src/SimplHDL.egg-info/PKG-INFO

@@ -1,6 +1,6 @@
 Metadata-Version: 2.1
 Name: SimplHDL
-Version: 0.0.4
+Version: 0.0.6
 Summary: A framework for simulating and implementing HDL designs
 Author-email: Rasmus Grøndahl Olsen <simplhdl@gmail.com>
 Maintainer-email: Rasmus Grøndahl Olsen <simplhdl@gmail.com>
@@ -51,6 +51,8 @@ Requires-Dist: types-PyYAML
 Requires-Dist: argcomplete
 Requires-Dist: jinja2
 Requires-Dist: GitPython
+Requires-Dist: rich
+Requires-Dist: vsg
 
 ## Introduction
 

{SimplHDL-0.0.4 → simplhdl-0.0.6}/src/SimplHDL.egg-info/SOURCES.txt

@@ -103,12 +103,18 @@ src/simplhdl/flows/modelsimflow.py
 src/simplhdl/flows/quartusflow.py
 src/simplhdl/flows/simulationflow.py
 src/simplhdl/flows/vivadoflow.py
+src/simplhdl/flows/quartusdse/__init__.py
+src/simplhdl/flows/quartusdse/quartusdseflow.py
 src/simplhdl/flows/questasim/__init__.py
 src/simplhdl/flows/questasim/questasimflow.py
 src/simplhdl/flows/rivierapro/__init__.py
 src/simplhdl/flows/rivierapro/rivieraproflow.py
 src/simplhdl/flows/vcs/__init__.py
 src/simplhdl/flows/vcs/vcsflow.py
+src/simplhdl/flows/verible/__init__.py
+src/simplhdl/flows/verible/veribleflow.py
+src/simplhdl/flows/vsg/__init__.py
+src/simplhdl/flows/vsg/vsgflow.py
 src/simplhdl/flows/xsim/__init__.py
 src/simplhdl/flows/xsim/xsimflow.py
 src/simplhdl/generators/__init__.py
@@ -137,6 +143,7 @@ src/simplhdl/resources/templates/questasim/cocotb.mk.j2
 src/simplhdl/resources/templates/questasim/dependencies.mk.j2
 src/simplhdl/resources/templates/questasim/files.j2
 src/simplhdl/resources/templates/questasim/fileset.j2
+src/simplhdl/resources/templates/questasim/gui.do.j2
 src/simplhdl/resources/templates/questasim/project.mk.j2
 src/simplhdl/resources/templates/rivierapro/Makefile.j2
 src/simplhdl/resources/templates/rivierapro/__init__.py
@@ -154,11 +161,17 @@ src/simplhdl/resources/templates/vcs/fileset.j2
 src/simplhdl/resources/templates/vcs/pli.tab.j2
 src/simplhdl/resources/templates/vcs/project.mk.j2
 src/simplhdl/resources/templates/vcs/synopsys_sim.setup.j2
+src/simplhdl/resources/templates/vcs/vcs.parameters.j2
+src/simplhdl/resources/templates/verible/__init__.py
+src/simplhdl/resources/templates/verible/rules.cfg.j2
 src/simplhdl/resources/templates/vivado/__init__.py
 src/simplhdl/resources/templates/vivado/launch_run.sh.j2
 src/simplhdl/resources/templates/vivado/project.tcl.j2
 src/simplhdl/resources/templates/vivado/run.tcl.j2
 src/simplhdl/resources/templates/vivado/steps.tcl.j2
+src/simplhdl/resources/templates/vsg/__init__.py
+src/simplhdl/resources/templates/vsg/files.json.j2
+src/simplhdl/resources/templates/vsg/rules.yml.j2
 src/simplhdl/resources/templates/xsim/Makefile.j2
 src/simplhdl/resources/templates/xsim/__init__.py
 src/simplhdl/resources/templates/xsim/cocotb.mk.j2

{SimplHDL-0.0.4 → simplhdl-0.0.6}/src/SimplHDL.egg-info/requires.txt

@@ -5,6 +5,8 @@ types-PyYAML
 argcomplete
 jinja2
 GitPython
+rich
+vsg
 
 [:python_version < "3.9"]
 importlib-resources

simplhdl-0.0.6/src/simplhdl/__init__.py

@@ -0,0 +1 @@
+__version__ = "0.0.6"

{SimplHDL-0.0.4 → simplhdl-0.0.6}/src/simplhdl/__main__.py

@@ -73,6 +73,8 @@ def main():
         logger.debug(traceback.format_exc())
         logger.error(e)
         return 1
+    except SystemError:
+        return 1
 
 
 if __name__ == '__main__':

simplhdl-0.0.6/src/simplhdl/cocotb.py

@@ -0,0 +1,118 @@
+import logging
+import re
+
+from pathlib import Path
+from typing import Optional
+
+from .utils import sh
+from .pyedaa.project import Project
+from .pyedaa import VerilogIncludeFile, VerilogSourceFile, SystemVerilogSourceFile, VHDLSourceFile, CocotbPythonFile
+from .flow import FlowError
+
+logger = logging.getLogger(__name__)
+
+
+class Cocotb:
+
+    def __init__(self, project: Project) -> None:
+        self.project = project
+        self.top = self.module()
+        self.dut = self.get_dut()
+        self.toplevels = self.hdltoplevels()
+        self.duttype = self.hdltype()
+
+    def lib_name_path(self, simulator: str, interface: str) -> Path:
+        output = sh(['cocotb-config', '--lib-name-path', interface, simulator])
+        path = Path(output)
+        if not path.exists():
+            raise FileNotFoundError(f"{path}: not found")
+        return path
+
+    def module(self) -> Optional[str]:
+        set_ = set()
+        try:
+            modules = self.project.DefaultDesign._topLevel.split()
+        except AttributeError:
+            raise FlowError("No top levels found")
+
+        for module in modules:
+            if self.is_python_module(module):
+                # TODO: What if more than one module match?
+                set_.add(module)
+        if not set_:
+            return None
+        elif len(set_) == 1:
+            return next(iter(set_))
+        else:
+            raise NotImplementedError(f"More than one CocoTB module found: {set_}")
+
+    def hdltoplevels(self) -> str:
+        tops = []
+        for t in self.project.DefaultDesign._topLevel.split():
+            if t != self.top:
+                tops.append(t)
+        return ' '.join(tops)
+
+    def get_dut(self) -> str:
+        for top in self.project.DefaultDesign._topLevel.split():
+            if top != self.top:
+                return top
+
+    def hdltype(self):  # noqa: C901
+        logger.debug(f"Cocotb hdl dut '{self.dut}'")
+        lib = next(iter(self.project.DefaultDesign.VHDLLibraries))
+        if '.' in self.dut:
+            lib, name = self.dut.split('.')
+        else:
+            name = self.dut
+
+        files = list(self.project.DefaultDesign.Files())
+        try:
+            for file in reversed(files):
+                if file.FileType in [VHDLSourceFile]:
+                    with open(file.Path, 'r', errors='replace') as f:
+                        lines = f.readlines()
+                        for line in lines:
+                            if re.search(rf'^\s*entity\s+{name}\s+is', line, re.IGNORECASE):
+                                if file.Library.Name == lib:
+                                    logger.info(f"Cocotb dut '{self.dut}' is VHDL")
+                                    return VHDLSourceFile
+                                else:
+                                    logger.warning(f"Found HDL entity {name} in ",
+                                                   f"library '{file.Library.Name}' expected '{lib}'")
+                if file.FileType in [VerilogIncludeFile, VerilogSourceFile, SystemVerilogSourceFile]:
+                    with open(file.Path, 'r', errors='replace') as f:
+                        lines = f.readlines()
+                        for line in lines:
+                            if re.search(rf'^\s*module\s+{name}(\s+|\(|;|$)', line):
+                                print(file.Path)
+                                if file.Library.Name == lib:
+                                    logger.info(f"Cocotb dut '{self.dut}' is Verilog")
+                                    return VerilogSourceFile
+                                else:
+                                    logger.warning(f"Found HDL module {name} in ",
+                                                   f"library '{file.Library.Name}' expected '{lib}'")
+                else:
+                    continue
+        except UnicodeDecodeError:
+            logger.warning(f"Can't decode {file.Path}")
+        raise FlowError(f"Could not find HDL entity/module '{name}' in library '{lib}'")
+
+    def is_python_module(self, name: str):
+        # TODO: Should we also search in installed packages?
+        if [f for f in self.files() if f.Path.stem == name]:
+            return True
+
+    def files(self):
+        return self.project.DefaultDesign.Files(CocotbPythonFile)
+
+    @property
+    def enabled(self) -> bool:
+        for file in self.files():
+            return True
+        return False
+
+    @property
+    def pythonpath(self) -> str:
+        directories = {str(f.Path.parent.absolute()) for f in self.files()}
+        return ':'.join(directories)

simplhdl-0.0.6/src/simplhdl/flows/quartusdse/quartusdseflow.py

@@ -0,0 +1,82 @@
+import shutil
+import logging
+
+from argparse import Namespace
+from pathlib import Path
+
+from simplhdl.flow import FlowFactory, FlowTools
+from simplhdl.flows.implementationflow import ImplementationFlow
+from simplhdl.flows.quartusflow import QuartusFlow
+from simplhdl.resources.templates import quartus as templates
+from simplhdl.utils import sh
+from simplhdl.pyedaa.project import Project
+
+logger = logging.getLogger(__name__)
+
+
+@FlowFactory.register('quartus-dse')
+class QuartusDseFlow(ImplementationFlow):
+
+    @classmethod
+    def parse_args(self, subparsers) -> None:
+        parser = subparsers.add_parser('quartus-dse', help='Quartus Design Space Explore Flow')
+        parser.add_argument(
+            '--gui',
+            action='store_true',
+            help="Open project in Quartus GUI"
+        )
+        parser.add_argument(
+            '--dse-args',
+            default='',
+            action='store',
+            metavar='ARGS',
+            help="Extra arguments for Quartus Design Space Explore command"
+        )
+        parser.add_argument(
+            '--dse-file',
+            action='store',
+            metavar='FILE',
+            help="The .dse configuration file to be used for this project"
+        )
+        parser.add_argument(
+            '--num-seeds',
+            action='store',
+            help="Number of seeds to sweep as part of the exploration space. "
+                 + "DSE auto-generates seed values when this is provided"
+        )
+
+    def __init__(self, name, args: Namespace, project: Project, builddir: Path):
+        super().__init__(name, args, project, builddir)
+        self.templates = templates
+        self.tools.add(FlowTools.QUARTUS)
+
+    def run(self) -> None:
+        quartus = QuartusFlow('quartus', None, self.project, self.builddir)
+        quartus.validate()
+        quartus.configure()
+        quartus.generate()
+        self.execute()
+
+    def execute(self):
+        name = self.project.Name
+        if self.args.gui:
+            sh(['quartus_dsew', name], cwd=self.builddir)
+            return
+        args = self.args.dse_args
+        if self.args.num_seeds:
+            args += f" --num-seeds {self.args.num_seeds}"
+        if self.args.dse_file:
+            args += f" --use-dse-file {self.args.dse_file}"
+        command = f"quartus_dse {args} {name}".split()
+        sh(command, cwd=self.builddir, output=True)
+
+    def is_tool_setup(self) -> None:
+        exit: bool = False
+        if shutil.which('quartus_sh') is None:
+            logger.error('quartus_sh: not found in PATH')
+            exit = True
+        if shutil.which('quartus') is None:
+            logger.error('quartus: not found in PATH')
+            exit = True
+        if exit:
+            raise FileNotFoundError("Quartus is not setup correctly")

{SimplHDL-0.0.4 → simplhdl-0.0.6}/src/simplhdl/flows/questasim/questasimflow.py

@@ -3,12 +3,12 @@ import logging
 import shutil
 
 from pathlib import Path
-from typing import Any, List, Dict
+from typing import Any, List, Dict, Optional
 from argparse import Namespace
 from jinja2 import Template
 from simplhdl.pyedaa.project import Project
 from simplhdl.pyedaa.fileset import FileSet
-from simplhdl.utils import sh
+from simplhdl.utils import sh, escape
 from simplhdl.flow import FlowFactory, FlowTools
 from simplhdl.resources.templates import questasim as questasimtemplates
 from simplhdl.flows.simulationflow import SimulationFlow
@@ -25,7 +25,7 @@ class QuestaSimFlow(SimulationFlow):
         parser.add_argument(
             '--step',
             action='store',
-            choices=['compile', 'elaborate', 'simulate'],
+            choices=['generate', 'compile', 'elaborate', 'simulate'],
             default='simulate',
             help="flow step to run"
         )
@@ -116,7 +116,8 @@ class QuestaSimFlow(SimulationFlow):
     def get_project_templates(self, environment) -> List[Template]:
         return [
             environment.get_template('Makefile.j2'),
-            environment.get_template('project.mk.j2')
+            environment.get_template('project.mk.j2'),
+            environment.get_template('gui.do.j2')
         ]
 
     def get_cocotb_templates(self, environment):
@@ -143,10 +144,8 @@ class QuestaSimFlow(SimulationFlow):
         args = set()
         if self.args.verbose == 0:
             args.add('-quiet')
-        for name in self.get_libraries().keys():
-            args.add(f"-L {name}")
         for name, value in self.project.Defines.items():
-            args.add(f"+define+{name}={value}")
+            args.add(f"+define+{name}={escape(value)}")
         return ' '.join(list(args) + [self.args.vlog_args])
 
     def vcom_args(self) -> str:
@@ -168,20 +167,23 @@ class QuestaSimFlow(SimulationFlow):
         if self.args.timescale:
             args.add(f"-timescale {self.args.timescale}")
         for name, value in self.project.Generics.items():
-            args.add(f"-g{name}={value}")
+            args.add(f"-g{name}={escape(value)}")
         for name, value in self.project.Parameters.items():
-            args.add(f"-g{name}={value}")
-        if self.args.gui or self.cocotb.enabled:
+            args.add(f"-g{name}={escape(value)}")
+        if self.args.gui or self.args.do or self.args.wave or self.cocotb.enabled:
             args.add('+acc=npr')
         return ' '.join(list(args) + [self.args.vopt_args])
 
     def vsim_args(self) -> str:
         args = set()
         args.add(f"-sv_seed {self.args.seed}")
+        timescale = self.timescale()
+        if timescale:
+            args.add(timescale)
         if self.args.verbose == 0:
             args.add('-quiet')
         for name, value in self.project.PlusArgs.items():
-            args.add(f"+{name}={value}")
+            args.add(f"+{name}={escape(value)}")
         if self.args.gui:
             args.add('-onfinish final')
         else:
@@ -201,8 +203,12 @@ class QuestaSimFlow(SimulationFlow):
 
     def execute(self, step: str) -> None:
         self.run_hooks('pre')
-        sh(['make', 'compile'], cwd=self.builddir, output=True)
+
+        if step == 'generate':
+            return
+
         if step == 'compile':
+            sh(['make', 'compile'], cwd=self.builddir, output=True)
             return
 
         if self.args.do:
@@ -228,6 +234,16 @@ class QuestaSimFlow(SimulationFlow):
             # NOTE: Continue if no hook is registret
             pass
 
+    def timescale(self) -> Optional[str]:
+        """
+        Sets the timescale for VHDL based on the Verilog timescale
+        resolution.
+        """
+        if self.args.timescale.endswith('ps'):
+            return "-t ps"
+        elif self.args.timescale.endswith('fs'):
+            return "-t fs"
+
     def is_tool_setup(self) -> None:
         if (shutil.which('vlog') is None or
                 shutil.which('vsim') is None or

{SimplHDL-0.0.4 → simplhdl-0.0.6}/src/simplhdl/flows/rivierapro/rivieraproflow.py

@@ -8,7 +8,7 @@ from argparse import Namespace
 from jinja2 import Template
 from simplhdl.pyedaa.project import Project
 from simplhdl.pyedaa.fileset import FileSet
-from simplhdl.utils import sh
+from simplhdl.utils import sh, escape
 from simplhdl.flow import FlowFactory, FlowTools
 from simplhdl.resources.templates import rivierapro as rivieraprotemplates
 from simplhdl.flows.simulationflow import SimulationFlow
@@ -150,7 +150,7 @@ class RivieraProFlow(SimulationFlow):
         if self.args.gui:
             args.add('-dbg')
         for name, value in self.project.Defines.items():
-            args.add(f"+define+{name}={value}")
+            args.add(f"+define+{name}={escape(value)}")
         return ' '.join(list(args) + [self.args.vlog_args])
 
     def vcom_args(self) -> str:
@@ -175,11 +175,11 @@ class RivieraProFlow(SimulationFlow):
         for name in self.get_libraries().keys():
             args.add(f"-L {name}")
         for name, value in self.project.Generics.items():
-            args.add(f"-g{name}={value}")
+            args.add(f"-g{name}={escape(value)}")
         for name, value in self.project.Parameters.items():
-            args.add(f"-g{name}={value}")
+            args.add(f"-g{name}={escape(value)}")
         for name, value in self.project.PlusArgs.items():
-            args.add(f"+{name}={value}")
+            args.add(f"+{name}={escape(value)}")
         if self.args.gui:
             args.add('-dbg +access +r')
         if self.cocotb.enabled:

{SimplHDL-0.0.4 → simplhdl-0.0.6}/src/simplhdl/flows/simulationflow.py

@@ -56,9 +56,13 @@ class SimulationFlow(FlowBase):
         globals['libraries'] = (list(self.project.DefaultDesign.VHDLLibraries.values()))
         globals['external_libraries'] = list(self.project.DefaultDesign.ExternalVHDLLibraries.values())
         globals['defaultlib'] = 'work'
-        globals['toplevels'] = ' '.join(
-            [t for t in self.project.DefaultDesign.TopLevel.split() if t != self.cocotb.module()])
+        globals['toplevels'] = self.cocotb.toplevels
         globals['pythonpath'] = self.cocotb.pythonpath
+        globals['cocotbtop'] = self.cocotb.top
+        globals['cocotbhdltype'] = self.cocotb.duttype
+        globals['cocotbdut'] = self.cocotb.dut
+        globals['VerilogSourceFile'] = VerilogSourceFile
+        globals['VHDLSourceFile'] = VHDLSourceFile
         globals['uvm'] = self.is_uvm()
         return globals
 
@@ -97,7 +101,7 @@ class SimulationFlow(FlowBase):
             name = md5sum(fileset.Name)
             dependencies = []
             for language_fileset in [f for f in filelist if f.stem.startswith(name)]:
-                for child in fileset.FileSets.values():
+                for child in fileset.Dependencies(usedin='simulation'):
                     child_name = md5sum(child.Name)
                     dependencies += [append_suffix(f, '.com').name for f in filelist
                                      if f.stem.startswith(child_name)]

{SimplHDL-0.0.4 → simplhdl-0.0.6}/src/simplhdl/flows/vcs/vcsflow.py

@@ -3,12 +3,13 @@ import os
 import logging
 from pathlib import Path
 import shutil
+import re
 
 from typing import Dict, Any, List
 from jinja2 import Template
 from simplhdl.pyedaa.fileset import FileSet
 from simplhdl.pyedaa.project import Project
-from simplhdl.utils import sh
+from simplhdl.utils import sh, escape
 from simplhdl.flow import FlowFactory, FlowTools
 from simplhdl.resources.templates import vcs as vcstemplates
 from ..simulationflow import SimulationFlow
@@ -95,13 +96,34 @@ class VcsFlow(SimulationFlow):
         globals['vhdlan_args'] = self.vhdlan_args()
         globals['vcs_args'] = self.vcs_args()
         globals['simv_args'] = self.simv_args()
+        globals['parameters'] = {**self.project.Generics, **self.project.Parameters}
+        globals['format'] = self.format
         return globals
 
+    def format(self, value: str) -> str:
+        """
+        Format the parameter value in relation to it's type.
+        """
+        isformat_a = re.compile(r"^\d+#[0-9a-gA-G]+#")
+        isformat_b = re.compile(r"^\d*'(h|d|b)[0-9a-fA-F]+")
+        isformat_c = re.compile(r"^\d+\.\d+")
+
+        if (
+            value.isnumeric() or
+            isformat_a.match(value) or
+            isformat_b.match(value) or
+            isformat_c.match(value)
+        ):
+            return value
+        else:
+            return f'"{value}"'
+
     def get_project_templates(self, environment) -> List[Template]:
         return [
             environment.get_template('Makefile.j2'),
             environment.get_template('synopsys_sim.setup.j2'),
-            environment.get_template('project.mk.j2')
+            environment.get_template('project.mk.j2'),
+            environment.get_template('vcs.parameters.j2'),
         ]
 
     def get_cocotb_templates(self, environment):
@@ -128,7 +150,7 @@ class VcsFlow(SimulationFlow):
     def vlogan_args(self) -> str:
         args = set()
         for name, value in self.project.Defines.items():
-            args.add(f"+define+{name}={value}")
+            args.add(f"+define+{name}={escape(value)}")
         if self.args.verbose == 0:
             args.add('-q')
         elif self.args.verbose > 1:
@@ -161,10 +183,10 @@ class VcsFlow(SimulationFlow):
             args.add('-debug_access+all')
             if self.is_verdi():
                 args.add('-kdb')
-        for name, value in self.project.Generics.items():
-            args.add(f"-pvalue+{name}={value}")
-        for name, value in self.project.Parameters.items():
-            args.add(f"-pvalue+{name}={value}")
+        parameters = {**self.project.Generics, **self.project.Parameters}
+        if parameters:
+            args.add('-gfile vcs.parameters -lca')
+
         return ' '.join(list(args) + [self.args.vcs_args])
 
     def simv_args(self) -> str:
@@ -172,7 +194,7 @@ class VcsFlow(SimulationFlow):
         if self.args.seed != '1':
             args.add(f"+ntb_random_seed={self.args.seed}")
         for name, value in self.project.PlusArgs.items():
-            args.add(f"+{name}={value}")
+            args.add(f"+{name}={escape(value)}")
         return ' '.join(list(args) + [self.args.simv_args])
 
     def get_library(self, fileset: FileSet) -> str:

simplhdl-0.0.6/src/simplhdl/flows/verible/veribleflow.py

@@ -0,0 +1,92 @@
+try:
+    from importlib.resources import files as resources_files
+except ImportError:
+    from importlib_resources import files as resources_files
+import os
+import logging
+from argparse import Namespace
+from pathlib import Path
+from jinja2 import Environment, FileSystemLoader
+
+from simplhdl.flow import FlowFactory, FlowBase
+from simplhdl.resources.templates import verible as templates
+from simplhdl.utils import sh, CalledShError, generate_from_template
+from simplhdl.pyedaa import VerilogIncludeFile, VerilogSourceFile, SystemVerilogSourceFile
+from simplhdl.pyedaa.project import Project
+
+logger = logging.getLogger(__name__)
+
+
+@FlowFactory.register('verible-verilog-lint')
+class VeribleFlow(FlowBase):
+
+    @classmethod
+    def parse_args(self, subparsers) -> None:
+        parser = subparsers.add_parser('verible-verilog-lint', help='Verible Lint Flow')
+        # parser.add_argument(
+        #     '--fix',
+        #     action='store_true',
+        #     help="Fix style formatting (Note: this modifies the source)"
+        # )
+        parser.add_argument(
+            '-r', '--rules',
+            action='store',
+            help="Rule configuration file"
+        )
+        parser.add_argument(
+            '-f', '--files',
+            type=lambda p: Path(p).absolute(),
+            nargs='+',
+            default=[],
+            help="Manually specify file list"
+        )
+
+    def __init__(self, name, args: Namespace, project: Project, builddir: Path):
+        super().__init__(name, args, project, builddir)
+        self.templates = templates
+
+    def setup(self):
+        os.makedirs(self.builddir, exist_ok=True)
+
+    def generate(self):
+        templatedir = resources_files(self.templates)
+        environment = Environment(
+            loader=FileSystemLoader(templatedir),
+            trim_blocks=True)
+        template = environment.get_template('rules.cfg.j2')
+        generate_from_template(template, self.builddir)
+
+    def execute(self):
+        errors = False
+        command = ["verible-verilog-lint"]
+        if self.args.rules:
+            rules = self.args.rules
+        elif os.getenv('SIMPLHDL_VERIBLE_RULES'):
+            rules = self.args.rules
+        else:
+            rules = 'rules.cfg'
+
+        command += f"--check_syntax=false --rules_config {rules}".split()
+
+        # if self.args.fix:
+        #     command.append("--fix")
+        # else:
+        #     command += f"-ap -of {self.args.output_format}".split()
+
+        file_types = [VerilogIncludeFile, VerilogSourceFile, SystemVerilogSourceFile]
+        files = [f for f in self.project.DefaultDesign.Files() if f.FileType in file_types]
+        for file in files:
+            try:
+                cmd = command + [str(file.Path)]
+                sh(cmd, cwd=self.builddir, output=True)
+            except CalledShError as e:
+                errors = True
+                print(e)
+
+        if errors:
+            return SystemError
+
+    def run(self) -> None:
+        self.setup()
+        self.generate()
+        self.execute()