SimplHDL 0.0.3__tar.gz → 0.0.5__tar.gz

{SimplHDL-0.0.3 → simplhdl-0.0.5}/PKG-INFO

@@ -1,6 +1,6 @@
 Metadata-Version: 2.1
 Name: SimplHDL
-Version: 0.0.3
+Version: 0.0.5
 Summary: A framework for simulating and implementing HDL designs
 Author-email: Rasmus Grøndahl Olsen <simplhdl@gmail.com>
 Maintainer-email: Rasmus Grøndahl Olsen <simplhdl@gmail.com>
@@ -51,6 +51,7 @@ Requires-Dist: types-PyYAML
 Requires-Dist: argcomplete
 Requires-Dist: jinja2
 Requires-Dist: GitPython
+Requires-Dist: rich
 
 ## Introduction
 

{SimplHDL-0.0.3 → simplhdl-0.0.5}/pyproject.toml

@@ -20,6 +20,7 @@ dependencies = [
     "argcomplete",
     "jinja2",
     "GitPython",
+    "rich",
 ]
 requires-python = ">=3.8"
 authors = [

{SimplHDL-0.0.3 → simplhdl-0.0.5}/src/SimplHDL.egg-info/PKG-INFO

@@ -1,6 +1,6 @@
 Metadata-Version: 2.1
 Name: SimplHDL
-Version: 0.0.3
+Version: 0.0.5
 Summary: A framework for simulating and implementing HDL designs
 Author-email: Rasmus Grøndahl Olsen <simplhdl@gmail.com>
 Maintainer-email: Rasmus Grøndahl Olsen <simplhdl@gmail.com>
@@ -51,6 +51,7 @@ Requires-Dist: types-PyYAML
 Requires-Dist: argcomplete
 Requires-Dist: jinja2
 Requires-Dist: GitPython
+Requires-Dist: rich
 
 ## Introduction
 

{SimplHDL-0.0.3 → simplhdl-0.0.5}/src/SimplHDL.egg-info/SOURCES.txt

@@ -154,6 +154,7 @@ src/simplhdl/resources/templates/vcs/fileset.j2
 src/simplhdl/resources/templates/vcs/pli.tab.j2
 src/simplhdl/resources/templates/vcs/project.mk.j2
 src/simplhdl/resources/templates/vcs/synopsys_sim.setup.j2
+src/simplhdl/resources/templates/vcs/vcs.parameters.j2
 src/simplhdl/resources/templates/vivado/__init__.py
 src/simplhdl/resources/templates/vivado/launch_run.sh.j2
 src/simplhdl/resources/templates/vivado/project.tcl.j2

{SimplHDL-0.0.3 → simplhdl-0.0.5}/src/SimplHDL.egg-info/requires.txt

@@ -5,6 +5,7 @@ types-PyYAML
 argcomplete
 jinja2
 GitPython
+rich
 
 [:python_version < "3.9"]
 importlib-resources

simplhdl-0.0.5/src/simplhdl/__init__.py

@@ -0,0 +1 @@
+__version__ = "0.0.5"

{SimplHDL-0.0.3 → simplhdl-0.0.5}/src/simplhdl/flows/quartusflow.py

@@ -16,7 +16,8 @@ from ..resources.templates import quartus as templates
 from ..utils import sh, generate_from_template
 from ..pyedaa import (QuartusIPSpecificationFile, VerilogIncludeFile, VerilogSourceFile,
                       SystemVerilogSourceFile, VHDLSourceFile, ConstraintFile,
-                      EDIFNetlistFile, NetlistFile, SettingFile, QuartusSignalTapFile)
+                      EDIFNetlistFile, NetlistFile, SettingFile, QuartusSignalTapFile,
+                      QuartusIniFile, QuartusQIPSpecificationFile, QuartusQSYSSpecificationFile)
 from ..pyedaa.project import Project
 from ..pyedaa.attributes import UsedIn
 
@@ -94,6 +95,9 @@ class QuartusFlow(ImplementationFlow):
             NetlistFile=NetlistFile,
             SettingFile=SettingFile,
             QuartusSignalTapFile=QuartusSignalTapFile,
+            QuartusQIPSpecificationFile=QuartusQIPSpecificationFile,
+            QuartusQSYSSpecificationFile=QuartusQSYSSpecificationFile,
+            QuartusIniFile=QuartusIniFile,
             project=self.project,
             UsedIn=UsedIn)
         template = environment.get_template('run.tcl.j2')

{SimplHDL-0.0.3 → simplhdl-0.0.5}/src/simplhdl/flows/questasim/questasimflow.py

@@ -3,7 +3,7 @@ import logging
 import shutil
 
 from pathlib import Path
-from typing import Any, List, Dict
+from typing import Any, List, Dict, Optional
 from argparse import Namespace
 from jinja2 import Template
 from simplhdl.pyedaa.project import Project
@@ -143,8 +143,6 @@ class QuestaSimFlow(SimulationFlow):
         args = set()
         if self.args.verbose == 0:
             args.add('-quiet')
-        for name in self.get_libraries().keys():
-            args.add(f"-L {name}")
         for name, value in self.project.Defines.items():
             args.add(f"+define+{name}={value}")
         return ' '.join(list(args) + [self.args.vlog_args])
@@ -171,13 +169,16 @@ class QuestaSimFlow(SimulationFlow):
             args.add(f"-g{name}={value}")
         for name, value in self.project.Parameters.items():
             args.add(f"-g{name}={value}")
-        if self.args.gui or self.cocotb.enabled:
+        if self.args.gui or self.args.do or self.args.wave or self.cocotb.enabled:
             args.add('+acc=npr')
         return ' '.join(list(args) + [self.args.vopt_args])
 
     def vsim_args(self) -> str:
         args = set()
         args.add(f"-sv_seed {self.args.seed}")
+        timescale = self.timescale()
+        if timescale:
+            args.add(timescale)
         if self.args.verbose == 0:
             args.add('-quiet')
         for name, value in self.project.PlusArgs.items():
@@ -228,6 +229,16 @@ class QuestaSimFlow(SimulationFlow):
             # NOTE: Continue if no hook is registret
             pass
 
+    def timescale(self) -> Optional[str]:
+        """
+        Sets the timescale for VHDL based on the Verilog timescale
+        resolution.
+        """
+        if self.args.timescale.endswith('ps'):
+            return "-t ps"
+        elif self.args.timescale.endswith('fs'):
+            return "-t fs"
+
     def is_tool_setup(self) -> None:
         if (shutil.which('vlog') is None or
                 shutil.which('vsim') is None or

{SimplHDL-0.0.3 → simplhdl-0.0.5}/src/simplhdl/flows/simulationflow.py

@@ -97,7 +97,7 @@ class SimulationFlow(FlowBase):
             name = md5sum(fileset.Name)
             dependencies = []
             for language_fileset in [f for f in filelist if f.stem.startswith(name)]:
-                for child in fileset.FileSets.values():
+                for child in fileset.Dependencies(usedin='simulation'):
                     child_name = md5sum(child.Name)
                     dependencies += [append_suffix(f, '.com').name for f in filelist
                                      if f.stem.startswith(child_name)]

{SimplHDL-0.0.3 → simplhdl-0.0.5}/src/simplhdl/flows/vcs/vcsflow.py

@@ -3,6 +3,7 @@ import os
 import logging
 from pathlib import Path
 import shutil
+import re
 
 from typing import Dict, Any, List
 from jinja2 import Template
@@ -95,13 +96,34 @@ class VcsFlow(SimulationFlow):
         globals['vhdlan_args'] = self.vhdlan_args()
         globals['vcs_args'] = self.vcs_args()
         globals['simv_args'] = self.simv_args()
+        globals['parameters'] = {**self.project.Generics, **self.project.Parameters}
+        globals['format'] = self.format
         return globals
 
+    def format(self, value: str) -> str:
+        """
+        Format the parameter value in relation to it's type.
+        """
+        isformat_a = re.compile(r"^\d+#[0-9a-gA-G]+#")
+        isformat_b = re.compile(r"^\d*'(h|d|b)[0-9a-fA-F]+")
+        isformat_c = re.compile(r"^\d+\.\d+")
+
+        if (
+            value.isnumeric() or
+            isformat_a.match(value) or
+            isformat_b.match(value) or
+            isformat_c.match(value)
+        ):
+            return value
+        else:
+            return f'"{value}"'
+
     def get_project_templates(self, environment) -> List[Template]:
         return [
             environment.get_template('Makefile.j2'),
             environment.get_template('synopsys_sim.setup.j2'),
-            environment.get_template('project.mk.j2')
+            environment.get_template('project.mk.j2'),
+            environment.get_template('vcs.parameters.j2'),
         ]
 
     def get_cocotb_templates(self, environment):
@@ -161,10 +183,10 @@ class VcsFlow(SimulationFlow):
             args.add('-debug_access+all')
             if self.is_verdi():
                 args.add('-kdb')
-        for name, value in self.project.Generics.items():
-            args.add(f"-pvalue+{name}={value}")
-        for name, value in self.project.Parameters.items():
-            args.add(f"-pvalue+{name}={value}")
+        parameters = {**self.project.Generics, **self.project.Parameters}
+        if parameters:
+            args.add('-gfile vcs.parameters -lca')
+
         return ' '.join(list(args) + [self.args.vcs_args])
 
     def simv_args(self) -> str:

{SimplHDL-0.0.3 → simplhdl-0.0.5}/src/simplhdl/generators/spd.py

@@ -10,7 +10,8 @@ from shutil import copy, copytree
 
 from ..pyedaa import (
     File, SystemVerilogSourceFile, VHDLSourceFile, VerilogSourceFile,
-    QuartusIPSpecificationFile, HDLLibrary, ConstraintFile, HDLSourceFile
+    QuartusIPSpecificationFile, HDLLibrary, ConstraintFile, HDLSourceFile,
+    QuartusIPCompressedSpecificationFile, QuartusQSYSSpecificationFile
 )
 from ..pyedaa.fileset import FileSet
 from ..flow import FlowBase, FlowCategory, FlowTools
@@ -111,14 +112,15 @@ class Spd:
 @GeneratorFactory.register('QuartusIP')
 class QuartusIP(GeneratorBase):
 
-    def unpack_ip(self, filename: QuartusIPSpecificationFile) -> QuartusIPSpecificationFile:
+    def unpack_ip(self, filename: QuartusIPSpecificationFile) -> QuartusIPSpecificationFile:  # noqa: C901
         ipdir = self.builddir.joinpath('ips')
         dest = ipdir.joinpath(filename.Path.name).with_suffix('')
         md5file = dest.with_suffix('.md5')
         ipdir.mkdir(exist_ok=True)
-        if filename.Path.suffix == '.qsys':
-            return
-        elif filename.Path.suffix == '.zip':
+        if filename.FileType == QuartusQSYSSpecificationFile:
+            pass
+
+        elif filename.FileType == QuartusIPCompressedSpecificationFile:
             update = True
             if md5file.exists():
                 update = not md5check(filename.Path, filename=md5file)
@@ -127,7 +129,14 @@ class QuartusIP(GeneratorBase):
                     zip.extractall(ipdir)
                 md5write(filename.Path, filename=md5file)
                 logger.debug(f"Copy {filename.Path} to {dest}")
-        elif filename.Path.suffix == '.ip':
+
+            if filename.Path.suffix == '.zip':
+                filename._path = dest.absolute()
+            else:
+                filename._path = dest.with_suffix('.ip').absolute()
+            filename._fileType = QuartusIPSpecificationFile
+
+        elif filename.FileType == QuartusIPSpecificationFile:
             update = True
             dir = filename.Path.with_suffix('')
             if dir.exists():
@@ -140,10 +149,8 @@ class QuartusIP(GeneratorBase):
                     copytree(str(dir), str(dest.with_suffix('')), dirs_exist_ok=True)
                     md5write(filename.Path, dir, filename=md5file)
                     logger.debug(f"Copy {filename.Path} to {dest}")
-        else:
-            # Non Qartus IP files
-            return filename
-        filename._path = dest.absolute()
+            filename._path = dest.with_suffix('.ip').absolute()
+
         return filename
 
     def run(self, flow: FlowBase):

{SimplHDL-0.0.3 → simplhdl-0.0.5}/src/simplhdl/info.py

@@ -1,3 +1,10 @@
+from argparse import Namespace
+from pathlib import Path
+from rich.console import Console
+from rich.tree import Tree
+from rich.style import Style
+
+from simplhdl.pyedaa.project import Project
 from .flow import FlowBase, FlowFactory
 from .pyedaa.attributes import UsedIn
 from .pyedaa.fileset import FileSet
@@ -6,6 +13,16 @@ from .pyedaa.fileset import FileSet
 @FlowFactory.register('info')
 class Info(FlowBase):
 
+    def __init__(self, name, args: Namespace, project: Project, builddir: Path):
+        super().__init__(name, args, project, builddir)
+        self.console = Console()
+        self.style = {
+            'fileset': Style(color="color(4)", reverse=True),
+            'ifile': Style(color="color(2)", reverse=False),
+            'sfile': Style(color="color(3)", reverse=False),
+            'file': Style(color="default", reverse=False),
+        }
+
     @classmethod
     def parse_args(self, subparsers) -> None:
         parser = subparsers.add_parser('info', help='Project infomations')
@@ -48,90 +65,98 @@ class Info(FlowBase):
             self.print_info()
 
     def print_files(self) -> None:
-        print('FILES:')
+        self.console.print('FILES:')
         for file in self.project.DefaultDesign.Files():
-            print(f"{file.Path}")
+            self.console.print(f"{file.Path}")
 
-    def print_fileset(self, fileset: FileSet, level: int) -> None:
-        indent = ' '*level
-        print(f"{indent}{fileset.Name}")
+    def print_fileset(self, fileset: FileSet, level: Tree) -> None:
+        # indent = ' '*level
+        tree = level.add(f"[bold]{fileset.Name}[/bold] ({fileset.VHDLLibrary})", style=self.style['fileset'])
         for file in fileset.GetFiles():
-            print(f"{indent}    - {file.Path} {file[UsedIn]}")
+            if "implementation" in file[UsedIn] and "simulation" not in file[UsedIn]:
+                style = self.style['ifile']
+            elif "simulation" in file[UsedIn] and "implementation" not in file[UsedIn]:
+                style = self.style['sfile']
+            else:
+                style = self.style['file']
+
+            tree.add(f"{file.Path}", style=style)
         for child_filset in fileset.FileSets.values():
-            self.print_fileset(child_filset, level+2)
+            self.print_fileset(child_filset, tree)
 
     def print_filesets(self) -> None:
-        print('FILESETS:')
+        tree = Tree('FILESETS:')
         for fileset in self.project.DefaultDesign.FileSets.values():
-            self.print_fileset(fileset, level=0)
+            self.print_fileset(fileset, tree)
+        self.console.print(tree)
 
     def print_hooks(self) -> None:
-        print('HOOKS:')
+        self.console.print('HOOKS:')
         for name, value in self.project.Hooks.items():
-            print(f"  - {name}: {value}")
+            self.console.print(f"  - {name}: {value}")
 
     def print_libraries(self) -> None:
-        print('LIBRARIES:')
+        self.console.print('LIBRARIES:')
         for library in self.project.DefaultDesign.VHDLLibraries.values():
-            print(f"  - {library.Name}")
+            self.console.print(f"  - {library.Name}")
 
     def print_parameters(self) -> None:
-        print('PARAMETERS')
+        self.console.print('PARAMETERS')
         for name, value in self.project.Parameters.items():
-            print(f"  - {name}: {value}")
+            self.console.print(f"  - {name}: {value}")
 
     def print_generics(self) -> None:
-        print('GENERICS')
+        self.console.print('GENERICS')
         for name, value in self.project.Generics.items():
-            print(f"  - {name}: {value}")
+            self.console.print(f"  - {name}: {value}")
 
     def print_defines(self) -> None:
-        print('DEFINES')
+        self.console.print('DEFINES')
         for name, value in self.project.Defines.items():
-            print(f"  - {name}: {value}")
+            self.console.print(f"  - {name}: {value}")
 
     def print_plusargs(self) -> None:
-        print('PLUSARGS')
+        self.console.print('PLUSARGS')
         for name, value in self.project.PlusArgs.items():
-            print(f"  - {name}: {value}")
+            self.console.print(f"  - {name}: {value}")
 
     def print_toplevels(self) -> None:
-        print('TOPLEVELS')
+        self.console.print('TOPLEVELS')
         for top in self.project.DefaultDesign.TopLevel.split():
-            print(f"  - {top}")
+            self.console.print(f"  - {top}")
 
     def print_resources(self) -> None:
-        print('RESOURCES')
+        self.console.print('RESOURCES')
         for resource in self.project.DefaultDesign.ExternalVHDLLibraries.values():
-            print(f"  - {resource.Name}: {resource.Path}")
+            self.console.print(f"  - {resource.Name}: {resource.Path}")
 
     def print_project(self) -> None:
-        print('PROJECTNAME')
-        print(f"  - {self.project.Name}")
+        self.console.print('PROJECTNAME')
+        self.console.print(f"  - {self.project.Name}")
 
     def print_part(self) -> None:
-        print('PART')
-        print(f"  - {self.project.Part}")
+        self.console.print('PART')
+        self.console.print(f"  - {self.project.Part}")
 
     def print_info(self) -> None:
         self.print_project()
-        print()
+        self.console.print()
         self.print_part()
-        print()
+        self.console.print()
         self.print_toplevels()
-        print()
+        self.console.print()
         self.print_plusargs()
-        print()
+        self.console.print()
         self.print_defines()
-        print()
+        self.console.print()
         self.print_parameters()
-        print()
+        self.console.print()
         self.print_generics()
-        print()
+        self.console.print()
         self.print_hooks()
-        print()
+        self.console.print()
         self.print_resources()
-        print()
+        self.console.print()
         self.print_libraries()
-        print()
+        self.console.print()
         self.print_filesets()

{SimplHDL-0.0.3 → simplhdl-0.0.5}/src/simplhdl/pyedaa/__init__.py

@@ -47,7 +47,10 @@ class HDLSourceFile(pm.HDLSourceFile, FileMixIn):
 
     @property
     def Library(self) -> HDLLibrary:
-        return self._library
+        if self._library is not None:
+            return self._library
+        elif self.FileSet.VHDLLibrary is not None:
+            return self.FileSet.VHDLLibrary
 
     @Library.setter
     def Library(self, value) -> None:
@@ -128,6 +131,25 @@ class QuartusIPSpecificationFile(IPSpecificationFile):
     pass
 
 
+class QuartusIPCompressedSpecificationFile(QuartusIPSpecificationFile):
+    pass
+
+
+class QuartusQSYSSpecificationFile(QuartusIPSpecificationFile):
+    pass
+
+
+class QuartusQIPSpecificationFile(QuartusIPSpecificationFile):
+    pass
+
+
+class QuartusIniFile(File):
+    def _registerAttributes(self):
+        super()._registerAttributes()
+        FileMixIn._registerAttributes(self)
+        self[UsedIn] = {'implementation'}
+
+
 class VivadoIPSpecificationFile(IPSpecificationFile):
     pass
 

{SimplHDL-0.0.3 → simplhdl-0.0.5}/src/simplhdl/pyedaa/fileset.py

@@ -1,6 +1,8 @@
 import pyEDAA.ProjectModel as pm  # type: ignore
+from simplhdl.pyedaa.attributes import UsedIn
+from simplhdl.pyedaa import File
 
-from typing import Dict, Generator
+from typing import Dict, Generator, List, Optional
 
 
 class FileSet(pm.FileSet):
@@ -31,7 +33,7 @@ class FileSet(pm.FileSet):
     def VHDLLibrary(self, value: 'VHDLLibrary') -> None:
         self._vhdlLibrary = value
 
-    def GetFiles(self) -> Generator[pm.File, None, None]:
+    def GetFiles(self) -> Generator[File, None, None]:
         for file in self._files:
             yield file
 
@@ -44,10 +46,26 @@ class FileSet(pm.FileSet):
             libraries.update(fileset.VHDLLibraries)
         return libraries
 
-    def InsertFile(self, position: int, file: pm.File) -> None:
+    def InsertFile(self, position: int, file: File) -> None:
         # file.FileSet = self
         self._files.insert(position, file)
 
-    def InsertFileAfter(self, listfile: pm.File, newfile: pm.File) -> None:
+    def InsertFileAfter(self, listfile: File, newfile: File) -> None:
         position = self._files.index(listfile)
         self.InsertFile(position, newfile)
+
+    def Dependencies(self, usedin: Optional[str] = None, isrecursive: bool = False) -> List['FileSet']:
+        """
+        Return a list of filesets that this fileset depends on. if dependent fileset is empty search recursive
+        in children until a fileset that is not empty is found.
+        """
+        if isrecursive:
+            files = [f for f in self.GetFiles()]
+            if usedin:
+                files = [f for f in files if usedin in f[UsedIn]]
+            if files:
+                return [self]
+        dependencies = list()
+        for fileset in self.FileSets.values():
+            dependencies += fileset.Dependencies(usedin=usedin, isrecursive=True)
+        return dependencies

{SimplHDL-0.0.3 → simplhdl-0.0.5}/src/simplhdl/resources/templates/quartus/project.tcl.j2

@@ -14,33 +14,26 @@ set_global_assignment -name VERILOG_MACRO "{{define}}={{value}}"
 {% for file in project.DefaultDesign.Files() if 'implementation' in file[UsedIn] %}
 {% if file.FileType == VerilogIncludeFile %}
 set_global_assignment -name VERILOG_INCLUDE_FILE "{{file.Path}}"
-{% endif %}
-{% if file.FileType == SystemVerilogSourceFile %}
+{% elif file.FileType == SystemVerilogSourceFile %}
 set_global_assignment -name SYSTEMVERILOG_FILE "{{file.Path}}"
-{% endif %}
-{% if file.FileType == VerilogSourceFile %}
+{% elif file.FileType == VerilogSourceFile %}
 set_global_assignment -name VERILOG_FILE "{{file.Path}}"
-{% endif %}
-{% if file.FileType == VHDLSourceFile %}
+{% elif file.FileType == VHDLSourceFile %}
 set_global_assignment -name VHDL_FILE "{{file.Path}}"
-{% endif %}
-{% if file.FileType == ConstraintFile %}
+{% elif file.FileType == ConstraintFile %}
 set_global_assignment -name SDC_FILE "{{file.Path}}"
-{% endif %}
-{% if file.FileType == TCLSourceFile %}
+{% elif file.FileType == TCLSourceFile %}
 set_global_assignment -name TCL_FILE "{{file.Path}}"
-{% endif %}
-{% if file.FileType == QuartusIPSpecificationFile and file.Path.suffix == '.ip' %}
+{% elif file.FileType == QuartusIPSpecificationFile %}
 set_global_assignment -name IP_FILE "{{file.Path}}"
-{% endif %}
-{% if file.FileType == QuartusIPSpecificationFile and file.Path.suffix == '.qip' %}
+{% elif file.FileType == QuartusQIPSpecificationFile %}
 set_global_assignment -name QIP_FILE "{{file.Path}}"
-{% endif %}
-{% if file.FileType == QuartusIPSpecificationFile and file.Path.suffix == '.qsys' %}
+{% elif file.FileType == QuartusQSYSSpecificationFile %}
 set_global_assignment -name QSYS_FILE "{{file.Path}}"
-{% endif %}
-{% if file.FileType == SettingFile and file.Path.suffix == '.qsf' %}
+{% elif file.FileType == SettingFile and file.Path.suffix == '.qsf' %}
 source "{{file.Path}}"
+{% elif file.FileType == QuartusIniFile %}
+file copy -force "{{file.Path}}" "quartus.ini"
 {% endif %}
 {% endfor %}
 

{SimplHDL-0.0.3 → simplhdl-0.0.5}/src/simplhdl/resources/templates/questasim/Makefile.j2

@@ -6,11 +6,11 @@ VOPT := vopt
 VSIM := vsim
 
 VLIB_FLAGS :=
-VMAP_FLAGS := {{vmap_args}}
-VCOM_FLAGS := {{vcom_args}}
-VLOG_FLAGS := {{vlog_args}}
-VOPT_FLAGS := {{vopt_args}}
-VSIM_FLAGS := {{vsim_args}}
+VMAP_FLAGS := {{vmap_args|replace('#', '\#')}}
+VCOM_FLAGS := {{vcom_args|replace('#', '\#')}}
+VLOG_FLAGS := {{vlog_args|replace('#', '\#')}}
+VOPT_FLAGS := {{vopt_args|replace('#', '\#')}}
+VSIM_FLAGS := {{vsim_args|replace('#', '\#')}}
 
 VOPT_DESIGN ?= simvopt
 
@@ -29,6 +29,8 @@ endif
 simulate: $(VOPT_DESIGN)
 	$(VSIM) $(VSIM_FLAGS) $< -c $(DO_CMD)
 
+elaborate: $(VOPT_DESIGN)
+
 $(VOPT_DESIGN): compile
 	$(VOPT) $(VOPT_FLAGS) $(TOPLEVELS) -o $@
 

{SimplHDL-0.0.3 → simplhdl-0.0.5}/src/simplhdl/resources/templates/rivierapro/Makefile.j2

@@ -7,11 +7,11 @@ VOPT := :
 VSIM := vsim
 
 VLIB_FLAGS :=
-VMAP_FLAGS := {{vmap_args}}
-VCOM_FLAGS := {{vcom_args}}
-VLOG_FLAGS := {{vlog_args}}
-VOPT_FLAGS := {{vopt_args}}
-VSIM_FLAGS := {{vsim_args}}
+VMAP_FLAGS := {{vmap_args|replace('#', '\#')}}
+VCOM_FLAGS := {{vcom_args|replace('#', '\#')}}
+VLOG_FLAGS := {{vlog_args|replace('#', '\#')}}
+VOPT_FLAGS := {{vopt_args|replace('#', '\#')}}
+VSIM_FLAGS := {{vsim_args|replace('#', '\#')}}
 
 VOPT_DESIGN ?= simvopt
 

{SimplHDL-0.0.3 → simplhdl-0.0.5}/src/simplhdl/resources/templates/vcs/Makefile.j2

@@ -8,10 +8,10 @@ UVM := uvm.com
 UVM :=
 {% endif %}
 
-VLOGAN_FLAGS := -full64 +warn=noLNX_OS_VERUN {{vlogan_args}}
-VHDLAN_FLAGS := -full64 {{vhdlan_args}}
-VCS_FLAGS := -full64 -licqueue +warn=noLINX_KRNL {{vcs_args}}
-SIMV_FLAGS := -licqueue {{simv_args}}
+VLOGAN_FLAGS := -full64 +warn=noLNX_OS_VERUN {{vlogan_args|replace('#', '\#')}}
+VHDLAN_FLAGS := -full64 {{vhdlan_args|replace('#', '\#')}}
+VCS_FLAGS := -full64 -licqueue +warn=noLINX_KRNL {{vcs_args|replace('#', '\#')}}
+SIMV_FLAGS := -licqueue {{simv_args|replace('#', '\#')}}
 
 include project.mk
 -include cocotb.mk

simplhdl-0.0.5/src/simplhdl/resources/templates/vcs/vcs.parameters.j2

@@ -0,0 +1,3 @@
+{% for name, value in parameters.items() %}
+assign {{format(value)}} {{name}}
+{% endfor %}

{SimplHDL-0.0.3 → simplhdl-0.0.5}/src/simplhdl/resources/templates/vivado/project.tcl.j2

@@ -85,7 +85,7 @@ read_verilog -sv "{{file.Path}}"
 {% elif file.FileType == VerilogSourceFile %}
 read_verilog "{{file.Path}}"
 {% elif file.FileType == VHDLSourceFile %}
-read_vhdl -vhdl2008 "{{file.Path}}"
+read_vhdl -vhdl2008 -library {{file.Library}} "{{file.Path}}"
 {% elif file.FileType == ConstraintFile %}
 read_xdc "{{file.Path}}"
 {% elif file.FileType == VivadoIPSpecificationFile %}

{SimplHDL-0.0.3 → simplhdl-0.0.5}/src/simplhdl/resources/templates/xsim/Makefile.j2

@@ -3,10 +3,10 @@ XVHDL := xvhdl
 XELAB := xelab
 XSIM := xsim
 
-XVLOG_FLAGS := {{xvlog_args}}
-XVHDL_FLAGS := {{xvhdl_args}}
-XELAB_FLAGS := {{xelab_args}}
-XSIM_FLAGS := {{xsim_args}}
+XVLOG_FLAGS := {{xvlog_args|replace('#', '\#')}}
+XVHDL_FLAGS := {{xvhdl_args|replace('#', '\#')}}
+XELAB_FLAGS := {{xelab_args|replace('#', '\#')}}
+XSIM_FLAGS := {{xsim_args|replace('#', '\#')}}
 
 include project.mk
 -include cocotb.mk

SimplHDL-0.0.3/src/simplhdl/__init__.py

@@ -1 +0,0 @@
-__version__ = "0.0.3"