SimplHDL 0.0.3__tar.gz → 0.0.4__tar.gz

{SimplHDL-0.0.3 → SimplHDL-0.0.4}/PKG-INFO

@@ -1,6 +1,6 @@
 Metadata-Version: 2.1
 Name: SimplHDL
-Version: 0.0.3
+Version: 0.0.4
 Summary: A framework for simulating and implementing HDL designs
 Author-email: Rasmus Grøndahl Olsen <simplhdl@gmail.com>
 Maintainer-email: Rasmus Grøndahl Olsen <simplhdl@gmail.com>

{SimplHDL-0.0.3 → SimplHDL-0.0.4}/src/SimplHDL.egg-info/PKG-INFO

@@ -1,6 +1,6 @@
 Metadata-Version: 2.1
 Name: SimplHDL
-Version: 0.0.3
+Version: 0.0.4
 Summary: A framework for simulating and implementing HDL designs
 Author-email: Rasmus Grøndahl Olsen <simplhdl@gmail.com>
 Maintainer-email: Rasmus Grøndahl Olsen <simplhdl@gmail.com>

SimplHDL-0.0.4/src/simplhdl/__init__.py

@@ -0,0 +1 @@
+__version__ = "0.0.4"

{SimplHDL-0.0.3 → SimplHDL-0.0.4}/src/simplhdl/flows/quartusflow.py

@@ -16,7 +16,8 @@ from ..resources.templates import quartus as templates
 from ..utils import sh, generate_from_template
 from ..pyedaa import (QuartusIPSpecificationFile, VerilogIncludeFile, VerilogSourceFile,
                       SystemVerilogSourceFile, VHDLSourceFile, ConstraintFile,
-                      EDIFNetlistFile, NetlistFile, SettingFile, QuartusSignalTapFile)
+                      EDIFNetlistFile, NetlistFile, SettingFile, QuartusSignalTapFile,
+                      QuartusIniFile, QuartusQIPSpecificationFile, QuartusQSYSSpecificationFile)
 from ..pyedaa.project import Project
 from ..pyedaa.attributes import UsedIn
 
@@ -94,6 +95,9 @@ class QuartusFlow(ImplementationFlow):
             NetlistFile=NetlistFile,
             SettingFile=SettingFile,
             QuartusSignalTapFile=QuartusSignalTapFile,
+            QuartusQIPSpecificationFile=QuartusQIPSpecificationFile,
+            QuartusQSYSSpecificationFile=QuartusQSYSSpecificationFile,
+            QuartusIniFile=QuartusIniFile,
             project=self.project,
             UsedIn=UsedIn)
         template = environment.get_template('run.tcl.j2')

{SimplHDL-0.0.3 → SimplHDL-0.0.4}/src/simplhdl/generators/spd.py

@@ -10,7 +10,8 @@ from shutil import copy, copytree
 
 from ..pyedaa import (
     File, SystemVerilogSourceFile, VHDLSourceFile, VerilogSourceFile,
-    QuartusIPSpecificationFile, HDLLibrary, ConstraintFile, HDLSourceFile
+    QuartusIPSpecificationFile, HDLLibrary, ConstraintFile, HDLSourceFile,
+    QuartusIPCompressedSpecificationFile, QuartusQSYSSpecificationFile
 )
 from ..pyedaa.fileset import FileSet
 from ..flow import FlowBase, FlowCategory, FlowTools
@@ -111,14 +112,15 @@ class Spd:
 @GeneratorFactory.register('QuartusIP')
 class QuartusIP(GeneratorBase):
 
-    def unpack_ip(self, filename: QuartusIPSpecificationFile) -> QuartusIPSpecificationFile:
+    def unpack_ip(self, filename: QuartusIPSpecificationFile) -> QuartusIPSpecificationFile:  # noqa: C901
         ipdir = self.builddir.joinpath('ips')
         dest = ipdir.joinpath(filename.Path.name).with_suffix('')
         md5file = dest.with_suffix('.md5')
         ipdir.mkdir(exist_ok=True)
-        if filename.Path.suffix == '.qsys':
-            return
-        elif filename.Path.suffix == '.zip':
+        if filename.FileType == QuartusQSYSSpecificationFile:
+            pass
+
+        elif filename.FileType == QuartusIPCompressedSpecificationFile:
             update = True
             if md5file.exists():
                 update = not md5check(filename.Path, filename=md5file)
@@ -127,7 +129,14 @@ class QuartusIP(GeneratorBase):
                     zip.extractall(ipdir)
                 md5write(filename.Path, filename=md5file)
                 logger.debug(f"Copy {filename.Path} to {dest}")
-        elif filename.Path.suffix == '.ip':
+
+            if filename.Path.suffix == '.zip':
+                filename._path = dest.absolute()
+            else:
+                filename._path = dest.with_suffix('.ip').absolute()
+            filename._fileType = QuartusIPSpecificationFile
+
+        elif filename.FileType == QuartusIPSpecificationFile:
             update = True
             dir = filename.Path.with_suffix('')
             if dir.exists():
@@ -140,10 +149,8 @@ class QuartusIP(GeneratorBase):
                     copytree(str(dir), str(dest.with_suffix('')), dirs_exist_ok=True)
                     md5write(filename.Path, dir, filename=md5file)
                     logger.debug(f"Copy {filename.Path} to {dest}")
-        else:
-            # Non Qartus IP files
-            return filename
-        filename._path = dest.absolute()
+            filename._path = dest.with_suffix('.ip').absolute()
+
         return filename
 
     def run(self, flow: FlowBase):

{SimplHDL-0.0.3 → SimplHDL-0.0.4}/src/simplhdl/pyedaa/__init__.py

@@ -128,6 +128,25 @@ class QuartusIPSpecificationFile(IPSpecificationFile):
     pass
 
 
+class QuartusIPCompressedSpecificationFile(QuartusIPSpecificationFile):
+    pass
+
+
+class QuartusQSYSSpecificationFile(QuartusIPSpecificationFile):
+    pass
+
+
+class QuartusQIPSpecificationFile(QuartusIPSpecificationFile):
+    pass
+
+
+class QuartusIniFile(File):
+    def _registerAttributes(self):
+        super()._registerAttributes()
+        FileMixIn._registerAttributes(self)
+        self[UsedIn] = {'implementation'}
+
+
 class VivadoIPSpecificationFile(IPSpecificationFile):
     pass
 

{SimplHDL-0.0.3 → SimplHDL-0.0.4}/src/simplhdl/resources/templates/quartus/project.tcl.j2

@@ -14,33 +14,26 @@ set_global_assignment -name VERILOG_MACRO "{{define}}={{value}}"
 {% for file in project.DefaultDesign.Files() if 'implementation' in file[UsedIn] %}
 {% if file.FileType == VerilogIncludeFile %}
 set_global_assignment -name VERILOG_INCLUDE_FILE "{{file.Path}}"
-{% endif %}
-{% if file.FileType == SystemVerilogSourceFile %}
+{% elif file.FileType == SystemVerilogSourceFile %}
 set_global_assignment -name SYSTEMVERILOG_FILE "{{file.Path}}"
-{% endif %}
-{% if file.FileType == VerilogSourceFile %}
+{% elif file.FileType == VerilogSourceFile %}
 set_global_assignment -name VERILOG_FILE "{{file.Path}}"
-{% endif %}
-{% if file.FileType == VHDLSourceFile %}
+{% elif file.FileType == VHDLSourceFile %}
 set_global_assignment -name VHDL_FILE "{{file.Path}}"
-{% endif %}
-{% if file.FileType == ConstraintFile %}
+{% elif file.FileType == ConstraintFile %}
 set_global_assignment -name SDC_FILE "{{file.Path}}"
-{% endif %}
-{% if file.FileType == TCLSourceFile %}
+{% elif file.FileType == TCLSourceFile %}
 set_global_assignment -name TCL_FILE "{{file.Path}}"
-{% endif %}
-{% if file.FileType == QuartusIPSpecificationFile and file.Path.suffix == '.ip' %}
+{% elif file.FileType == QuartusIPSpecificationFile %}
 set_global_assignment -name IP_FILE "{{file.Path}}"
-{% endif %}
-{% if file.FileType == QuartusIPSpecificationFile and file.Path.suffix == '.qip' %}
+{% elif file.FileType == QuartusQIPSpecificationFile %}
 set_global_assignment -name QIP_FILE "{{file.Path}}"
-{% endif %}
-{% if file.FileType == QuartusIPSpecificationFile and file.Path.suffix == '.qsys' %}
+{% elif file.FileType == QuartusQSYSSpecificationFile %}
 set_global_assignment -name QSYS_FILE "{{file.Path}}"
-{% endif %}
-{% if file.FileType == SettingFile and file.Path.suffix == '.qsf' %}
+{% elif file.FileType == SettingFile and file.Path.suffix == '.qsf' %}
 source "{{file.Path}}"
+{% elif file.FileType == QuartusIniFile %}
+file copy -force "{{file.Path}}" "quartus.ini"
 {% endif %}
 {% endfor %}
 

SimplHDL-0.0.3/src/simplhdl/__init__.py

@@ -1 +0,0 @@
-__version__ = "0.0.3"