SimplHDL 0.0.1__tar.gz → 0.0.4__tar.gz
This diff represents the content of publicly available package versions that have been released to one of the supported registries. The information contained in this diff is provided for informational purposes only and reflects changes between package versions as they appear in their respective public registries.
- SimplHDL-0.0.4/.github/workflows/publish.yml +39 -0
- SimplHDL-0.0.4/.gitignore +95 -0
- SimplHDL-0.0.4/.readthedocs.yaml +28 -0
- SimplHDL-0.0.4/LICENSE +21 -0
- SimplHDL-0.0.4/PKG-INFO +166 -0
- SimplHDL-0.0.4/README.md +112 -0
- SimplHDL-0.0.4/docs/_static/simplhdl_dark.png +0 -0
- SimplHDL-0.0.4/docs/_static/simplhdl_light.png +0 -0
- SimplHDL-0.0.4/docs/_static/simplhdl_light_1.png +0 -0
- SimplHDL-0.0.4/docs/conf.py +65 -0
- SimplHDL-0.0.4/docs/drawing.svg +305 -0
- SimplHDL-0.0.4/docs/flows/ghdl.rst +2 -0
- SimplHDL-0.0.4/docs/flows/icarus.rst +2 -0
- SimplHDL-0.0.4/docs/flows/quartus.rst +2 -0
- SimplHDL-0.0.4/docs/flows/questasim.rst +2 -0
- SimplHDL-0.0.4/docs/flows/vcs.rst +2 -0
- SimplHDL-0.0.4/docs/flows/vivado.rst +48 -0
- SimplHDL-0.0.4/docs/flows/xsim.rst +2 -0
- SimplHDL-0.0.4/docs/flows.rst +16 -0
- SimplHDL-0.0.4/docs/index.rst +32 -0
- SimplHDL-0.0.4/docs/intel-ips.md +22 -0
- SimplHDL-0.0.4/docs/introduction.rst +4 -0
- SimplHDL-0.0.4/docs/plugins.rst +55 -0
- SimplHDL-0.0.4/docs/requirements.txt +33 -0
- SimplHDL-0.0.4/examples/hdl/adder/adder.yml +3 -0
- SimplHDL-0.0.4/examples/hdl/adder/hdl/adder.sv +19 -0
- SimplHDL-0.0.4/examples/hdl/adder/sim/testbench.sv +10 -0
- SimplHDL-0.0.4/examples/hdl/adder/sim/testbench.yml +10 -0
- SimplHDL-0.0.4/examples/hdl/adder/syn/build.yml +18 -0
- SimplHDL-0.0.4/examples/hdl/adder/syn/placement.xdc +23 -0
- SimplHDL-0.0.4/examples/hdl/adder/syn/timing.xdc +1 -0
- SimplHDL-0.0.4/examples/hdl/adder/syn/top.sv +21 -0
- SimplHDL-0.0.4/examples/hdl/alu/alu.yml +6 -0
- SimplHDL-0.0.4/examples/hdl/alu/hdl/add.sv +11 -0
- SimplHDL-0.0.4/examples/hdl/alu/hdl/alu.sv +116 -0
- SimplHDL-0.0.4/examples/hdl/alu/hdl/mul.sv +11 -0
- SimplHDL-0.0.4/examples/hdl/alu/hdl/sub.sv +11 -0
- SimplHDL-0.0.4/examples/hdl/alu/sim/pyuvm/alu_vip/__init__.py +7 -0
- SimplHDL-0.0.4/examples/hdl/alu/sim/pyuvm/alu_vip/agent.py +26 -0
- SimplHDL-0.0.4/examples/hdl/alu/sim/pyuvm/alu_vip/aluif.py +11 -0
- SimplHDL-0.0.4/examples/hdl/alu/sim/pyuvm/alu_vip/driver.py +40 -0
- SimplHDL-0.0.4/examples/hdl/alu/sim/pyuvm/alu_vip/monitor.py +31 -0
- SimplHDL-0.0.4/examples/hdl/alu/sim/pyuvm/alu_vip/sequenceitem.py +43 -0
- SimplHDL-0.0.4/examples/hdl/alu/sim/pyuvm/alu_vip/sequencer.py +7 -0
- SimplHDL-0.0.4/examples/hdl/alu/sim/pyuvm/clock_vip/__init__.py +3 -0
- SimplHDL-0.0.4/examples/hdl/alu/sim/pyuvm/clock_vip/agent.py +29 -0
- SimplHDL-0.0.4/examples/hdl/alu/sim/pyuvm/clock_vip/clockif.py +8 -0
- SimplHDL-0.0.4/examples/hdl/alu/sim/pyuvm/pyuvm.yml +9 -0
- SimplHDL-0.0.4/examples/hdl/alu/sim/pyuvm/test/env.py +14 -0
- SimplHDL-0.0.4/examples/hdl/alu/sim/pyuvm/test/seq_lib.py +35 -0
- SimplHDL-0.0.4/examples/hdl/alu/sim/pyuvm/test/test.py +52 -0
- SimplHDL-0.0.4/examples/hdl/alu/sim/pyuvm/testbench.py +8 -0
- SimplHDL-0.0.4/examples/hdl/alu/sim/uvm/alu_vip/agent.svh +40 -0
- SimplHDL-0.0.4/examples/hdl/alu/sim/uvm/alu_vip/alu_vip.sv +22 -0
- SimplHDL-0.0.4/examples/hdl/alu/sim/uvm/alu_vip/alu_vip.yml +9 -0
- SimplHDL-0.0.4/examples/hdl/alu/sim/uvm/alu_vip/driver.svh +51 -0
- SimplHDL-0.0.4/examples/hdl/alu/sim/uvm/alu_vip/env.svh +4 -0
- SimplHDL-0.0.4/examples/hdl/alu/sim/uvm/alu_vip/monitor.svh +135 -0
- SimplHDL-0.0.4/examples/hdl/alu/sim/uvm/alu_vip/sequence_item.svh +27 -0
- SimplHDL-0.0.4/examples/hdl/alu/sim/uvm/tb_env/seq_lib/add_seq.svh +22 -0
- SimplHDL-0.0.4/examples/hdl/alu/sim/uvm/tb_env/seq_lib/base_seq.svh +37 -0
- SimplHDL-0.0.4/examples/hdl/alu/sim/uvm/tb_env/tb_env.sv +13 -0
- SimplHDL-0.0.4/examples/hdl/alu/sim/uvm/tb_env/tb_env.yml +13 -0
- SimplHDL-0.0.4/examples/hdl/alu/sim/uvm/tb_env/test/base_test.svh +22 -0
- SimplHDL-0.0.4/examples/hdl/alu/sim/uvm/tb_env/test/test_add.svh +26 -0
- SimplHDL-0.0.4/examples/hdl/alu/sim/uvm/testbench/alu_if.sv +77 -0
- SimplHDL-0.0.4/examples/hdl/alu/sim/uvm/testbench/testbench.sv +52 -0
- SimplHDL-0.0.4/examples/hdl/alu/sim/uvm/testbench/testbench.yml +9 -0
- SimplHDL-0.0.4/examples/hdl/alu/sim/uvm/testcases/test_add/test_add.yml +9 -0
- SimplHDL-0.0.4/examples/hdl/alu/syn/build.yml +12 -0
- SimplHDL-0.0.4/examples/hdl/alu/syn/placement.xdc +34 -0
- SimplHDL-0.0.4/examples/hdl/alu/syn/timing.xdc +4 -0
- SimplHDL-0.0.4/examples/hdl/hello/build.sbt +11 -0
- SimplHDL-0.0.4/examples/hdl/hello/hello.yml +3 -0
- SimplHDL-0.0.4/examples/hdl/hello/src/main/scala/Hello.scala +33 -0
- SimplHDL-0.0.4/examples/hdl/hello/syn/build.yml +8 -0
- SimplHDL-0.0.4/examples/plugins/simple_parser/setup.py +18 -0
- SimplHDL-0.0.4/examples/plugins/simple_parser/src/simple_parser/__init__.py +4 -0
- SimplHDL-0.0.4/examples/plugins/simple_parser/src/simple_parser/simple_parser.py +41 -0
- SimplHDL-0.0.4/pyproject.toml +54 -0
- SimplHDL-0.0.4/src/SimplHDL.egg-info/PKG-INFO +166 -0
- SimplHDL-0.0.4/src/SimplHDL.egg-info/SOURCES.txt +169 -0
- SimplHDL-0.0.4/src/SimplHDL.egg-info/requires.txt +10 -0
- SimplHDL-0.0.4/src/simplhdl/__init__.py +1 -0
- SimplHDL-0.0.4/src/simplhdl/__main__.py +79 -0
- SimplHDL-0.0.4/src/simplhdl/cocotb.py +52 -0
- SimplHDL-0.0.4/src/simplhdl/flow.py +83 -0
- SimplHDL-0.0.4/src/simplhdl/flows/__init__.py +0 -0
- SimplHDL-0.0.4/src/simplhdl/flows/implementationflow.py +18 -0
- SimplHDL-0.0.4/src/simplhdl/flows/modelsimflow.py +32 -0
- SimplHDL-0.0.4/src/simplhdl/flows/quartusflow.py +129 -0
- SimplHDL-0.0.4/src/simplhdl/flows/questasim/__init__.py +0 -0
- SimplHDL-0.0.4/src/simplhdl/flows/questasim/questasimflow.py +250 -0
- SimplHDL-0.0.4/src/simplhdl/flows/rivierapro/__init__.py +0 -0
- SimplHDL-0.0.4/src/simplhdl/flows/rivierapro/rivieraproflow.py +264 -0
- SimplHDL-0.0.4/src/simplhdl/flows/simulationflow.py +172 -0
- SimplHDL-0.0.4/src/simplhdl/flows/vcs/__init__.py +0 -0
- SimplHDL-0.0.4/src/simplhdl/flows/vcs/vcsflow.py +219 -0
- SimplHDL-0.0.4/src/simplhdl/flows/vivadoflow.py +140 -0
- SimplHDL-0.0.4/src/simplhdl/flows/xsim/__init__.py +0 -0
- SimplHDL-0.0.4/src/simplhdl/flows/xsim/xsimflow.py +218 -0
- SimplHDL-0.0.4/src/simplhdl/generator.py +71 -0
- SimplHDL-0.0.4/src/simplhdl/generators/__init__.py +0 -0
- SimplHDL-0.0.4/src/simplhdl/generators/chisel.py +61 -0
- SimplHDL-0.0.4/src/simplhdl/generators/ipxact.py +216 -0
- SimplHDL-0.0.4/src/simplhdl/generators/spd.py +166 -0
- SimplHDL-0.0.4/src/simplhdl/generators/systemrdl.py +27 -0
- SimplHDL-0.0.4/src/simplhdl/info.py +137 -0
- {SimplHDL-0.0.1 → SimplHDL-0.0.4}/src/simplhdl/parser.py +16 -6
- SimplHDL-0.0.4/src/simplhdl/parsers/__init__.py +0 -0
- {SimplHDL-0.0.1 → SimplHDL-0.0.4}/src/simplhdl/parsers/fusesocparser.py +10 -3
- SimplHDL-0.0.4/src/simplhdl/parsers/simplhdlparser.py +137 -0
- {SimplHDL-0.0.1 → SimplHDL-0.0.4}/src/simplhdl/plugins.py +22 -6
- SimplHDL-0.0.4/src/simplhdl/pyedaa/__init__.py +163 -0
- SimplHDL-0.0.4/src/simplhdl/pyedaa/attributes.py +8 -0
- SimplHDL-0.0.4/src/simplhdl/pyedaa/design.py +68 -0
- SimplHDL-0.0.4/src/simplhdl/pyedaa/fileset.py +53 -0
- SimplHDL-0.0.4/src/simplhdl/pyedaa/filetypes.py +0 -0
- SimplHDL-0.0.4/src/simplhdl/pyedaa/project.py +173 -0
- SimplHDL-0.0.4/src/simplhdl/pyedaa/vhdllibrary.py +31 -0
- SimplHDL-0.0.4/src/simplhdl/repo.py +93 -0
- SimplHDL-0.0.4/src/simplhdl/resources/__init__.py +0 -0
- SimplHDL-0.0.4/src/simplhdl/resources/templates/__init__.py +0 -0
- SimplHDL-0.0.4/src/simplhdl/resources/templates/quartus/__init__.py +0 -0
- SimplHDL-0.0.4/src/simplhdl/resources/templates/quartus/project.tcl.j2 +46 -0
- SimplHDL-0.0.4/src/simplhdl/resources/templates/quartus/run.tcl.j2 +48 -0
- SimplHDL-0.0.4/src/simplhdl/resources/templates/questasim/Makefile.j2 +62 -0
- SimplHDL-0.0.4/src/simplhdl/resources/templates/questasim/__init__.py +0 -0
- SimplHDL-0.0.4/src/simplhdl/resources/templates/questasim/cocotb.mk.j2 +19 -0
- SimplHDL-0.0.4/src/simplhdl/resources/templates/questasim/dependencies.mk.j2 +6 -0
- SimplHDL-0.0.4/src/simplhdl/resources/templates/questasim/files.j2 +4 -0
- SimplHDL-0.0.4/src/simplhdl/resources/templates/questasim/fileset.j2 +7 -0
- SimplHDL-0.0.4/src/simplhdl/resources/templates/questasim/project.mk.j2 +24 -0
- SimplHDL-0.0.4/src/simplhdl/resources/templates/rivierapro/Makefile.j2 +63 -0
- SimplHDL-0.0.4/src/simplhdl/resources/templates/rivierapro/__init__.py +0 -0
- SimplHDL-0.0.4/src/simplhdl/resources/templates/rivierapro/cocotb.mk.j2 +21 -0
- SimplHDL-0.0.4/src/simplhdl/resources/templates/rivierapro/dependencies.mk.j2 +6 -0
- SimplHDL-0.0.4/src/simplhdl/resources/templates/rivierapro/files.j2 +4 -0
- SimplHDL-0.0.4/src/simplhdl/resources/templates/rivierapro/fileset.j2 +7 -0
- SimplHDL-0.0.4/src/simplhdl/resources/templates/rivierapro/project.mk.j2 +24 -0
- SimplHDL-0.0.4/src/simplhdl/resources/templates/vcs/Makefile.j2 +66 -0
- SimplHDL-0.0.4/src/simplhdl/resources/templates/vcs/__init__.py +0 -0
- SimplHDL-0.0.4/src/simplhdl/resources/templates/vcs/cocotb.mk.j2 +10 -0
- SimplHDL-0.0.4/src/simplhdl/resources/templates/vcs/dependencies.mk.j2 +6 -0
- SimplHDL-0.0.4/src/simplhdl/resources/templates/vcs/files.j2 +4 -0
- SimplHDL-0.0.4/src/simplhdl/resources/templates/vcs/fileset.j2 +7 -0
- SimplHDL-0.0.4/src/simplhdl/resources/templates/vcs/pli.tab.j2 +1 -0
- SimplHDL-0.0.4/src/simplhdl/resources/templates/vcs/project.mk.j2 +4 -0
- SimplHDL-0.0.4/src/simplhdl/resources/templates/vcs/synopsys_sim.setup.j2 +7 -0
- SimplHDL-0.0.4/src/simplhdl/resources/templates/vivado/__init__.py +0 -0
- SimplHDL-0.0.4/src/simplhdl/resources/templates/vivado/launch_run.sh.j2 +12 -0
- SimplHDL-0.0.4/src/simplhdl/resources/templates/vivado/project.tcl.j2 +124 -0
- SimplHDL-0.0.4/src/simplhdl/resources/templates/vivado/run.tcl.j2 +55 -0
- SimplHDL-0.0.4/src/simplhdl/resources/templates/vivado/steps.tcl.j2 +19 -0
- SimplHDL-0.0.4/src/simplhdl/resources/templates/xsim/Makefile.j2 +56 -0
- SimplHDL-0.0.4/src/simplhdl/resources/templates/xsim/__init__.py +0 -0
- SimplHDL-0.0.4/src/simplhdl/resources/templates/xsim/cocotb.mk.j2 +12 -0
- SimplHDL-0.0.4/src/simplhdl/resources/templates/xsim/dependencies.mk.j2 +6 -0
- SimplHDL-0.0.4/src/simplhdl/resources/templates/xsim/files.j2 +4 -0
- SimplHDL-0.0.4/src/simplhdl/resources/templates/xsim/fileset.j2 +7 -0
- SimplHDL-0.0.4/src/simplhdl/resources/templates/xsim/project.mk.j2 +4 -0
- SimplHDL-0.0.4/src/simplhdl/simplhdl.py +47 -0
- SimplHDL-0.0.4/src/simplhdl/tools.py +17 -0
- SimplHDL-0.0.4/src/simplhdl/utils.py +130 -0
- SimplHDL-0.0.4/tox.ini +61 -0
- SimplHDL-0.0.1/LICENSE +0 -674
- SimplHDL-0.0.1/PKG-INFO +0 -20
- SimplHDL-0.0.1/README.md +0 -2
- SimplHDL-0.0.1/setup.py +0 -41
- SimplHDL-0.0.1/src/SimplHDL.egg-info/PKG-INFO +0 -20
- SimplHDL-0.0.1/src/SimplHDL.egg-info/SOURCES.txt +0 -18
- SimplHDL-0.0.1/src/SimplHDL.egg-info/requires.txt +0 -8
- SimplHDL-0.0.1/src/simplhdl/__init__.py +0 -3
- SimplHDL-0.0.1/src/simplhdl/__main__.py +0 -46
- SimplHDL-0.0.1/src/simplhdl/parsers/importlistparser.py +0 -19
- SimplHDL-0.0.1/src/simplhdl/simplhdl.py +0 -26
- {SimplHDL-0.0.1/src/simplhdl/parsers → SimplHDL-0.0.4/examples/hdl/alu/sim/pyuvm/test}/__init__.py +0 -0
- {SimplHDL-0.0.1 → SimplHDL-0.0.4}/setup.cfg +0 -0
- {SimplHDL-0.0.1 → SimplHDL-0.0.4}/src/SimplHDL.egg-info/dependency_links.txt +0 -0
- {SimplHDL-0.0.1 → SimplHDL-0.0.4}/src/SimplHDL.egg-info/entry_points.txt +0 -0
- {SimplHDL-0.0.1 → SimplHDL-0.0.4}/src/SimplHDL.egg-info/top_level.txt +0 -0
- {SimplHDL-0.0.1 → SimplHDL-0.0.4}/tests/test_dummy.py +0 -0
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.scrapy
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# Sphinx documentation
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docs/_build/
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target/
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# .readthedocs.yaml
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# Read the Docs configuration file
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# Required
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version: 2
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# Set the OS, Python version and other tools you might need
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build:
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os: ubuntu-22.04
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tools:
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python: "3.10"
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# Build documentation in the "docs/" directory with Sphinx
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sphinx:
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configuration: docs/conf.py
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# Optionally build your docs in additional formats such as PDF and ePub
|
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formats:
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- pdf
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- epub
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# Optional but recommended, declare the Python requirements required
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# to build your documentation
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# See https://docs.readthedocs.io/en/stable/guides/reproducible-builds.html
|
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python:
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install:
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- requirements: docs/requirements.txt
|
SimplHDL-0.0.4/LICENSE
ADDED
|
@@ -0,0 +1,21 @@
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|
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|
+
MIT License
|
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2
|
+
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|
3
|
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Copyright (c) 2024 SimplHDL
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to deal
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7
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+
in the Software without restriction, including without limitation the rights
|
|
8
|
+
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
|
9
|
+
copies of the Software, and to permit persons to whom the Software is
|
|
10
|
+
furnished to do so, subject to the following conditions:
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|
11
|
+
|
|
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|
+
The above copyright notice and this permission notice shall be included in all
|
|
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|
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copies or substantial portions of the Software.
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|
+
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
|
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|
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
|
17
|
+
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
|
18
|
+
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
|
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|
+
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
|
20
|
+
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
|
|
21
|
+
SOFTWARE.
|
SimplHDL-0.0.4/PKG-INFO
ADDED
|
@@ -0,0 +1,166 @@
|
|
|
1
|
+
Metadata-Version: 2.1
|
|
2
|
+
Name: SimplHDL
|
|
3
|
+
Version: 0.0.4
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|
4
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Summary: A framework for simulating and implementing HDL designs
|
|
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Author-email: Rasmus Grøndahl Olsen <simplhdl@gmail.com>
|
|
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|
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Maintainer-email: Rasmus Grøndahl Olsen <simplhdl@gmail.com>
|
|
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|
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License: MIT License
|
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|
+
|
|
9
|
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Copyright (c) 2024 SimplHDL
|
|
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|
+
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|
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|
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Permission is hereby granted, free of charge, to any person obtaining a copy
|
|
12
|
+
of this software and associated documentation files (the "Software"), to deal
|
|
13
|
+
in the Software without restriction, including without limitation the rights
|
|
14
|
+
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
|
15
|
+
copies of the Software, and to permit persons to whom the Software is
|
|
16
|
+
furnished to do so, subject to the following conditions:
|
|
17
|
+
|
|
18
|
+
The above copyright notice and this permission notice shall be included in all
|
|
19
|
+
copies or substantial portions of the Software.
|
|
20
|
+
|
|
21
|
+
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
|
22
|
+
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
|
23
|
+
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
|
24
|
+
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
|
25
|
+
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
|
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|
+
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
|
|
27
|
+
SOFTWARE.
|
|
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|
+
|
|
29
|
+
Project-URL: Homepage, https://github.com/SimplHDL
|
|
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|
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Project-URL: Documentation, https://simplhdl.readthedocs.io/en/latest/
|
|
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|
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Project-URL: Repository, https://github.com/SimplHDL/simplhdl.git
|
|
32
|
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Project-URL: Issues, https://github.com/SimplHDL/simplhdl/issues
|
|
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|
+
Classifier: Development Status :: 4 - Beta
|
|
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|
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Classifier: Programming Language :: Python :: 3
|
|
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|
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Classifier: Programming Language :: Python :: 3.8
|
|
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|
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Classifier: Programming Language :: Python :: 3.9
|
|
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|
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Classifier: Programming Language :: Python :: 3.10
|
|
38
|
+
Classifier: Programming Language :: Python :: 3.11
|
|
39
|
+
Classifier: Programming Language :: Python :: 3.12
|
|
40
|
+
Classifier: Intended Audience :: Developers
|
|
41
|
+
Classifier: License :: OSI Approved :: MIT License
|
|
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|
+
Classifier: Operating System :: OS Independent
|
|
43
|
+
Requires-Python: >=3.8
|
|
44
|
+
Description-Content-Type: text/markdown
|
|
45
|
+
License-File: LICENSE
|
|
46
|
+
Requires-Dist: importlib-resources; python_version < "3.9"
|
|
47
|
+
Requires-Dist: pySVModel==0.3.5
|
|
48
|
+
Requires-Dist: pyEDAA.ProjectModel==0.4.3
|
|
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|
+
Requires-Dist: pyyaml
|
|
50
|
+
Requires-Dist: types-PyYAML
|
|
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|
+
Requires-Dist: argcomplete
|
|
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|
+
Requires-Dist: jinja2
|
|
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|
+
Requires-Dist: GitPython
|
|
54
|
+
|
|
55
|
+
## Introduction
|
|
56
|
+
|
|
57
|
+
SimplHDL is a plugin-based command-line application for simplifying FPGA and
|
|
58
|
+
ASIC development regardless of EDA tools and flows.
|
|
59
|
+
|
|
60
|
+
The goal is to embrase structured and reusable designs by creating a generic
|
|
61
|
+
project model that can be used in any hdl development flow regardless of
|
|
62
|
+
project structure and EDA tool requirements.
|
|
63
|
+
|
|
64
|
+
The plugin based architecture allows for SimplHDL to be migrated into any
|
|
65
|
+
existing project, replacing ad-hoc simulation and implmentation scripts while
|
|
66
|
+
providing a intuitive command-line interface for HDL design and verification
|
|
67
|
+
engineers.
|
|
68
|
+
|
|
69
|
+
I wide vararity of languges, standards and tools are supported.
|
|
70
|
+
|
|
71
|
+
### HDL languages
|
|
72
|
+
|
|
73
|
+
* Verilog / System Verilog
|
|
74
|
+
* VHDL
|
|
75
|
+
* Chisel
|
|
76
|
+
* SystemRDL
|
|
77
|
+
* IPXact
|
|
78
|
+
* Vivado IP containters (.xci, .xcix)
|
|
79
|
+
* Quartus IP containers (.ip)
|
|
80
|
+
|
|
81
|
+
### Methodologies
|
|
82
|
+
|
|
83
|
+
* UVM
|
|
84
|
+
* OSVMM
|
|
85
|
+
* UVVM
|
|
86
|
+
* Cocotb
|
|
87
|
+
* pyuvm
|
|
88
|
+
|
|
89
|
+
### EDA Tools
|
|
90
|
+
|
|
91
|
+
* Vivado
|
|
92
|
+
* Quartus
|
|
93
|
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* Modelsim
|
|
94
|
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* Questasim
|
|
95
|
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* Xsim
|
|
96
|
+
* Vcs
|
|
97
|
+
* Riviera Pro
|
|
98
|
+
* Xcelium (coming)
|
|
99
|
+
* Verilator (coming)
|
|
100
|
+
* Icarus (coming)
|
|
101
|
+
* GHDL (coming)
|
|
102
|
+
|
|
103
|
+
## Getting Started
|
|
104
|
+
|
|
105
|
+
SimplHDL currently works on Linux and Windows WSL. It is written in Python and can
|
|
106
|
+
be installed with *pip*. To run SimplHDL Python 3.8 or later is required. The
|
|
107
|
+
tools for the flows you wish to run also need to be installed and set up
|
|
108
|
+
correctly in the shell environment. SimplHDL can be installed on your system's
|
|
109
|
+
Python installation, but it is highly recommended to install and run SimplHDL
|
|
110
|
+
in a Python virtual environment or a Conda environment.
|
|
111
|
+
|
|
112
|
+
## Example
|
|
113
|
+
|
|
114
|
+
To quickly try out SimplHDL follow these steps. In this example, we will use
|
|
115
|
+
Vivado and QuestaSim. The prerequisites are that SimplHDL install installed and
|
|
116
|
+
Vivado and QuestaSim are correctly set up in your shell environment.
|
|
117
|
+
|
|
118
|
+
1. Clone Git repository from GitHub
|
|
119
|
+
|
|
120
|
+
```console
|
|
121
|
+
git clone https://github.com/SimplHDL/simplhdl.git
|
|
122
|
+
```
|
|
123
|
+
|
|
124
|
+
2. install SimplHDL from source
|
|
125
|
+
|
|
126
|
+
```console
|
|
127
|
+
pip install ./simplhdl
|
|
128
|
+
```
|
|
129
|
+
|
|
130
|
+
3. Run simulation
|
|
131
|
+
|
|
132
|
+
```console
|
|
133
|
+
cd simplhdl/examples/hdl/alu/sim
|
|
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|
+
simpl questasim
|
|
135
|
+
```
|
|
136
|
+
|
|
137
|
+
4. Run simulation interactively in Gui.
|
|
138
|
+
|
|
139
|
+
```console
|
|
140
|
+
cd simplhdl/examples/hdl/alu/sim
|
|
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|
+
simpl questasim --gui
|
|
142
|
+
```
|
|
143
|
+
|
|
144
|
+
5. Run implementation
|
|
145
|
+
|
|
146
|
+
```console
|
|
147
|
+
cd ../syn
|
|
148
|
+
simpl vivado
|
|
149
|
+
```
|
|
150
|
+
|
|
151
|
+
6. Run implementation interactively in Gui.
|
|
152
|
+
|
|
153
|
+
```console
|
|
154
|
+
simpl vivado --gui
|
|
155
|
+
```
|
|
156
|
+
|
|
157
|
+
In this example, the project specification is written in Yaml. This format is
|
|
158
|
+
only meant as a demonstration. To integrate SimplHDL into your project, you have
|
|
159
|
+
to write a parser plugin for your specific project specification format.
|
|
160
|
+
See the documentation and plugin examples for more information.
|
|
161
|
+
|
|
162
|
+
## Links
|
|
163
|
+
|
|
164
|
+
* Homepage:
|
|
165
|
+
* Source: <https://github.com/SimplHDL/simplhdl>
|
|
166
|
+
* Tracker: <https://github.com/SimplHDL/simplhdl/issues>
|
SimplHDL-0.0.4/README.md
ADDED
|
@@ -0,0 +1,112 @@
|
|
|
1
|
+
## Introduction
|
|
2
|
+
|
|
3
|
+
SimplHDL is a plugin-based command-line application for simplifying FPGA and
|
|
4
|
+
ASIC development regardless of EDA tools and flows.
|
|
5
|
+
|
|
6
|
+
The goal is to embrase structured and reusable designs by creating a generic
|
|
7
|
+
project model that can be used in any hdl development flow regardless of
|
|
8
|
+
project structure and EDA tool requirements.
|
|
9
|
+
|
|
10
|
+
The plugin based architecture allows for SimplHDL to be migrated into any
|
|
11
|
+
existing project, replacing ad-hoc simulation and implmentation scripts while
|
|
12
|
+
providing a intuitive command-line interface for HDL design and verification
|
|
13
|
+
engineers.
|
|
14
|
+
|
|
15
|
+
I wide vararity of languges, standards and tools are supported.
|
|
16
|
+
|
|
17
|
+
### HDL languages
|
|
18
|
+
|
|
19
|
+
* Verilog / System Verilog
|
|
20
|
+
* VHDL
|
|
21
|
+
* Chisel
|
|
22
|
+
* SystemRDL
|
|
23
|
+
* IPXact
|
|
24
|
+
* Vivado IP containters (.xci, .xcix)
|
|
25
|
+
* Quartus IP containers (.ip)
|
|
26
|
+
|
|
27
|
+
### Methodologies
|
|
28
|
+
|
|
29
|
+
* UVM
|
|
30
|
+
* OSVMM
|
|
31
|
+
* UVVM
|
|
32
|
+
* Cocotb
|
|
33
|
+
* pyuvm
|
|
34
|
+
|
|
35
|
+
### EDA Tools
|
|
36
|
+
|
|
37
|
+
* Vivado
|
|
38
|
+
* Quartus
|
|
39
|
+
* Modelsim
|
|
40
|
+
* Questasim
|
|
41
|
+
* Xsim
|
|
42
|
+
* Vcs
|
|
43
|
+
* Riviera Pro
|
|
44
|
+
* Xcelium (coming)
|
|
45
|
+
* Verilator (coming)
|
|
46
|
+
* Icarus (coming)
|
|
47
|
+
* GHDL (coming)
|
|
48
|
+
|
|
49
|
+
## Getting Started
|
|
50
|
+
|
|
51
|
+
SimplHDL currently works on Linux and Windows WSL. It is written in Python and can
|
|
52
|
+
be installed with *pip*. To run SimplHDL Python 3.8 or later is required. The
|
|
53
|
+
tools for the flows you wish to run also need to be installed and set up
|
|
54
|
+
correctly in the shell environment. SimplHDL can be installed on your system's
|
|
55
|
+
Python installation, but it is highly recommended to install and run SimplHDL
|
|
56
|
+
in a Python virtual environment or a Conda environment.
|
|
57
|
+
|
|
58
|
+
## Example
|
|
59
|
+
|
|
60
|
+
To quickly try out SimplHDL follow these steps. In this example, we will use
|
|
61
|
+
Vivado and QuestaSim. The prerequisites are that SimplHDL install installed and
|
|
62
|
+
Vivado and QuestaSim are correctly set up in your shell environment.
|
|
63
|
+
|
|
64
|
+
1. Clone Git repository from GitHub
|
|
65
|
+
|
|
66
|
+
```console
|
|
67
|
+
git clone https://github.com/SimplHDL/simplhdl.git
|
|
68
|
+
```
|
|
69
|
+
|
|
70
|
+
2. install SimplHDL from source
|
|
71
|
+
|
|
72
|
+
```console
|
|
73
|
+
pip install ./simplhdl
|
|
74
|
+
```
|
|
75
|
+
|
|
76
|
+
3. Run simulation
|
|
77
|
+
|
|
78
|
+
```console
|
|
79
|
+
cd simplhdl/examples/hdl/alu/sim
|
|
80
|
+
simpl questasim
|
|
81
|
+
```
|
|
82
|
+
|
|
83
|
+
4. Run simulation interactively in Gui.
|
|
84
|
+
|
|
85
|
+
```console
|
|
86
|
+
cd simplhdl/examples/hdl/alu/sim
|
|
87
|
+
simpl questasim --gui
|
|
88
|
+
```
|
|
89
|
+
|
|
90
|
+
5. Run implementation
|
|
91
|
+
|
|
92
|
+
```console
|
|
93
|
+
cd ../syn
|
|
94
|
+
simpl vivado
|
|
95
|
+
```
|
|
96
|
+
|
|
97
|
+
6. Run implementation interactively in Gui.
|
|
98
|
+
|
|
99
|
+
```console
|
|
100
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+
simpl vivado --gui
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101
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+
```
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102
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+
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103
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+
In this example, the project specification is written in Yaml. This format is
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104
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+
only meant as a demonstration. To integrate SimplHDL into your project, you have
|
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105
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+
to write a parser plugin for your specific project specification format.
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106
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+
See the documentation and plugin examples for more information.
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107
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+
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108
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+
## Links
|
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109
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+
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110
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+
* Homepage:
|
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111
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+
* Source: <https://github.com/SimplHDL/simplhdl>
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112
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+
* Tracker: <https://github.com/SimplHDL/simplhdl/issues>
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Binary file
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Binary file
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Binary file
|
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@@ -0,0 +1,65 @@
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1
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# Configuration file for the Sphinx documentation builder.
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2
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+
#
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3
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+
# For the full list of built-in configuration values, see the documentation:
|
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4
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+
# https://www.sphinx-doc.org/en/master/usage/configuration.html
|
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5
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+
|
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6
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# -- Project information -----------------------------------------------------
|
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7
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+
# https://www.sphinx-doc.org/en/master/usage/configuration.html#project-information
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8
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+
|
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9
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+
import sys
|
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10
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+
import time
|
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11
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from os import environ
|
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12
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+
from os.path import abspath, join
|
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13
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+
from pathlib import Path
|
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14
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+
from sphinx_pyproject import SphinxConfig
|
|
15
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+
from simplhdl import __version__
|
|
16
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+
|
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17
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+
sys.path.insert(0, abspath('.'))
|
|
18
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+
sys.path.insert(0, abspath('..'))
|
|
19
|
+
sys.path.insert(0, abspath('../src/simplhdl'))
|
|
20
|
+
|
|
21
|
+
config = SphinxConfig(
|
|
22
|
+
"../pyproject.toml",
|
|
23
|
+
globalns=globals(),
|
|
24
|
+
config_overrides={'version': __version__})
|
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25
|
+
|
|
26
|
+
|
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27
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+
project = name
|
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28
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+
copyright = f"2016-{time.strftime('%Y')}, {author}"
|
|
29
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+
release = version
|
|
30
|
+
|
|
31
|
+
# -- General configuration ---------------------------------------------------
|
|
32
|
+
# https://www.sphinx-doc.org/en/master/usage/configuration.html#general-configuration
|
|
33
|
+
|
|
34
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+
extensions = []
|
|
35
|
+
|
|
36
|
+
# templates_path = ['_templates']
|
|
37
|
+
exclude_patterns = ['_build', 'Thumbs.db', '.DS_Store']
|
|
38
|
+
|
|
39
|
+
# -- Options for HTML output -------------------------------------------------
|
|
40
|
+
# https://www.sphinx-doc.org/en/master/usage/configuration.html#options-for-html-output
|
|
41
|
+
|
|
42
|
+
html_theme = 'furo'
|
|
43
|
+
html_static_path = ['_static']
|
|
44
|
+
html_logo = join(abspath('.'), html_static_path[0], 'simplhdl_light_1.png')
|
|
45
|
+
|
|
46
|
+
html_theme_options = {
|
|
47
|
+
"source_repository": "https://github.com/SimplHDL/simplhdl",
|
|
48
|
+
"source_branch": environ.get("GITHUB_REF_NAME", "main"),
|
|
49
|
+
"source_directory": "",
|
|
50
|
+
"sidebar_hide_name": True,
|
|
51
|
+
"footer_icons": [
|
|
52
|
+
{
|
|
53
|
+
"name": "Gitter hdl/community",
|
|
54
|
+
"url": "https://gitter.im/hdl/community",
|
|
55
|
+
"html": "",
|
|
56
|
+
"class": "fa-solid fa-brands fa-gitter",
|
|
57
|
+
},
|
|
58
|
+
{
|
|
59
|
+
"name": "GitHub https://github.com/SimplHDL/simplhdl",
|
|
60
|
+
"url": "https://github.com/SimplHDL/simplhdl",
|
|
61
|
+
"html": "",
|
|
62
|
+
"class": "fa-solid fa-brands fa-github",
|
|
63
|
+
},
|
|
64
|
+
],
|
|
65
|
+
}
|