SimplHDL 0.0.1__tar.gz → 0.0.3__tar.gz

This diff represents the content of publicly available package versions that have been released to one of the supported registries. The information contained in this diff is provided for informational purposes only and reflects changes between package versions as they appear in their respective public registries.
Files changed (182) hide show
  1. SimplHDL-0.0.3/.github/workflows/publish.yml +39 -0
  2. SimplHDL-0.0.3/.gitignore +95 -0
  3. SimplHDL-0.0.3/.readthedocs.yaml +28 -0
  4. SimplHDL-0.0.3/LICENSE +21 -0
  5. SimplHDL-0.0.3/PKG-INFO +166 -0
  6. SimplHDL-0.0.3/README.md +112 -0
  7. SimplHDL-0.0.3/docs/_static/simplhdl_dark.png +0 -0
  8. SimplHDL-0.0.3/docs/_static/simplhdl_light.png +0 -0
  9. SimplHDL-0.0.3/docs/_static/simplhdl_light_1.png +0 -0
  10. SimplHDL-0.0.3/docs/conf.py +65 -0
  11. SimplHDL-0.0.3/docs/drawing.svg +305 -0
  12. SimplHDL-0.0.3/docs/flows/ghdl.rst +2 -0
  13. SimplHDL-0.0.3/docs/flows/icarus.rst +2 -0
  14. SimplHDL-0.0.3/docs/flows/quartus.rst +2 -0
  15. SimplHDL-0.0.3/docs/flows/questasim.rst +2 -0
  16. SimplHDL-0.0.3/docs/flows/vcs.rst +2 -0
  17. SimplHDL-0.0.3/docs/flows/vivado.rst +48 -0
  18. SimplHDL-0.0.3/docs/flows/xsim.rst +2 -0
  19. SimplHDL-0.0.3/docs/flows.rst +16 -0
  20. SimplHDL-0.0.3/docs/index.rst +32 -0
  21. SimplHDL-0.0.3/docs/intel-ips.md +22 -0
  22. SimplHDL-0.0.3/docs/introduction.rst +4 -0
  23. SimplHDL-0.0.3/docs/plugins.rst +55 -0
  24. SimplHDL-0.0.3/docs/requirements.txt +33 -0
  25. SimplHDL-0.0.3/examples/hdl/adder/adder.yml +3 -0
  26. SimplHDL-0.0.3/examples/hdl/adder/hdl/adder.sv +19 -0
  27. SimplHDL-0.0.3/examples/hdl/adder/sim/testbench.sv +10 -0
  28. SimplHDL-0.0.3/examples/hdl/adder/sim/testbench.yml +10 -0
  29. SimplHDL-0.0.3/examples/hdl/adder/syn/build.yml +18 -0
  30. SimplHDL-0.0.3/examples/hdl/adder/syn/placement.xdc +23 -0
  31. SimplHDL-0.0.3/examples/hdl/adder/syn/timing.xdc +1 -0
  32. SimplHDL-0.0.3/examples/hdl/adder/syn/top.sv +21 -0
  33. SimplHDL-0.0.3/examples/hdl/alu/alu.yml +6 -0
  34. SimplHDL-0.0.3/examples/hdl/alu/hdl/add.sv +11 -0
  35. SimplHDL-0.0.3/examples/hdl/alu/hdl/alu.sv +116 -0
  36. SimplHDL-0.0.3/examples/hdl/alu/hdl/mul.sv +11 -0
  37. SimplHDL-0.0.3/examples/hdl/alu/hdl/sub.sv +11 -0
  38. SimplHDL-0.0.3/examples/hdl/alu/sim/pyuvm/alu_vip/__init__.py +7 -0
  39. SimplHDL-0.0.3/examples/hdl/alu/sim/pyuvm/alu_vip/agent.py +26 -0
  40. SimplHDL-0.0.3/examples/hdl/alu/sim/pyuvm/alu_vip/aluif.py +11 -0
  41. SimplHDL-0.0.3/examples/hdl/alu/sim/pyuvm/alu_vip/driver.py +40 -0
  42. SimplHDL-0.0.3/examples/hdl/alu/sim/pyuvm/alu_vip/monitor.py +31 -0
  43. SimplHDL-0.0.3/examples/hdl/alu/sim/pyuvm/alu_vip/sequenceitem.py +43 -0
  44. SimplHDL-0.0.3/examples/hdl/alu/sim/pyuvm/alu_vip/sequencer.py +7 -0
  45. SimplHDL-0.0.3/examples/hdl/alu/sim/pyuvm/clock_vip/__init__.py +3 -0
  46. SimplHDL-0.0.3/examples/hdl/alu/sim/pyuvm/clock_vip/agent.py +29 -0
  47. SimplHDL-0.0.3/examples/hdl/alu/sim/pyuvm/clock_vip/clockif.py +8 -0
  48. SimplHDL-0.0.3/examples/hdl/alu/sim/pyuvm/pyuvm.yml +9 -0
  49. SimplHDL-0.0.3/examples/hdl/alu/sim/pyuvm/test/env.py +14 -0
  50. SimplHDL-0.0.3/examples/hdl/alu/sim/pyuvm/test/seq_lib.py +35 -0
  51. SimplHDL-0.0.3/examples/hdl/alu/sim/pyuvm/test/test.py +52 -0
  52. SimplHDL-0.0.3/examples/hdl/alu/sim/pyuvm/testbench.py +8 -0
  53. SimplHDL-0.0.3/examples/hdl/alu/sim/uvm/alu_vip/agent.svh +40 -0
  54. SimplHDL-0.0.3/examples/hdl/alu/sim/uvm/alu_vip/alu_vip.sv +22 -0
  55. SimplHDL-0.0.3/examples/hdl/alu/sim/uvm/alu_vip/alu_vip.yml +9 -0
  56. SimplHDL-0.0.3/examples/hdl/alu/sim/uvm/alu_vip/driver.svh +51 -0
  57. SimplHDL-0.0.3/examples/hdl/alu/sim/uvm/alu_vip/env.svh +4 -0
  58. SimplHDL-0.0.3/examples/hdl/alu/sim/uvm/alu_vip/monitor.svh +135 -0
  59. SimplHDL-0.0.3/examples/hdl/alu/sim/uvm/alu_vip/sequence_item.svh +27 -0
  60. SimplHDL-0.0.3/examples/hdl/alu/sim/uvm/tb_env/seq_lib/add_seq.svh +22 -0
  61. SimplHDL-0.0.3/examples/hdl/alu/sim/uvm/tb_env/seq_lib/base_seq.svh +37 -0
  62. SimplHDL-0.0.3/examples/hdl/alu/sim/uvm/tb_env/tb_env.sv +13 -0
  63. SimplHDL-0.0.3/examples/hdl/alu/sim/uvm/tb_env/tb_env.yml +13 -0
  64. SimplHDL-0.0.3/examples/hdl/alu/sim/uvm/tb_env/test/base_test.svh +22 -0
  65. SimplHDL-0.0.3/examples/hdl/alu/sim/uvm/tb_env/test/test_add.svh +26 -0
  66. SimplHDL-0.0.3/examples/hdl/alu/sim/uvm/testbench/alu_if.sv +77 -0
  67. SimplHDL-0.0.3/examples/hdl/alu/sim/uvm/testbench/testbench.sv +52 -0
  68. SimplHDL-0.0.3/examples/hdl/alu/sim/uvm/testbench/testbench.yml +9 -0
  69. SimplHDL-0.0.3/examples/hdl/alu/sim/uvm/testcases/test_add/test_add.yml +9 -0
  70. SimplHDL-0.0.3/examples/hdl/alu/syn/build.yml +12 -0
  71. SimplHDL-0.0.3/examples/hdl/alu/syn/placement.xdc +34 -0
  72. SimplHDL-0.0.3/examples/hdl/alu/syn/timing.xdc +4 -0
  73. SimplHDL-0.0.3/examples/hdl/hello/build.sbt +11 -0
  74. SimplHDL-0.0.3/examples/hdl/hello/hello.yml +3 -0
  75. SimplHDL-0.0.3/examples/hdl/hello/src/main/scala/Hello.scala +33 -0
  76. SimplHDL-0.0.3/examples/hdl/hello/syn/build.yml +8 -0
  77. SimplHDL-0.0.3/examples/plugins/simple_parser/setup.py +18 -0
  78. SimplHDL-0.0.3/examples/plugins/simple_parser/src/simple_parser/__init__.py +4 -0
  79. SimplHDL-0.0.3/examples/plugins/simple_parser/src/simple_parser/simple_parser.py +41 -0
  80. SimplHDL-0.0.3/pyproject.toml +54 -0
  81. SimplHDL-0.0.3/src/SimplHDL.egg-info/PKG-INFO +166 -0
  82. SimplHDL-0.0.3/src/SimplHDL.egg-info/SOURCES.txt +169 -0
  83. SimplHDL-0.0.3/src/SimplHDL.egg-info/requires.txt +10 -0
  84. SimplHDL-0.0.3/src/simplhdl/__init__.py +1 -0
  85. SimplHDL-0.0.3/src/simplhdl/__main__.py +79 -0
  86. SimplHDL-0.0.3/src/simplhdl/cocotb.py +52 -0
  87. SimplHDL-0.0.3/src/simplhdl/flow.py +83 -0
  88. SimplHDL-0.0.3/src/simplhdl/flows/__init__.py +0 -0
  89. SimplHDL-0.0.3/src/simplhdl/flows/implementationflow.py +18 -0
  90. SimplHDL-0.0.3/src/simplhdl/flows/modelsimflow.py +32 -0
  91. SimplHDL-0.0.3/src/simplhdl/flows/quartusflow.py +125 -0
  92. SimplHDL-0.0.3/src/simplhdl/flows/questasim/__init__.py +0 -0
  93. SimplHDL-0.0.3/src/simplhdl/flows/questasim/questasimflow.py +250 -0
  94. SimplHDL-0.0.3/src/simplhdl/flows/rivierapro/__init__.py +0 -0
  95. SimplHDL-0.0.3/src/simplhdl/flows/rivierapro/rivieraproflow.py +264 -0
  96. SimplHDL-0.0.3/src/simplhdl/flows/simulationflow.py +172 -0
  97. SimplHDL-0.0.3/src/simplhdl/flows/vcs/__init__.py +0 -0
  98. SimplHDL-0.0.3/src/simplhdl/flows/vcs/vcsflow.py +219 -0
  99. SimplHDL-0.0.3/src/simplhdl/flows/vivadoflow.py +140 -0
  100. SimplHDL-0.0.3/src/simplhdl/flows/xsim/__init__.py +0 -0
  101. SimplHDL-0.0.3/src/simplhdl/flows/xsim/xsimflow.py +218 -0
  102. SimplHDL-0.0.3/src/simplhdl/generator.py +71 -0
  103. SimplHDL-0.0.3/src/simplhdl/generators/__init__.py +0 -0
  104. SimplHDL-0.0.3/src/simplhdl/generators/chisel.py +61 -0
  105. SimplHDL-0.0.3/src/simplhdl/generators/ipxact.py +216 -0
  106. SimplHDL-0.0.3/src/simplhdl/generators/spd.py +159 -0
  107. SimplHDL-0.0.3/src/simplhdl/generators/systemrdl.py +27 -0
  108. SimplHDL-0.0.3/src/simplhdl/info.py +137 -0
  109. {SimplHDL-0.0.1 → SimplHDL-0.0.3}/src/simplhdl/parser.py +16 -6
  110. SimplHDL-0.0.3/src/simplhdl/parsers/__init__.py +0 -0
  111. {SimplHDL-0.0.1 → SimplHDL-0.0.3}/src/simplhdl/parsers/fusesocparser.py +10 -3
  112. SimplHDL-0.0.3/src/simplhdl/parsers/simplhdlparser.py +137 -0
  113. {SimplHDL-0.0.1 → SimplHDL-0.0.3}/src/simplhdl/plugins.py +22 -6
  114. SimplHDL-0.0.3/src/simplhdl/pyedaa/__init__.py +144 -0
  115. SimplHDL-0.0.3/src/simplhdl/pyedaa/attributes.py +8 -0
  116. SimplHDL-0.0.3/src/simplhdl/pyedaa/design.py +68 -0
  117. SimplHDL-0.0.3/src/simplhdl/pyedaa/fileset.py +53 -0
  118. SimplHDL-0.0.3/src/simplhdl/pyedaa/filetypes.py +0 -0
  119. SimplHDL-0.0.3/src/simplhdl/pyedaa/project.py +173 -0
  120. SimplHDL-0.0.3/src/simplhdl/pyedaa/vhdllibrary.py +31 -0
  121. SimplHDL-0.0.3/src/simplhdl/repo.py +93 -0
  122. SimplHDL-0.0.3/src/simplhdl/resources/__init__.py +0 -0
  123. SimplHDL-0.0.3/src/simplhdl/resources/templates/__init__.py +0 -0
  124. SimplHDL-0.0.3/src/simplhdl/resources/templates/quartus/__init__.py +0 -0
  125. SimplHDL-0.0.3/src/simplhdl/resources/templates/quartus/project.tcl.j2 +53 -0
  126. SimplHDL-0.0.3/src/simplhdl/resources/templates/quartus/run.tcl.j2 +48 -0
  127. SimplHDL-0.0.3/src/simplhdl/resources/templates/questasim/Makefile.j2 +62 -0
  128. SimplHDL-0.0.3/src/simplhdl/resources/templates/questasim/__init__.py +0 -0
  129. SimplHDL-0.0.3/src/simplhdl/resources/templates/questasim/cocotb.mk.j2 +19 -0
  130. SimplHDL-0.0.3/src/simplhdl/resources/templates/questasim/dependencies.mk.j2 +6 -0
  131. SimplHDL-0.0.3/src/simplhdl/resources/templates/questasim/files.j2 +4 -0
  132. SimplHDL-0.0.3/src/simplhdl/resources/templates/questasim/fileset.j2 +7 -0
  133. SimplHDL-0.0.3/src/simplhdl/resources/templates/questasim/project.mk.j2 +24 -0
  134. SimplHDL-0.0.3/src/simplhdl/resources/templates/rivierapro/Makefile.j2 +63 -0
  135. SimplHDL-0.0.3/src/simplhdl/resources/templates/rivierapro/__init__.py +0 -0
  136. SimplHDL-0.0.3/src/simplhdl/resources/templates/rivierapro/cocotb.mk.j2 +21 -0
  137. SimplHDL-0.0.3/src/simplhdl/resources/templates/rivierapro/dependencies.mk.j2 +6 -0
  138. SimplHDL-0.0.3/src/simplhdl/resources/templates/rivierapro/files.j2 +4 -0
  139. SimplHDL-0.0.3/src/simplhdl/resources/templates/rivierapro/fileset.j2 +7 -0
  140. SimplHDL-0.0.3/src/simplhdl/resources/templates/rivierapro/project.mk.j2 +24 -0
  141. SimplHDL-0.0.3/src/simplhdl/resources/templates/vcs/Makefile.j2 +66 -0
  142. SimplHDL-0.0.3/src/simplhdl/resources/templates/vcs/__init__.py +0 -0
  143. SimplHDL-0.0.3/src/simplhdl/resources/templates/vcs/cocotb.mk.j2 +10 -0
  144. SimplHDL-0.0.3/src/simplhdl/resources/templates/vcs/dependencies.mk.j2 +6 -0
  145. SimplHDL-0.0.3/src/simplhdl/resources/templates/vcs/files.j2 +4 -0
  146. SimplHDL-0.0.3/src/simplhdl/resources/templates/vcs/fileset.j2 +7 -0
  147. SimplHDL-0.0.3/src/simplhdl/resources/templates/vcs/pli.tab.j2 +1 -0
  148. SimplHDL-0.0.3/src/simplhdl/resources/templates/vcs/project.mk.j2 +4 -0
  149. SimplHDL-0.0.3/src/simplhdl/resources/templates/vcs/synopsys_sim.setup.j2 +7 -0
  150. SimplHDL-0.0.3/src/simplhdl/resources/templates/vivado/__init__.py +0 -0
  151. SimplHDL-0.0.3/src/simplhdl/resources/templates/vivado/launch_run.sh.j2 +12 -0
  152. SimplHDL-0.0.3/src/simplhdl/resources/templates/vivado/project.tcl.j2 +124 -0
  153. SimplHDL-0.0.3/src/simplhdl/resources/templates/vivado/run.tcl.j2 +55 -0
  154. SimplHDL-0.0.3/src/simplhdl/resources/templates/vivado/steps.tcl.j2 +19 -0
  155. SimplHDL-0.0.3/src/simplhdl/resources/templates/xsim/Makefile.j2 +56 -0
  156. SimplHDL-0.0.3/src/simplhdl/resources/templates/xsim/__init__.py +0 -0
  157. SimplHDL-0.0.3/src/simplhdl/resources/templates/xsim/cocotb.mk.j2 +12 -0
  158. SimplHDL-0.0.3/src/simplhdl/resources/templates/xsim/dependencies.mk.j2 +6 -0
  159. SimplHDL-0.0.3/src/simplhdl/resources/templates/xsim/files.j2 +4 -0
  160. SimplHDL-0.0.3/src/simplhdl/resources/templates/xsim/fileset.j2 +7 -0
  161. SimplHDL-0.0.3/src/simplhdl/resources/templates/xsim/project.mk.j2 +4 -0
  162. SimplHDL-0.0.3/src/simplhdl/simplhdl.py +47 -0
  163. SimplHDL-0.0.3/src/simplhdl/tools.py +17 -0
  164. SimplHDL-0.0.3/src/simplhdl/utils.py +130 -0
  165. SimplHDL-0.0.3/tox.ini +61 -0
  166. SimplHDL-0.0.1/LICENSE +0 -674
  167. SimplHDL-0.0.1/PKG-INFO +0 -20
  168. SimplHDL-0.0.1/README.md +0 -2
  169. SimplHDL-0.0.1/setup.py +0 -41
  170. SimplHDL-0.0.1/src/SimplHDL.egg-info/PKG-INFO +0 -20
  171. SimplHDL-0.0.1/src/SimplHDL.egg-info/SOURCES.txt +0 -18
  172. SimplHDL-0.0.1/src/SimplHDL.egg-info/requires.txt +0 -8
  173. SimplHDL-0.0.1/src/simplhdl/__init__.py +0 -3
  174. SimplHDL-0.0.1/src/simplhdl/__main__.py +0 -46
  175. SimplHDL-0.0.1/src/simplhdl/parsers/importlistparser.py +0 -19
  176. SimplHDL-0.0.1/src/simplhdl/simplhdl.py +0 -26
  177. {SimplHDL-0.0.1/src/simplhdl/parsers → SimplHDL-0.0.3/examples/hdl/alu/sim/pyuvm/test}/__init__.py +0 -0
  178. {SimplHDL-0.0.1 → SimplHDL-0.0.3}/setup.cfg +0 -0
  179. {SimplHDL-0.0.1 → SimplHDL-0.0.3}/src/SimplHDL.egg-info/dependency_links.txt +0 -0
  180. {SimplHDL-0.0.1 → SimplHDL-0.0.3}/src/SimplHDL.egg-info/entry_points.txt +0 -0
  181. {SimplHDL-0.0.1 → SimplHDL-0.0.3}/src/SimplHDL.egg-info/top_level.txt +0 -0
  182. {SimplHDL-0.0.1 → SimplHDL-0.0.3}/tests/test_dummy.py +0 -0
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+ # This workflow will upload a Python Package using Twine when a release is created
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+ # For more information see: https://docs.github.com/en/actions/automating-builds-and-tests/building-and-testing-python#publishing-to-package-registries
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+
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+ # This workflow uses actions that are not certified by GitHub.
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+ # They are provided by a third-party and are governed by
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+ # separate terms of service, privacy policy, and support
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+ # documentation.
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+
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+ name: Upload Python Package
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+
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+ on:
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+ release:
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+ types: [published]
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+
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+ permissions:
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+ contents: read
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+
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+ jobs:
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+ publish:
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+ name: upload release to PyPI
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+ runs-on: ubuntu-latest
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+ environment: release
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+ permissions:
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+ # IMPORTANT: this permission is mandatory for trusted publishing
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+ id-token: write
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+ steps:
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+ - uses: actions/checkout@v3
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+ - name: Set up Python
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+ uses: actions/setup-python@v3
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+ with:
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+ python-version: '3.x'
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+ - name: Install dependencies
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+ run: |
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+ python -m pip install --upgrade pip
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+ pip install build
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+ - name: Build package
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+ run: python -m build
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+ - name: Publish package distributions to PyPI
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+ uses: pypa/gh-action-pypi-publish@release/v1
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+ # SimplHDL build dir
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+ _build
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+
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+ # Byte-compiled / optimized / DLL files
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+ __pycache__/
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+ *.py[cod]
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+ *$py.class
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+
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+ # C extensions
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+ *.so
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+
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+ # Distribution / packaging
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+ .Python
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+ env/
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+ build/
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+ develop-eggs/
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+ dist/
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+ downloads/
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+ eggs/
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+ .eggs/
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+ lib/
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+ lib64/
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+ parts/
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+ sdist/
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+ var/
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+ *.egg-info/
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+ .installed.cfg
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+ *.egg
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+
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+ # PyInstaller
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+ # Usually these files are written by a python script from a template
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+ # before PyInstaller builds the exe, so as to inject date/other infos into it.
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+ *.manifest
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+ *.spec
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+
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+ # Installer logs
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+ pip-log.txt
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+ pip-delete-this-directory.txt
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+
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+ # Unit test / coverage reports
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+ htmlcov/
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+ .tox/
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+ .coverage
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+ .coverage.*
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+ .cache
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+ nosetests.xml
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+ coverage.xml
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+ *,cover
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+ .hypothesis/
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+
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+ # Translations
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+ *.mo
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+ *.pot
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+
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+ # Django stuff:
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+ *.log
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+ local_settings.py
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+
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+ # Flask stuff:
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+ instance/
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+ .webassets-cache
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+
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+ # Scrapy stuff:
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+ .scrapy
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+
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+ # Sphinx documentation
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+ docs/_build/
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+
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+ # PyBuilder
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+ target/
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+
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+ # IPython Notebook
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+ .ipynb_checkpoints
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+
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+ # pyenv
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+ .python-version
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+
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+ # celery beat schedule file
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+ celerybeat-schedule
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+
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+ # dotenv
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+ .env
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+
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+ # virtualenv
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+ venv/
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+ ENV/
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+
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+ # Spyder project settings
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+ .spyderproject
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+
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+ # Rope project settings
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+ .ropeproject
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+
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+ # VSCode
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+ .vscode
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+ # .readthedocs.yaml
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+ # Read the Docs configuration file
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+ # See https://docs.readthedocs.io/en/stable/config-file/v2.html for details
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+
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+ # Required
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+ version: 2
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+
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+ # Set the OS, Python version and other tools you might need
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+ build:
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+ os: ubuntu-22.04
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+ tools:
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+ python: "3.10"
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+
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+ # Build documentation in the "docs/" directory with Sphinx
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+ sphinx:
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+ configuration: docs/conf.py
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+
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+ # Optionally build your docs in additional formats such as PDF and ePub
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+ formats:
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+ - pdf
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+ - epub
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+
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+ # Optional but recommended, declare the Python requirements required
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+ # to build your documentation
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+ # See https://docs.readthedocs.io/en/stable/guides/reproducible-builds.html
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+ python:
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+ install:
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+ - requirements: docs/requirements.txt
SimplHDL-0.0.3/LICENSE ADDED
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+ MIT License
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+
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+ Copyright (c) 2024 SimplHDL
4
+
5
+ Permission is hereby granted, free of charge, to any person obtaining a copy
6
+ of this software and associated documentation files (the "Software"), to deal
7
+ in the Software without restriction, including without limitation the rights
8
+ to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
9
+ copies of the Software, and to permit persons to whom the Software is
10
+ furnished to do so, subject to the following conditions:
11
+
12
+ The above copyright notice and this permission notice shall be included in all
13
+ copies or substantial portions of the Software.
14
+
15
+ THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16
+ IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17
+ FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
18
+ AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19
+ LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20
+ OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21
+ SOFTWARE.
@@ -0,0 +1,166 @@
1
+ Metadata-Version: 2.1
2
+ Name: SimplHDL
3
+ Version: 0.0.3
4
+ Summary: A framework for simulating and implementing HDL designs
5
+ Author-email: Rasmus Grøndahl Olsen <simplhdl@gmail.com>
6
+ Maintainer-email: Rasmus Grøndahl Olsen <simplhdl@gmail.com>
7
+ License: MIT License
8
+
9
+ Copyright (c) 2024 SimplHDL
10
+
11
+ Permission is hereby granted, free of charge, to any person obtaining a copy
12
+ of this software and associated documentation files (the "Software"), to deal
13
+ in the Software without restriction, including without limitation the rights
14
+ to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
15
+ copies of the Software, and to permit persons to whom the Software is
16
+ furnished to do so, subject to the following conditions:
17
+
18
+ The above copyright notice and this permission notice shall be included in all
19
+ copies or substantial portions of the Software.
20
+
21
+ THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
22
+ IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
23
+ FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
24
+ AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
25
+ LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
26
+ OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
27
+ SOFTWARE.
28
+
29
+ Project-URL: Homepage, https://github.com/SimplHDL
30
+ Project-URL: Documentation, https://simplhdl.readthedocs.io/en/latest/
31
+ Project-URL: Repository, https://github.com/SimplHDL/simplhdl.git
32
+ Project-URL: Issues, https://github.com/SimplHDL/simplhdl/issues
33
+ Classifier: Development Status :: 4 - Beta
34
+ Classifier: Programming Language :: Python :: 3
35
+ Classifier: Programming Language :: Python :: 3.8
36
+ Classifier: Programming Language :: Python :: 3.9
37
+ Classifier: Programming Language :: Python :: 3.10
38
+ Classifier: Programming Language :: Python :: 3.11
39
+ Classifier: Programming Language :: Python :: 3.12
40
+ Classifier: Intended Audience :: Developers
41
+ Classifier: License :: OSI Approved :: MIT License
42
+ Classifier: Operating System :: OS Independent
43
+ Requires-Python: >=3.8
44
+ Description-Content-Type: text/markdown
45
+ License-File: LICENSE
46
+ Requires-Dist: importlib-resources; python_version < "3.9"
47
+ Requires-Dist: pySVModel==0.3.5
48
+ Requires-Dist: pyEDAA.ProjectModel==0.4.3
49
+ Requires-Dist: pyyaml
50
+ Requires-Dist: types-PyYAML
51
+ Requires-Dist: argcomplete
52
+ Requires-Dist: jinja2
53
+ Requires-Dist: GitPython
54
+
55
+ ## Introduction
56
+
57
+ SimplHDL is a plugin-based command-line application for simplifying FPGA and
58
+ ASIC development regardless of EDA tools and flows.
59
+
60
+ The goal is to embrase structured and reusable designs by creating a generic
61
+ project model that can be used in any hdl development flow regardless of
62
+ project structure and EDA tool requirements.
63
+
64
+ The plugin based architecture allows for SimplHDL to be migrated into any
65
+ existing project, replacing ad-hoc simulation and implmentation scripts while
66
+ providing a intuitive command-line interface for HDL design and verification
67
+ engineers.
68
+
69
+ I wide vararity of languges, standards and tools are supported.
70
+
71
+ ### HDL languages
72
+
73
+ * Verilog / System Verilog
74
+ * VHDL
75
+ * Chisel
76
+ * SystemRDL
77
+ * IPXact
78
+ * Vivado IP containters (.xci, .xcix)
79
+ * Quartus IP containers (.ip)
80
+
81
+ ### Methodologies
82
+
83
+ * UVM
84
+ * OSVMM
85
+ * UVVM
86
+ * Cocotb
87
+ * pyuvm
88
+
89
+ ### EDA Tools
90
+
91
+ * Vivado
92
+ * Quartus
93
+ * Modelsim
94
+ * Questasim
95
+ * Xsim
96
+ * Vcs
97
+ * Riviera Pro
98
+ * Xcelium (coming)
99
+ * Verilator (coming)
100
+ * Icarus (coming)
101
+ * GHDL (coming)
102
+
103
+ ## Getting Started
104
+
105
+ SimplHDL currently works on Linux and Windows WSL. It is written in Python and can
106
+ be installed with *pip*. To run SimplHDL Python 3.8 or later is required. The
107
+ tools for the flows you wish to run also need to be installed and set up
108
+ correctly in the shell environment. SimplHDL can be installed on your system's
109
+ Python installation, but it is highly recommended to install and run SimplHDL
110
+ in a Python virtual environment or a Conda environment.
111
+
112
+ ## Example
113
+
114
+ To quickly try out SimplHDL follow these steps. In this example, we will use
115
+ Vivado and QuestaSim. The prerequisites are that SimplHDL install installed and
116
+ Vivado and QuestaSim are correctly set up in your shell environment.
117
+
118
+ 1. Clone Git repository from GitHub
119
+
120
+ ```console
121
+ git clone https://github.com/SimplHDL/simplhdl.git
122
+ ```
123
+
124
+ 2. install SimplHDL from source
125
+
126
+ ```console
127
+ pip install ./simplhdl
128
+ ```
129
+
130
+ 3. Run simulation
131
+
132
+ ```console
133
+ cd simplhdl/examples/hdl/alu/sim
134
+ simpl questasim
135
+ ```
136
+
137
+ 4. Run simulation interactively in Gui.
138
+
139
+ ```console
140
+ cd simplhdl/examples/hdl/alu/sim
141
+ simpl questasim --gui
142
+ ```
143
+
144
+ 5. Run implementation
145
+
146
+ ```console
147
+ cd ../syn
148
+ simpl vivado
149
+ ```
150
+
151
+ 6. Run implementation interactively in Gui.
152
+
153
+ ```console
154
+ simpl vivado --gui
155
+ ```
156
+
157
+ In this example, the project specification is written in Yaml. This format is
158
+ only meant as a demonstration. To integrate SimplHDL into your project, you have
159
+ to write a parser plugin for your specific project specification format.
160
+ See the documentation and plugin examples for more information.
161
+
162
+ ## Links
163
+
164
+ * Homepage:
165
+ * Source: <https://github.com/SimplHDL/simplhdl>
166
+ * Tracker: <https://github.com/SimplHDL/simplhdl/issues>
@@ -0,0 +1,112 @@
1
+ ## Introduction
2
+
3
+ SimplHDL is a plugin-based command-line application for simplifying FPGA and
4
+ ASIC development regardless of EDA tools and flows.
5
+
6
+ The goal is to embrase structured and reusable designs by creating a generic
7
+ project model that can be used in any hdl development flow regardless of
8
+ project structure and EDA tool requirements.
9
+
10
+ The plugin based architecture allows for SimplHDL to be migrated into any
11
+ existing project, replacing ad-hoc simulation and implmentation scripts while
12
+ providing a intuitive command-line interface for HDL design and verification
13
+ engineers.
14
+
15
+ I wide vararity of languges, standards and tools are supported.
16
+
17
+ ### HDL languages
18
+
19
+ * Verilog / System Verilog
20
+ * VHDL
21
+ * Chisel
22
+ * SystemRDL
23
+ * IPXact
24
+ * Vivado IP containters (.xci, .xcix)
25
+ * Quartus IP containers (.ip)
26
+
27
+ ### Methodologies
28
+
29
+ * UVM
30
+ * OSVMM
31
+ * UVVM
32
+ * Cocotb
33
+ * pyuvm
34
+
35
+ ### EDA Tools
36
+
37
+ * Vivado
38
+ * Quartus
39
+ * Modelsim
40
+ * Questasim
41
+ * Xsim
42
+ * Vcs
43
+ * Riviera Pro
44
+ * Xcelium (coming)
45
+ * Verilator (coming)
46
+ * Icarus (coming)
47
+ * GHDL (coming)
48
+
49
+ ## Getting Started
50
+
51
+ SimplHDL currently works on Linux and Windows WSL. It is written in Python and can
52
+ be installed with *pip*. To run SimplHDL Python 3.8 or later is required. The
53
+ tools for the flows you wish to run also need to be installed and set up
54
+ correctly in the shell environment. SimplHDL can be installed on your system's
55
+ Python installation, but it is highly recommended to install and run SimplHDL
56
+ in a Python virtual environment or a Conda environment.
57
+
58
+ ## Example
59
+
60
+ To quickly try out SimplHDL follow these steps. In this example, we will use
61
+ Vivado and QuestaSim. The prerequisites are that SimplHDL install installed and
62
+ Vivado and QuestaSim are correctly set up in your shell environment.
63
+
64
+ 1. Clone Git repository from GitHub
65
+
66
+ ```console
67
+ git clone https://github.com/SimplHDL/simplhdl.git
68
+ ```
69
+
70
+ 2. install SimplHDL from source
71
+
72
+ ```console
73
+ pip install ./simplhdl
74
+ ```
75
+
76
+ 3. Run simulation
77
+
78
+ ```console
79
+ cd simplhdl/examples/hdl/alu/sim
80
+ simpl questasim
81
+ ```
82
+
83
+ 4. Run simulation interactively in Gui.
84
+
85
+ ```console
86
+ cd simplhdl/examples/hdl/alu/sim
87
+ simpl questasim --gui
88
+ ```
89
+
90
+ 5. Run implementation
91
+
92
+ ```console
93
+ cd ../syn
94
+ simpl vivado
95
+ ```
96
+
97
+ 6. Run implementation interactively in Gui.
98
+
99
+ ```console
100
+ simpl vivado --gui
101
+ ```
102
+
103
+ In this example, the project specification is written in Yaml. This format is
104
+ only meant as a demonstration. To integrate SimplHDL into your project, you have
105
+ to write a parser plugin for your specific project specification format.
106
+ See the documentation and plugin examples for more information.
107
+
108
+ ## Links
109
+
110
+ * Homepage:
111
+ * Source: <https://github.com/SimplHDL/simplhdl>
112
+ * Tracker: <https://github.com/SimplHDL/simplhdl/issues>
@@ -0,0 +1,65 @@
1
+ # Configuration file for the Sphinx documentation builder.
2
+ #
3
+ # For the full list of built-in configuration values, see the documentation:
4
+ # https://www.sphinx-doc.org/en/master/usage/configuration.html
5
+
6
+ # -- Project information -----------------------------------------------------
7
+ # https://www.sphinx-doc.org/en/master/usage/configuration.html#project-information
8
+
9
+ import sys
10
+ import time
11
+ from os import environ
12
+ from os.path import abspath, join
13
+ from pathlib import Path
14
+ from sphinx_pyproject import SphinxConfig
15
+ from simplhdl import __version__
16
+
17
+ sys.path.insert(0, abspath('.'))
18
+ sys.path.insert(0, abspath('..'))
19
+ sys.path.insert(0, abspath('../src/simplhdl'))
20
+
21
+ config = SphinxConfig(
22
+ "../pyproject.toml",
23
+ globalns=globals(),
24
+ config_overrides={'version': __version__})
25
+
26
+
27
+ project = name
28
+ copyright = f"2016-{time.strftime('%Y')}, {author}"
29
+ release = version
30
+
31
+ # -- General configuration ---------------------------------------------------
32
+ # https://www.sphinx-doc.org/en/master/usage/configuration.html#general-configuration
33
+
34
+ extensions = []
35
+
36
+ # templates_path = ['_templates']
37
+ exclude_patterns = ['_build', 'Thumbs.db', '.DS_Store']
38
+
39
+ # -- Options for HTML output -------------------------------------------------
40
+ # https://www.sphinx-doc.org/en/master/usage/configuration.html#options-for-html-output
41
+
42
+ html_theme = 'furo'
43
+ html_static_path = ['_static']
44
+ html_logo = join(abspath('.'), html_static_path[0], 'simplhdl_light_1.png')
45
+
46
+ html_theme_options = {
47
+ "source_repository": "https://github.com/SimplHDL/simplhdl",
48
+ "source_branch": environ.get("GITHUB_REF_NAME", "main"),
49
+ "source_directory": "",
50
+ "sidebar_hide_name": True,
51
+ "footer_icons": [
52
+ {
53
+ "name": "Gitter hdl/community",
54
+ "url": "https://gitter.im/hdl/community",
55
+ "html": "",
56
+ "class": "fa-solid fa-brands fa-gitter",
57
+ },
58
+ {
59
+ "name": "GitHub https://github.com/SimplHDL/simplhdl",
60
+ "url": "https://github.com/SimplHDL/simplhdl",
61
+ "html": "",
62
+ "class": "fa-solid fa-brands fa-github",
63
+ },
64
+ ],
65
+ }