PySHDL 0.1.4__tar.gz → 0.1.5__tar.gz

{pyshdl-0.1.4 → pyshdl-0.1.5}/PKG-INFO

@@ -1,6 +1,6 @@
 Metadata-Version: 2.4
 Name: PySHDL
-Version: 0.1.4
+Version: 0.1.5
 Summary: SHDL (Simple Hardware Description Language) is a minimal HDL designed for creating digital circuits and easily simulating them. It compiles directly to C for maximum performance and portability. PySHDL is the Python interface for SHDL.
 Project-URL: Homepage, https://github.com/rafa-rrayes/SHDL
 Project-URL: Repository, https://github.com/rafa-rrayes/SHDL

{pyshdl-0.1.4 → pyshdl-0.1.5}/pyproject.toml

@@ -1,6 +1,6 @@
 [project]
 name = "PySHDL"
-version = "0.1.4"
+version = "0.1.5"
 description = "SHDL (Simple Hardware Description Language) is a minimal HDL designed for creating digital circuits and easily simulating them. It compiles directly to C for maximum performance and portability. PySHDL is the Python interface for SHDL."
 readme = "README.md"
 authors = [

{pyshdl-0.1.4 → pyshdl-0.1.5}/src/PySHDL/shdlc.py

@@ -423,23 +423,52 @@ class SHDLParser:
 
         # --- Helpers -------------------------------------------------------------
 
+        def parse_pin_ref(pin: str):
+            """
+            Parse a pin reference into components.
+            Returns: (instance_name, port_name, bit_index) or (None, port_name, bit_index)
+            
+            Examples:
+                'inv.A[1]' -> ('inv', 'A', 1)
+                'fa1.Cout' -> ('fa1', 'Cout', None)
+                'A[5]' -> (None, 'A', 5)
+                'Sum' -> (None, 'Sum', None)
+            """
+            # Check for instance.port pattern
+            if '.' in pin:
+                inst_part, port_part = pin.split('.', 1)
+                # Check for bit index in port part
+                match = re.match(r'(\w+)\[(\d+)\]', port_part)
+                if match:
+                    return (inst_part, match.group(1), int(match.group(2)))
+                else:
+                    return (inst_part, port_part, None)
+            else:
+                # No instance, just port (possibly with bit index)
+                match = re.match(r'(\w+)\[(\d+)\]', pin)
+                if match:
+                    return (None, match.group(1), int(match.group(2)))
+                else:
+                    return (None, pin, None)
+
         def ports_of(defn: "Component"):
             return {p.name for p in defn.inputs}, {p.name for p in defn.outputs}
 
         def output_drivers(defn: "Component"):
             """
-            Map child output port -> internal driver pin (e.g., 'Sum' -> 'x2.O').
+            Map child output port (with optional bit index) -> internal driver pin.
+            Examples: 'Sum' -> 'x2.O', 'Y[1]' -> 'g1.O'
             """
             m = {}
             for src, dst in defn.connections:
-                if '.' not in dst:  # bare output port
+                if '.' not in dst:  # bare output port (possibly with bit index)
                     m[dst] = src
             return m
 
         def prefixed_internal(pin: str, inst_name: str):
             """
             Prefix internal instance pins: 'x1.O' -> 'fa1_x1.O'.
-            Leave bare ports ('A', 'Sum') unchanged (handled elsewhere).
+            Leave bare ports ('A', 'Sum', 'A[1]') unchanged (handled elsewhere).
             """
             if '.' in pin:
                 inst, port = pin.split('.', 1)
@@ -447,8 +476,12 @@ class SHDLParser:
             return pin
 
         def is_abstract_pin(token: str):
-            # an abstract pin looks like 'fa1.Cin' or 'fa1.Cout'
-            return '.' in token and '[' not in token and token.count('.') == 1
+            """
+            Check if token is an abstract pin reference (references an instance).
+            Examples: 'fa1.Cin', 'inv.A[1]' -> True
+                     'A[1]', 'Sum' -> False
+            """
+            return '.' in token
 
         # Index original connections
         conns_from = defaultdict(list)
@@ -479,38 +512,50 @@ class SHDLParser:
                 "out_drivers": out_drv,
             }
 
-        # Global maps for substitution
+        # Global maps for substitution with bit-indexed support
         # (1) Abstract OUTPUT -> concrete internal driver pin (prefixed)
         abstract_out_to_driver = {}
         for inst in instances_to_inline:
             meta = inlined_meta[inst.name]
             for outp, driver_pin in meta["out_drivers"].items():
-                abstract = f"{inst.name}.{outp}"               # e.g., 'fa1.Cout'
-                concrete = prefixed_internal(driver_pin, inst.name)  # 'fa1_o1.O'
+                # outp might be 'Y[1]' or 'Cout'
+                abstract = f"{inst.name}.{outp}"
+                concrete = prefixed_internal(driver_pin, inst.name)
                 abstract_out_to_driver[abstract] = concrete
 
         def resolve_output_ref(token: str) -> str:
-            """Replace 'inst.OutPort' with its internal driver pin, repeatedly if needed."""
+            """Replace 'inst.OutPort' or 'inst.OutPort[i]' with its internal driver pin."""
             while token in abstract_out_to_driver:
                 token = abstract_out_to_driver[token]
             return token
 
         # (2) Abstract INPUT -> resolved external net (after output resolution)
+        # Now handles bit-indexed inputs like 'inv.A[1]'
         abstract_in_to_net = {}
         for inst in instances_to_inline:
             meta = inlined_meta[inst.name]
+            
+            # For each input port, check all possible bit-indexed references
             for inp in meta["in_ports"]:
-                abs_input = f"{inst.name}.{inp}"  # e.g., 'fa2.Cin'
+                # First check non-indexed reference
+                abs_input = f"{inst.name}.{inp}"
                 if abs_input in conns_to and conns_to[abs_input]:
-                    upstream = conns_to[abs_input][-1][0]  # last writer wins
-                    upstream = resolve_output_ref(upstream)  # resolve if it was 'faX.Out'
+                    upstream = conns_to[abs_input][-1][0]
+                    upstream = resolve_output_ref(upstream)
                     abstract_in_to_net[abs_input] = upstream
-                else:
-                    # Unconnected input; leave unmapped. (Could default/raise as needed.)
-                    pass
+                
+                # Also check for bit-indexed references in the connections
+                for conn_dst in conns_to.keys():
+                    inst_name, port_name, bit_idx = parse_pin_ref(conn_dst)
+                    if inst_name == inst.name and port_name == inp and bit_idx is not None:
+                        # This is a bit-indexed reference to this instance's input
+                        if conns_to[conn_dst]:
+                            upstream = conns_to[conn_dst][-1][0]
+                            upstream = resolve_output_ref(upstream)
+                            abstract_in_to_net[conn_dst] = upstream
 
         def resolve_input_ref(token: str) -> str:
-            """Replace 'inst.InPort' with its resolved external net, repeatedly if needed."""
+            """Replace 'inst.InPort' or 'inst.InPort[i]' with its resolved external net."""
             seen = set()
             while token in abstract_in_to_net and token not in seen:
                 seen.add(token)
@@ -522,10 +567,10 @@ class SHDLParser:
         def is_inlined_abstract_input(dst: str) -> bool:
             if not is_abstract_pin(dst):
                 return False
-            inst_name, port = dst.split('.', 1)
+            inst_name, port_name, bit_idx = parse_pin_ref(dst)
             if inst_name not in inlined_meta:
                 return False
-            return port in inlined_meta[inst_name]["in_ports"]
+            return port_name in inlined_meta[inst_name]["in_ports"]
 
         # Bring in internals for each inlined child
         for inst in instances_to_inline:
@@ -546,18 +591,31 @@ class SHDLParser:
                         if s not in merged_imports[lib]:
                             merged_imports[lib].append(s)
 
-            # (c) Recreate child's internal wiring with substitutions:
-            #     - child input ports -> resolved external net (input map)
-            #     - internal pins -> prefixed_internal(...)
-            #     - child output ports are NOT emitted as ports (we wire their drivers elsewhere)
-            input_external = {p: abstract_in_to_net.get(f"{inst.name}.{p}") for p in meta["in_ports"]}
+            # (c) Recreate child's internal wiring with substitutions
+            # Build input mapping: for each child input port (with possible bit index),
+            # find what it should map to from the parent's connections
+            input_external = {}
+            
+            # Check direct port mappings (non-indexed)
+            for p in meta["in_ports"]:
+                abs_ref = f"{inst.name}.{p}"
+                if abs_ref in abstract_in_to_net:
+                    input_external[p] = abstract_in_to_net[abs_ref]
+            
+            # Check bit-indexed port mappings
+            for conn_dst in abstract_in_to_net.keys():
+                inst_name, port_name, bit_idx = parse_pin_ref(conn_dst)
+                if inst_name == inst.name and port_name in meta["in_ports"] and bit_idx is not None:
+                    # Store with the bit index: 'A[1]' -> upstream net
+                    port_with_idx = f"{port_name}[{bit_idx}]"
+                    input_external[port_with_idx] = abstract_in_to_net[conn_dst]
 
             for src, dst in child_def.connections:
                 # Resolve source
-                if '.' not in src:  # child input port
+                if '.' not in src:  # child input port (may have bit index)
                     upstream = input_external.get(src)
                     if upstream is None:
-                        # Skip unconnected; or raise if strict is desired
+                        # Skip unconnected
                         continue
                     flat_src = resolve_output_ref(upstream)
                 else:
@@ -571,20 +629,26 @@ class SHDLParser:
                     flat_dst = prefixed_internal(dst, inst.name)
                     new_connections.append((flat_src, flat_dst))
 
-            # (d) Rewire parent edges that referenced child OUTPUTS (e.g., 'fa1.Cout' -> X)
-            #     But do NOT create edges into abstract inputs of other inlined children
-            #     (those will be realized by that child's own internal wiring above).
+            # (d) Rewire parent edges that referenced child OUTPUTS
             for outp in meta["out_ports"]:
+                # Check non-indexed outputs
                 abs_out = f"{inst.name}.{outp}"
-                if abs_out not in conns_from:
-                    continue
-                driver = resolve_output_ref(abs_out)  # should give prefixed internal pin
-                for (_src, dst) in conns_from[abs_out]:
-                    if is_inlined_abstract_input(dst):
-                        # Skip; the receiving child will handle via its internal mapping.
-                        continue
-                    # Otherwise, we can keep the destination:
-                    new_connections.append((driver, dst))
+                if abs_out in conns_from:
+                    driver = resolve_output_ref(abs_out)
+                    for (_src, dst) in conns_from[abs_out]:
+                        if is_inlined_abstract_input(dst):
+                            continue
+                        new_connections.append((driver, dst))
+                
+                # Check bit-indexed outputs
+                for conn_src in conns_from.keys():
+                    inst_name, port_name, bit_idx = parse_pin_ref(conn_src)
+                    if inst_name == inst.name and port_name == outp and bit_idx is not None:
+                        driver = resolve_output_ref(conn_src)
+                        for (_src, dst) in conns_from[conn_src]:
+                            if is_inlined_abstract_input(dst):
+                                continue
+                            new_connections.append((driver, dst))
 
         # Keep original parent connections that don't touch any abstract pins of inlined children
         abstract_pins = set()
@@ -592,6 +656,13 @@ class SHDLParser:
             meta = inlined_meta[inst.name]
             for p in meta["in_ports"] | meta["out_ports"]:
                 abstract_pins.add(f"{inst.name}.{p}")
+        
+        # Also add bit-indexed versions
+        for conn in parent.connections:
+            for pin in [conn[0], conn[1]]:
+                inst_name, port_name, bit_idx = parse_pin_ref(pin)
+                if inst_name and inst_name in inlined_meta:
+                    abstract_pins.add(pin)
 
         def touches_any_abstract(conn):
             s, d = conn
@@ -605,15 +676,15 @@ class SHDLParser:
         finalized = []
         for s, d in new_connections:
             s2 = resolve_output_ref(s)
-            s2 = resolve_input_ref(s2)   # just in case a chain pointed to an abstract input
-            d2 = resolve_output_ref(d)   # unlikely for destinations, but safe
+            s2 = resolve_input_ref(s2)
+            d2 = resolve_output_ref(d)
             d2 = resolve_input_ref(d2)
-            # Drop any connection that still targets an abstract input (shouldn't happen)
+            # Drop any connection that still targets an abstract input
             if is_inlined_abstract_input(d2):
                 continue
             finalized.append((s2, d2))
 
-        # Optional: prune imports of fully inlined component types (e.g., 'FullAdder')
+        # Optional: prune imports of fully inlined component types
         if merged_imports:
             cleaned_imports = {}
             for lib, syms in merged_imports.items():