PySHDL 0.1.3__tar.gz → 0.1.5__tar.gz

{pyshdl-0.1.3 → pyshdl-0.1.5}/.gitignore

@@ -1,4 +1,5 @@
 .gitignore
+
 # Python-generated files
 __pycache__/
 *.py[oc]
@@ -13,4 +14,5 @@ wheels/
 
 *.c
 *.so
-.python-version
+.python-version
+.DS_Store

{pyshdl-0.1.3 → pyshdl-0.1.5}/DOCS.md

@@ -191,6 +191,72 @@ A[1]    # LSB of A
 A[8]    # MSB of 8-bit A
 ```
 
+### Constants
+
+Constants allow you to define named values that can be used throughout your component definition. This makes your code more maintainable and easier to parameterize.
+
+**Syntax:**
+
+```shdl
+CONSTANT_NAME = value;
+```
+
+Where `value` can be:
+- Decimal: `WIDTH = 16;`
+- Binary: `MASK = 0b1111;`
+- Hexadecimal: `FLAGS = 0xFF;`
+
+**Rules:**
+- Constant names must be all uppercase with underscores (e.g., `WIDTH`, `BUS_SIZE`, `NUM_GATES`)
+- Any uppercase identifier followed by `= number;` is treated as a constant
+- Constants must be declared inside the component body, before their use
+- Constant values must be non-negative integers
+- Constants are substituted before generator expansion
+
+**Usage:**
+
+Constants can be used in two ways:
+
+1. **As scalar values** in connections (for constants 0 or 1):
+```shdl
+TRUE = 1;
+FALSE = 0;
+A -> gate1.A;
+TRUE -> gate1.B;  # Ties input B to constant 1
+```
+
+2. **As bit-indexed vectors** in connections:
+```shdl
+COMP = 7;  # 0b111 in binary
+COMP[1] -> gate1.A;  # Bit 1 (LSB) of COMP
+COMP[2] -> gate2.A;  # Bit 2 of COMP
+COMP[3] -> gate3.A;  # Bit 3 (MSB) of COMP
+```
+
+**Example:**
+
+```shdl
+component ParamAdder(A[16], B[16], Cin) -> (Sum[16], Cout) {
+    WIDTH = 16;
+    LAST_BIT = 16;
+    
+    # Create WIDTH full adders
+    >i[WIDTH]{
+        fa{i}: FullAdder;
+    }
+    
+    connect {
+        # ... connections using WIDTH and LAST_BIT ...
+    }
+}
+```
+
+**Use Cases:**
+- Defining bus widths: `BUS_WIDTH = 32;`
+- Setting array sizes: `>i[BUS_WIDTH]{ ... }`
+- Parameterizing generator ranges: `>i[1, WIDTH]{ ... }`
+- Making components more maintainable and reusable
+
 ---
 
 ## Imports and Modules

{pyshdl-0.1.3 → pyshdl-0.1.5}/PKG-INFO

@@ -1,6 +1,6 @@
 Metadata-Version: 2.4
 Name: PySHDL
-Version: 0.1.3
+Version: 0.1.5
 Summary: SHDL (Simple Hardware Description Language) is a minimal HDL designed for creating digital circuits and easily simulating them. It compiles directly to C for maximum performance and portability. PySHDL is the Python interface for SHDL.
 Project-URL: Homepage, https://github.com/rafa-rrayes/SHDL
 Project-URL: Repository, https://github.com/rafa-rrayes/SHDL
@@ -20,6 +20,7 @@ A lightweight hardware description language and Python driver for digital circui
 - ⚡ **C Backend** - Compiles to optimized C code for fast simulation and portability
 - 🔧 **Command Line Tools** - Built-in compiler and utilities
 - 📦 **Component Reuse** - Import and compose reusable circuit components
+- 🔢 **Constants Support** - Use named constants for parameterizable designs
 
 ## Installation
 
@@ -128,7 +129,7 @@ See the `examples/` directory for more complete examples:
 
 ## Documentation
 Github repository: [rafa-rrayes/SHDL](https://github.com/rafa-rrayes/SHDL)
-For more detailed documentation, see [DOCS.md](DOCS.md).
+For more detailed documentation, see [DOCS.md](https://github.com/rafa-rrayes/SHDL/blob/master/DOCS.md)
 
 ## Requirements
 

{pyshdl-0.1.3 → pyshdl-0.1.5}/README.md

@@ -9,6 +9,7 @@ A lightweight hardware description language and Python driver for digital circui
 - ⚡ **C Backend** - Compiles to optimized C code for fast simulation and portability
 - 🔧 **Command Line Tools** - Built-in compiler and utilities
 - 📦 **Component Reuse** - Import and compose reusable circuit components
+- 🔢 **Constants Support** - Use named constants for parameterizable designs
 
 ## Installation
 
@@ -117,7 +118,7 @@ See the `examples/` directory for more complete examples:
 
 ## Documentation
 Github repository: [rafa-rrayes/SHDL](https://github.com/rafa-rrayes/SHDL)
-For more detailed documentation, see [DOCS.md](DOCS.md).
+For more detailed documentation, see [DOCS.md](https://github.com/rafa-rrayes/SHDL/blob/master/DOCS.md)
 
 ## Requirements
 

pyshdl-0.1.5/examples/SHDL_components/compare7.shdl

@@ -0,0 +1,23 @@
+use stdgates::{AND};
+
+component Comp7(A[3]) -> (True) {
+    COMP = 7;  # 0b111
+    
+    >i[3]{
+        and{i}: AND;
+    }
+    and_out1: AND;
+    and_out2: AND;
+    
+    connect {
+        >i[3]{
+            A[{i}] -> and{i}.A;
+            COMP[{i}] -> and{i}.B;
+        }
+        and1.O -> and_out1.A;
+        and2.O -> and_out1.B;
+        and_out1.O -> and_out2.A;
+        and3.O -> and_out2.B;
+        and_out2.O -> True;
+    }
+}

{pyshdl-0.1.3 → pyshdl-0.1.5}/examples/interacting.py

@@ -1,5 +1,14 @@
 from PySHDL import Circuit
 
+def test_comp7():
+    circuit = Circuit("examples/SHDL_components/compare7.shdl")
+
+    for val in range(8):
+        circuit.poke("A", val)
+        circuit.step(10)
+        result = circuit.peek("True")
+        print(f"Compare7 input: {val}, output: {result}")
+
 def test_register16():
     circuit = Circuit("examples/SHDL_components/reg16.shdl")
 
@@ -37,4 +46,5 @@ if __name__ == "__main__":
     result = circuit.peek("Sum")
 
     print(f"{A} + {B} + {Cin} = {result}, expected {A + B + Cin}")
-    test_register16()
+    test_register16()
+    test_comp7()

{pyshdl-0.1.3 → pyshdl-0.1.5}/pyproject.toml

@@ -1,6 +1,6 @@
 [project]
 name = "PySHDL"
-version = "0.1.3"
+version = "0.1.5"
 description = "SHDL (Simple Hardware Description Language) is a minimal HDL designed for creating digital circuits and easily simulating them. It compiles directly to C for maximum performance and portability. PySHDL is the Python interface for SHDL."
 readme = "README.md"
 authors = [

{pyshdl-0.1.3 → pyshdl-0.1.5}/src/PySHDL/__init__.py

@@ -1,4 +1,4 @@
-"""PySHDL library."""
+"""shdl library."""
 
 from importlib import import_module
 from importlib.metadata import PackageNotFoundError, version
@@ -16,6 +16,6 @@ __all__ = [
     "__version__",
 ]
 try:
-    __version__ = version("PySHDL")
+    __version__ = version("shdl")
 except PackageNotFoundError:
     __version__ = "0.0.0"

{pyshdl-0.1.3 → pyshdl-0.1.5}/src/PySHDL/shdlc.py

@@ -59,6 +59,7 @@ class Component:
     instances: List[Instance] = field(default_factory=list)
     connections: List[Tuple[str, str]] = field(default_factory=list)  # (from, to)
     imports: Dict[str, List[str]] = field(default_factory=dict)  # module -> [components]
+    constants: Dict[str, int] = field(default_factory=dict)  # constant_name -> value
 
 
 class SHDLParser:
@@ -142,6 +143,9 @@ class SHDLParser:
         # Parse outputs
         comp.outputs = self._parse_ports(outputs_str, is_input=False)
         
+        # Parse constants
+        comp.constants = self._parse_constants(body)
+        
         # Parse body (instances and connections)
         self._parse_body(comp, body)
         
@@ -171,11 +175,81 @@ class SHDLParser:
         
         return ports
     
+    def _parse_constants(self, body: str) -> Dict[str, int]:
+        """
+        Parse constant declarations from component body.
+        Syntax: NAME = value;
+        Example: WIDTH = 16; or COMP = 0b111; or MASK = 0xFF;
+        Constants are identified by uppercase names.
+        Supports decimal, binary (0b), and hexadecimal (0x) literals.
+        """
+        constants = {}
+        
+        # Match: UPPERCASE_NAME = value;
+        # Constants must be all uppercase with optional underscores
+        # Value can be: decimal (123), binary (0b1010), or hex (0xAF)
+        pattern = r'([A-Z_][A-Z0-9_]*)\s*=\s*(0[bB][01]+|0[xX][0-9a-fA-F]+|\d+)\s*;'
+        
+        for match in re.finditer(pattern, body):
+            name = match.group(1)
+            value_str = match.group(2)
+            
+            # Parse the value based on prefix
+            if value_str.startswith(('0b', '0B')):
+                value = int(value_str[2:], 2)  # Binary
+            elif value_str.startswith(('0x', '0X')):
+                value = int(value_str[2:], 16)  # Hexadecimal
+            else:
+                value = int(value_str)  # Decimal
+            
+            constants[name] = value
+        
+        return constants
+    
+    def _add_constant_drivers(self, comp: Component, body: str):
+        """
+        Build a mapping of constant bit signals to their values (VCC/GND).
+        This will be used to resolve references during connection parsing.
+        """
+        # Find all synthetic constant bit signals in the body
+        const_bit_pattern = r'__const_([A-Z_][A-Z0-9_]*)_bit_(\d+)'
+        matches = re.findall(const_bit_pattern, body)
+        
+        # Build mapping: signal_name -> '__VCC' or '__GND'
+        const_bit_map = {}
+        
+        for const_name, bit_str in matches:
+            bit_index = int(bit_str)
+            
+            # Get the constant value
+            if const_name not in comp.constants:
+                continue
+            
+            const_value = comp.constants[const_name]
+            
+            # Extract the bit value (1-indexed, LSB is bit 1)
+            bit_value = (const_value >> (bit_index - 1)) & 1
+            
+            # Create a signal name for this constant bit
+            signal_name = f'__const_{const_name}_bit_{bit_index}'
+            
+            # Map to VCC or GND
+            const_bit_map[signal_name] = '__VCC' if bit_value == 1 else '__GND'
+        
+        # Store the mapping in the component for use during connection parsing
+        comp.constants_bit_map = const_bit_map
+    
     def _parse_body(self, comp: Component, body: str):
         """Parse component body (instances and connections)."""
-        # Expand generators first
+        # Substitute constants first
+        body = self._substitute_constants(body, comp.constants)
+        
+        # Expand generators
         body = self._expand_generators(body)
         
+        # Add constant bit drivers AFTER generator expansion
+        self._add_constant_drivers(comp, body)
+        
         # Split into instances and connections
         connect_match = re.search(r'connect\s*\{(.*)\}', body, re.DOTALL)
         
@@ -192,6 +266,44 @@ class SHDLParser:
         # Parse connections
         self._parse_connections(comp, connections_part)
     
+    def _substitute_constants(self, body: str, constants: Dict[str, int]) -> str:
+        """
+        Substitute constant names with their values in the body.
+        Constants can be used:
+        1. As scalar values in connections: TRUE -> a1.B;  (becomes __VCC or __GND)
+        2. As bit-indexed vectors: COMP[{i}] -> gate.A;  (becomes __const_COMP_bit_N)
+        """
+        # Remove constant declarations from the body
+        body = re.sub(r'[A-Z_][A-Z0-9_]*\s*=\s*(?:0[bB][01]+|0[xX][0-9a-fA-F]+|\d+)\s*;', '', body)
+        
+        # For each constant, we need to handle two cases:
+        # 1. Direct usage: CONSTANT_NAME (not followed by [)
+        # 2. Bit-indexed usage: CONSTANT_NAME[index]
+        
+        for const_name, const_value in constants.items():
+            # Case 1: Bit-indexed usage CONST[N] - convert to synthetic signal name
+            # CONST[1] becomes __const_CONST_bit_1, CONST[2] becomes __const_CONST_bit_2, etc.
+            def replace_bit_index(match):
+                bit_index = match.group(1)
+                return f'__const_{const_name}_bit_{bit_index}'
+            
+            # Replace CONST[...] with synthetic signal name
+            body = re.sub(rf'\b{const_name}\[([^\]]+)\]', replace_bit_index, body)
+            
+            # Case 2: Direct scalar usage - replace with __VCC or __GND for 0/1, 
+            # or leave as numeric value for other constants
+            # Use word boundaries to avoid partial matches
+            if const_value == 0:
+                body = re.sub(r'\b' + const_name + r'\b', '__GND', body)
+            elif const_value == 1:
+                body = re.sub(r'\b' + const_name + r'\b', '__VCC', body)
+            else:
+                # For other values, replace with the numeric value
+                # This is useful for parameterization in generators
+                body = re.sub(r'\b' + const_name + r'\b', str(const_value), body)
+        
+        return body
+    
     def _expand_generators(self, body: str) -> str:
         """
         Expand generator syntax:
@@ -269,9 +381,19 @@ class SHDLParser:
         # Match: signal -> port;
         pattern = r'([^\s;]+)\s*->\s*([^\s;]+)\s*;'
         
+        # Get the constant bit mapping if it exists
+        const_bit_map = getattr(comp, 'constants_bit_map', {})
+        
         for match in re.finditer(pattern, connections_str):
             from_sig = match.group(1).strip()
             to_sig = match.group(2).strip()
+            
+            # Resolve constant bit signals to VCC/GND
+            if from_sig in const_bit_map:
+                from_sig = const_bit_map[from_sig]
+            if to_sig in const_bit_map:
+                to_sig = const_bit_map[to_sig]
+            
             comp.connections.append((from_sig, to_sig))
     
     def _load_imports(self, comp: Component, base_path: Path):
@@ -301,23 +423,52 @@ class SHDLParser:
 
         # --- Helpers -------------------------------------------------------------
 
+        def parse_pin_ref(pin: str):
+            """
+            Parse a pin reference into components.
+            Returns: (instance_name, port_name, bit_index) or (None, port_name, bit_index)
+            
+            Examples:
+                'inv.A[1]' -> ('inv', 'A', 1)
+                'fa1.Cout' -> ('fa1', 'Cout', None)
+                'A[5]' -> (None, 'A', 5)
+                'Sum' -> (None, 'Sum', None)
+            """
+            # Check for instance.port pattern
+            if '.' in pin:
+                inst_part, port_part = pin.split('.', 1)
+                # Check for bit index in port part
+                match = re.match(r'(\w+)\[(\d+)\]', port_part)
+                if match:
+                    return (inst_part, match.group(1), int(match.group(2)))
+                else:
+                    return (inst_part, port_part, None)
+            else:
+                # No instance, just port (possibly with bit index)
+                match = re.match(r'(\w+)\[(\d+)\]', pin)
+                if match:
+                    return (None, match.group(1), int(match.group(2)))
+                else:
+                    return (None, pin, None)
+
         def ports_of(defn: "Component"):
             return {p.name for p in defn.inputs}, {p.name for p in defn.outputs}
 
         def output_drivers(defn: "Component"):
             """
-            Map child output port -> internal driver pin (e.g., 'Sum' -> 'x2.O').
+            Map child output port (with optional bit index) -> internal driver pin.
+            Examples: 'Sum' -> 'x2.O', 'Y[1]' -> 'g1.O'
             """
             m = {}
             for src, dst in defn.connections:
-                if '.' not in dst:  # bare output port
+                if '.' not in dst:  # bare output port (possibly with bit index)
                     m[dst] = src
             return m
 
         def prefixed_internal(pin: str, inst_name: str):
             """
             Prefix internal instance pins: 'x1.O' -> 'fa1_x1.O'.
-            Leave bare ports ('A', 'Sum') unchanged (handled elsewhere).
+            Leave bare ports ('A', 'Sum', 'A[1]') unchanged (handled elsewhere).
             """
             if '.' in pin:
                 inst, port = pin.split('.', 1)
@@ -325,8 +476,12 @@ class SHDLParser:
             return pin
 
         def is_abstract_pin(token: str):
-            # an abstract pin looks like 'fa1.Cin' or 'fa1.Cout'
-            return '.' in token and '[' not in token and token.count('.') == 1
+            """
+            Check if token is an abstract pin reference (references an instance).
+            Examples: 'fa1.Cin', 'inv.A[1]' -> True
+                     'A[1]', 'Sum' -> False
+            """
+            return '.' in token
 
         # Index original connections
         conns_from = defaultdict(list)
@@ -357,38 +512,50 @@ class SHDLParser:
                 "out_drivers": out_drv,
             }
 
-        # Global maps for substitution
+        # Global maps for substitution with bit-indexed support
         # (1) Abstract OUTPUT -> concrete internal driver pin (prefixed)
         abstract_out_to_driver = {}
         for inst in instances_to_inline:
             meta = inlined_meta[inst.name]
             for outp, driver_pin in meta["out_drivers"].items():
-                abstract = f"{inst.name}.{outp}"               # e.g., 'fa1.Cout'
-                concrete = prefixed_internal(driver_pin, inst.name)  # 'fa1_o1.O'
+                # outp might be 'Y[1]' or 'Cout'
+                abstract = f"{inst.name}.{outp}"
+                concrete = prefixed_internal(driver_pin, inst.name)
                 abstract_out_to_driver[abstract] = concrete
 
         def resolve_output_ref(token: str) -> str:
-            """Replace 'inst.OutPort' with its internal driver pin, repeatedly if needed."""
+            """Replace 'inst.OutPort' or 'inst.OutPort[i]' with its internal driver pin."""
             while token in abstract_out_to_driver:
                 token = abstract_out_to_driver[token]
             return token
 
         # (2) Abstract INPUT -> resolved external net (after output resolution)
+        # Now handles bit-indexed inputs like 'inv.A[1]'
         abstract_in_to_net = {}
         for inst in instances_to_inline:
             meta = inlined_meta[inst.name]
+            
+            # For each input port, check all possible bit-indexed references
             for inp in meta["in_ports"]:
-                abs_input = f"{inst.name}.{inp}"  # e.g., 'fa2.Cin'
+                # First check non-indexed reference
+                abs_input = f"{inst.name}.{inp}"
                 if abs_input in conns_to and conns_to[abs_input]:
-                    upstream = conns_to[abs_input][-1][0]  # last writer wins
-                    upstream = resolve_output_ref(upstream)  # resolve if it was 'faX.Out'
+                    upstream = conns_to[abs_input][-1][0]
+                    upstream = resolve_output_ref(upstream)
                     abstract_in_to_net[abs_input] = upstream
-                else:
-                    # Unconnected input; leave unmapped. (Could default/raise as needed.)
-                    pass
+                
+                # Also check for bit-indexed references in the connections
+                for conn_dst in conns_to.keys():
+                    inst_name, port_name, bit_idx = parse_pin_ref(conn_dst)
+                    if inst_name == inst.name and port_name == inp and bit_idx is not None:
+                        # This is a bit-indexed reference to this instance's input
+                        if conns_to[conn_dst]:
+                            upstream = conns_to[conn_dst][-1][0]
+                            upstream = resolve_output_ref(upstream)
+                            abstract_in_to_net[conn_dst] = upstream
 
         def resolve_input_ref(token: str) -> str:
-            """Replace 'inst.InPort' with its resolved external net, repeatedly if needed."""
+            """Replace 'inst.InPort' or 'inst.InPort[i]' with its resolved external net."""
             seen = set()
             while token in abstract_in_to_net and token not in seen:
                 seen.add(token)
@@ -400,10 +567,10 @@ class SHDLParser:
         def is_inlined_abstract_input(dst: str) -> bool:
             if not is_abstract_pin(dst):
                 return False
-            inst_name, port = dst.split('.', 1)
+            inst_name, port_name, bit_idx = parse_pin_ref(dst)
             if inst_name not in inlined_meta:
                 return False
-            return port in inlined_meta[inst_name]["in_ports"]
+            return port_name in inlined_meta[inst_name]["in_ports"]
 
         # Bring in internals for each inlined child
         for inst in instances_to_inline:
@@ -424,18 +591,31 @@ class SHDLParser:
                         if s not in merged_imports[lib]:
                             merged_imports[lib].append(s)
 
-            # (c) Recreate child's internal wiring with substitutions:
-            #     - child input ports -> resolved external net (input map)
-            #     - internal pins -> prefixed_internal(...)
-            #     - child output ports are NOT emitted as ports (we wire their drivers elsewhere)
-            input_external = {p: abstract_in_to_net.get(f"{inst.name}.{p}") for p in meta["in_ports"]}
+            # (c) Recreate child's internal wiring with substitutions
+            # Build input mapping: for each child input port (with possible bit index),
+            # find what it should map to from the parent's connections
+            input_external = {}
+            
+            # Check direct port mappings (non-indexed)
+            for p in meta["in_ports"]:
+                abs_ref = f"{inst.name}.{p}"
+                if abs_ref in abstract_in_to_net:
+                    input_external[p] = abstract_in_to_net[abs_ref]
+            
+            # Check bit-indexed port mappings
+            for conn_dst in abstract_in_to_net.keys():
+                inst_name, port_name, bit_idx = parse_pin_ref(conn_dst)
+                if inst_name == inst.name and port_name in meta["in_ports"] and bit_idx is not None:
+                    # Store with the bit index: 'A[1]' -> upstream net
+                    port_with_idx = f"{port_name}[{bit_idx}]"
+                    input_external[port_with_idx] = abstract_in_to_net[conn_dst]
 
             for src, dst in child_def.connections:
                 # Resolve source
-                if '.' not in src:  # child input port
+                if '.' not in src:  # child input port (may have bit index)
                     upstream = input_external.get(src)
                     if upstream is None:
-                        # Skip unconnected; or raise if strict is desired
+                        # Skip unconnected
                         continue
                     flat_src = resolve_output_ref(upstream)
                 else:
@@ -449,20 +629,26 @@ class SHDLParser:
                     flat_dst = prefixed_internal(dst, inst.name)
                     new_connections.append((flat_src, flat_dst))
 
-            # (d) Rewire parent edges that referenced child OUTPUTS (e.g., 'fa1.Cout' -> X)
-            #     But do NOT create edges into abstract inputs of other inlined children
-            #     (those will be realized by that child's own internal wiring above).
+            # (d) Rewire parent edges that referenced child OUTPUTS
             for outp in meta["out_ports"]:
+                # Check non-indexed outputs
                 abs_out = f"{inst.name}.{outp}"
-                if abs_out not in conns_from:
-                    continue
-                driver = resolve_output_ref(abs_out)  # should give prefixed internal pin
-                for (_src, dst) in conns_from[abs_out]:
-                    if is_inlined_abstract_input(dst):
-                        # Skip; the receiving child will handle via its internal mapping.
-                        continue
-                    # Otherwise, we can keep the destination:
-                    new_connections.append((driver, dst))
+                if abs_out in conns_from:
+                    driver = resolve_output_ref(abs_out)
+                    for (_src, dst) in conns_from[abs_out]:
+                        if is_inlined_abstract_input(dst):
+                            continue
+                        new_connections.append((driver, dst))
+                
+                # Check bit-indexed outputs
+                for conn_src in conns_from.keys():
+                    inst_name, port_name, bit_idx = parse_pin_ref(conn_src)
+                    if inst_name == inst.name and port_name == outp and bit_idx is not None:
+                        driver = resolve_output_ref(conn_src)
+                        for (_src, dst) in conns_from[conn_src]:
+                            if is_inlined_abstract_input(dst):
+                                continue
+                            new_connections.append((driver, dst))
 
         # Keep original parent connections that don't touch any abstract pins of inlined children
         abstract_pins = set()
@@ -470,6 +656,13 @@ class SHDLParser:
             meta = inlined_meta[inst.name]
             for p in meta["in_ports"] | meta["out_ports"]:
                 abstract_pins.add(f"{inst.name}.{p}")
+        
+        # Also add bit-indexed versions
+        for conn in parent.connections:
+            for pin in [conn[0], conn[1]]:
+                inst_name, port_name, bit_idx = parse_pin_ref(pin)
+                if inst_name and inst_name in inlined_meta:
+                    abstract_pins.add(pin)
 
         def touches_any_abstract(conn):
             s, d = conn
@@ -483,15 +676,15 @@ class SHDLParser:
         finalized = []
         for s, d in new_connections:
             s2 = resolve_output_ref(s)
-            s2 = resolve_input_ref(s2)   # just in case a chain pointed to an abstract input
-            d2 = resolve_output_ref(d)   # unlikely for destinations, but safe
+            s2 = resolve_input_ref(s2)
+            d2 = resolve_output_ref(d)
             d2 = resolve_input_ref(d2)
-            # Drop any connection that still targets an abstract input (shouldn't happen)
+            # Drop any connection that still targets an abstract input
             if is_inlined_abstract_input(d2):
                 continue
             finalized.append((s2, d2))
 
-        # Optional: prune imports of fully inlined component types (e.g., 'FullAdder')
+        # Optional: prune imports of fully inlined component types
         if merged_imports:
             cleaned_imports = {}
             for lib, syms in merged_imports.items():
@@ -666,6 +859,17 @@ def generate_c_code(component: Component) -> str:
         # constant zero for unconnected pins?
         if src == CONST_ZERO:
             return '0u'
+        # VCC (constant 1)?
+        if src == '__VCC':
+            return '1u'
+        # GND (constant 0)?
+        if src == '__GND':
+            return '0u'
+        # Synthetic constant bit signal?
+        if src.startswith('__const_'):
+            # These should have been resolved to __VCC or __GND via connections
+            # but if we see them here directly, treat as error
+            raise ValueError(f'Unresolved constant signal: {src}')
         # input bit?
         if is_bit(src):
             base, idx = parse_bit(src)

{pyshdl-0.1.3 → pyshdl-0.1.5}/uv.lock

@@ -1,8 +1,8 @@
 version = 1
-revision = 2
+revision = 3
 requires-python = ">=3.9"
 
 [[package]]
 name = "pyshdl"
-version = "0.1.2"
+version = "0.1.3"
 source = { editable = "." }