PyNerva 0.0.7__tar.gz → 0.0.8__tar.gz

{pynerva-0.0.7 → pynerva-0.0.8}/PKG-INFO

@@ -1,6 +1,6 @@
 Metadata-Version: 2.4
 Name: PyNerva
-Version: 0.0.7
+Version: 0.0.8
 Summary: Framework for exploring advanced program synthesis and transformation techniques
 Project-URL: Homepage, https://github.com/kriskwiatkowski/NervaPy.git
 Author-email: Kris Kwiatkowski <kris@amongbytes.com>

{pynerva-0.0.7 → pynerva-0.0.8}/nervapy/arm/__init__.py

@@ -93,7 +93,7 @@ from nervapy.arm.generic import (ADC, ADCCC, ADCCS, ADCEQ, ADCGE, ADCGT, ADCHI,
                                  TSTCS, TSTEQ, TSTGE, TSTGT, TSTHI, TSTHS,
                                  TSTLE, TSTLO, TSTLS, TSTLT, TSTMI, TSTNE,
                                  TSTPL, TSTVC, TSTVS, TT, TTA, TTAT, TTT,
-                                 UMAAL, UMAALGE, UMLAL, UMULL, B)
+                                 UMAAL, UMAALGE, UMLAL, UMULL, UXTH, B)
 from nervapy.arm.literal_pool import LDR_LITERAL, LDRL
 from nervapy.arm.microarchitecture import Microarchitecture
 from nervapy.arm.pseudo import (ALIGN, ASSUME, IMPORT, INIT, LABEL, LOAD,

{pynerva-0.0.7 → pynerva-0.0.8}/nervapy/arm/generic.py

@@ -9509,6 +9509,47 @@ class BitFieldInstruction(Instruction):
     def get_output_registers_list(self):
         return self.operands[0].get_registers_list()
 
+
+class UnsignedExtendHalfwordInstruction(Instruction):
+    """UXTH - zero-extend the low halfword of a register."""
+
+    def __init__(self, destination, source, origin=None):
+        from nervapy.arm.function import active_function
+        from nervapy.arm.isa import Extension
+
+        if not (
+            destination.is_general_purpose_register()
+            and source.is_general_purpose_register()
+        ):
+            raise ValueError(
+                "UXTH destination and source operands must be general-purpose registers"
+            )
+        if active_function and Extension.V6 not in active_function.target.extensions:
+            raise ValueError("UXTH is not supported on the current target")
+        super(UnsignedExtendHalfwordInstruction, self).__init__(
+            "UXTH", [destination, source], origin=origin
+        )
+
+    def get_input_registers_list(self):
+        return self.operands[1].get_registers_list()
+
+    def get_output_registers_list(self):
+        return self.operands[0].get_registers_list()
+
+
+def UXTH(destination, source):
+    """UXTH - zero-extend bits 0-15 of *source* into *destination*."""
+    origin = (
+        inspect.stack() if nervapy.arm.function.active_function.collect_origin else None
+    )
+    instruction = UnsignedExtendHalfwordInstruction(
+        Operand(destination), Operand(source), origin=origin
+    )
+    if nervapy.stream.active_stream is not None:
+        nervapy.stream.active_stream.add_instruction(instruction)
+    return instruction
+
+
 def BFI(destination, source, lsb, width):
     """BFI - Bit Field Insert  (Thumb-2 / ARMv7-M, ARMv8-M.main).
 

{pynerva-0.0.7 → pynerva-0.0.8}/pyproject.toml

@@ -1,6 +1,6 @@
 [project]
 name = "PyNerva"
-version = "0.0.7"
+version = "0.0.8"
 description = "Framework for exploring advanced program synthesis and transformation techniques"
 authors = [{ name = "Kris Kwiatkowski", email = "kris@amongbytes.com" }]
 keywords = [

pynerva-0.0.8/tests/arm/test_uxth.py

@@ -0,0 +1,43 @@
+import unittest
+
+from nervapy import *
+from nervapy.arm import *
+from nervapy.arm.abi import arm_gnueabihf
+from nervapy.arm.microarchitecture import Microarchitecture
+
+
+class TestUXTH(unittest.TestCase):
+    def test_emits_zero_extend_halfword(self):
+        with Function(
+            "zero_extend_halfword",
+            (),
+            target=Microarchitecture.ARM11,
+            abi=arm_gnueabihf,
+            report_generation=False,
+        ) as function:
+            UXTH(r0, r1)
+            RETURN()
+
+        self.assertIn("UXTH r0, r1", function.assembly)
+
+    def test_requires_armv6(self):
+        with self.assertRaisesRegex(ValueError, "not supported"):
+            with Function(
+                "unsupported_uxth",
+                (),
+                target=Microarchitecture.ARM9,
+                abi=arm_gnueabihf,
+                report_generation=False,
+            ):
+                UXTH(r0, r1)
+
+    def test_rejects_non_register_operands(self):
+        with self.assertRaisesRegex(ValueError, "general-purpose registers"):
+            with Function(
+                "invalid_uxth",
+                (),
+                target=Microarchitecture.ARM11,
+                abi=arm_gnueabihf,
+                report_generation=False,
+            ):
+                UXTH(r0, 1)