PyNerva 0.0.6__tar.gz → 0.0.8__tar.gz

{pynerva-0.0.6 → pynerva-0.0.8}/.gitea/workflows/test.yml

@@ -27,7 +27,7 @@ jobs:
       fail-fast: false
       matrix:
         os: [ ubuntu-latest-small ]
-        python-version: [ "3.8", "3.9", "3.10", "3.11", "3.12" ]
+        python-version: [ "3.10", "3.11", "3.12", "3.13", "3.14" ]
         exclude:
           # Exclude some combinations to reduce CI load if needed
           - os: windows-latest

{pynerva-0.0.6 → pynerva-0.0.8}/.github/workflows/test.yml

@@ -27,7 +27,7 @@ jobs:
       fail-fast: false
       matrix:
         os: [ubuntu-latest]
-        python-version: ['3.8', '3.9', '3.10', '3.11', '3.12']
+        python-version: ['3.10', '3.11', '3.12', '3.13', '3.14']
         exclude:
           # Exclude some combinations to reduce CI load if needed
           - os: windows-latest
@@ -162,4 +162,4 @@ jobs:
             except Exception as e:
                 print(f'✗ {module}: {e}')
                 sys.exit(1)
-        "
+        "

{pynerva-0.0.6 → pynerva-0.0.8}/PKG-INFO

@@ -1,6 +1,6 @@
 Metadata-Version: 2.4
 Name: PyNerva
-Version: 0.0.6
+Version: 0.0.8
 Summary: Framework for exploring advanced program synthesis and transformation techniques
 Project-URL: Homepage, https://github.com/kriskwiatkowski/NervaPy.git
 Author-email: Kris Kwiatkowski <kris@amongbytes.com>
@@ -27,9 +27,9 @@ Classifier: Topic :: Software Development :: Assemblers
 Classifier: Topic :: Software Development :: Code Generators
 Classifier: Topic :: Software Development :: Compilers
 Classifier: Topic :: Software Development :: Libraries
-Requires-Python: >=3.8
+Requires-Python: >=3.10
 Requires-Dist: click>=8.1.8
-Requires-Dist: requests>=2.32.4
+Requires-Dist: requests>=2.34.2
 Description-Content-Type: text/x-rst
 
 .. image:: https://github.com/kriskwiatkowski/NervaPy/blob/master/logo/nervapy.png

{pynerva-0.0.6 → pynerva-0.0.8}/examples/arm_rust_integration.py

@@ -7,39 +7,20 @@ Rust Integration Example
 Demonstrates how to generate ARM assembly kernels for use in Rust projects,
 targeting Cortex-M33 (ARMv8-M.main).
 
-Two integration methods are shown:
-
-  Option A - Separate .s file compiled via build.rs:
-
-      // build.rs
-      fn main() {
-          cc::Build::new()
-              .file("src/kernels.s")
-              .compile("kernels");
-      }
-
-      // Cargo.toml
-      [build-dependencies]
-      cc = "1"
-
-      // lib.rs
-      unsafe extern "C" {
-          fn copy_words(src: *const u32, dst: *mut u32, n: usize);
-          fn accumulate(data: *const u32, n: usize) -> u32;
-      }
-
-  Option B - Embedded directly in a .rs file (no build.rs needed):
-
-      // kernels.rs  (generated by this script)
-      use core::arch::global_asm;
-      core::arch::global_asm!(r#" ... "#);
-
-      // lib.rs
-      mod kernels;
-      unsafe extern "C" {
-          fn copy_words(src: *const u32, dst: *mut u32, n: usize);
-          fn accumulate(data: *const u32, n: usize) -> u32;
-      }
+The method is embedded directly in a .rs file with typed externs (no build.rs needed):
+
+       // kernels.rs  (generated by this script)
+       core::arch::global_asm!(r#" ... "#);
+       unsafe extern "C" {
+           pub fn copy_words(src: *const u32, dst: *mut u32, n: usize);
+       }
+       core::arch::global_asm!(r#" ... "#);
+       unsafe extern "C" {
+           pub fn accumulate(data: *const u32, n: usize) -> u32;
+       }
+
+       // lib.rs
+       mod kernels;
 """
 
 import os
@@ -51,7 +32,6 @@ from nervapy.arm.microarchitecture import Microarchitecture
 
 TARGET = Microarchitecture.CortexM33
 
-
 def generate_copy_words():
     """Copy n words from src to dst - equivalent to memcpy for aligned u32 arrays."""
     src_arg = Argument(ptr(const_uint32_t))
@@ -103,22 +83,12 @@ def generate_accumulate():
 
     return f
 
-
-def write_s_file(functions, path):
-    """Write all functions to a single .s file (Option A)."""
-    with open(path, "w") as fp:
-        for f in functions:
-            fp.write(f.assembly)
-    print("Wrote: {}".format(path))
-
-
 def write_global_asm_file(functions, path):
-    """Write all functions as a Rust global_asm!() file (Option B)."""
+    """Write all functions as a Rust file with global_asm!() and typed externs (Option B)."""
     with open(path, "w") as fp:
         fp.write("// Auto-generated by NervaPy - do not edit manually.\n")
-        fp.write("use core::arch::global_asm;\n\n")
         for f in functions:
-            fp.write(f.global_asm)
+            fp.write(f.rust_module)
             fp.write("\n")
     print("Wrote: {}".format(path))
 
@@ -128,20 +98,4 @@ if __name__ == "__main__":
     accum_fn = generate_accumulate()
     functions = [copy_fn, accum_fn]
 
-    out_dir = os.path.join(os.path.dirname(__file__), "rust_output")
-    os.makedirs(out_dir, exist_ok=True)
-
-    # Option A: separate .s file
-    write_s_file(functions, os.path.join(out_dir, "kernels.s"))
-
-    # Option B: global_asm!() Rust file
-    write_global_asm_file(functions, os.path.join(out_dir, "kernels.rs"))
-
-    print()
-    print("--- kernels.s (Option A) ---")
-    for f in functions:
-        print(f.assembly)
-
-    print("--- kernels.rs (Option B) ---")
-    for f in functions:
-        print(f.global_asm)
+    write_global_asm_file(functions, os.path.join(os.path.dirname(__file__), "kernels.rs"))

pynerva-0.0.8/examples/kernels.rs

@@ -0,0 +1,51 @@
+// Auto-generated by NervaPy - do not edit manually.
+core::arch::global_asm!(r#"
+	.syntax unified
+	.arch armv8-m.main
+
+	.text
+
+.global copy_words
+.type copy_words, %function
+copy_words:
+Lcopy_words.ENTRY:
+Lcopy_words.loop_begin:
+	LDR r12, [r0], #4
+	STR r12, [r1], #4
+	SUBS r2, r2, #1
+	BNE Lcopy_words.loop_begin
+Lcopy_words.loop_end:
+	BX lr
+
+"#);
+
+unsafe extern "C" {
+    pub fn copy_words(src: *const u32, dst: *mut u32, n: usize);
+}
+
+core::arch::global_asm!(r#"
+	.syntax unified
+	.arch armv8-m.main
+
+	.text
+
+.global accumulate
+.type accumulate, %function
+accumulate:
+Laccumulate.ENTRY:
+	MOV r12, #0
+Laccumulate.loop_begin:
+	LDR r3, [r0], #4
+	ADD r12, r12, r3
+	SUBS r1, r1, #1
+	BNE Laccumulate.loop_begin
+Laccumulate.loop_end:
+	MOV r0, r12
+	BX lr
+
+"#);
+
+unsafe extern "C" {
+    pub fn accumulate(data: *const u32, n: usize) -> u32;
+}
+

{pynerva-0.0.6 → pynerva-0.0.8}/nervapy/arm/__init__.py

@@ -93,7 +93,7 @@ from nervapy.arm.generic import (ADC, ADCCC, ADCCS, ADCEQ, ADCGE, ADCGT, ADCHI,
                                  TSTCS, TSTEQ, TSTGE, TSTGT, TSTHI, TSTHS,
                                  TSTLE, TSTLO, TSTLS, TSTLT, TSTMI, TSTNE,
                                  TSTPL, TSTVC, TSTVS, TT, TTA, TTAT, TTT,
-                                 UMAAL, UMAALGE, UMLAL, UMULL, B)
+                                 UMAAL, UMAALGE, UMLAL, UMULL, UXTH, B)
 from nervapy.arm.literal_pool import LDR_LITERAL, LDRL
 from nervapy.arm.microarchitecture import Microarchitecture
 from nervapy.arm.pseudo import (ALIGN, ASSUME, IMPORT, INIT, LABEL, LOAD,

{pynerva-0.0.6 → pynerva-0.0.8}/nervapy/arm/function.py

@@ -338,7 +338,67 @@ class Function(object):
             unsafe extern "C" { fn my_func(a: u32) -> u32; }
         """
         gas = self._generate_gas_assembly()
-        return 'core::arch::global_asm!(r#"\n{asm}"#);\n'.format(asm=gas)
+        return 'core::arch::global_asm!(r#"\n{asm}"#);\n'.format(
+            asm=self._escape_rust_asm_template(gas)
+        )
+
+    @staticmethod
+    def _escape_rust_asm_template(asm):
+        return asm.replace("{", "{{").replace("}", "}}")
+
+    def _rust_ffi_type(self, c_type):
+        if c_type.is_pointer:
+            pointee = c_type.base
+            if pointee is None:
+                pointee_type = "core::ffi::c_void"
+                is_const_pointee = c_type.is_const
+            else:
+                pointee_type = self._rust_ffi_type(pointee)
+                is_const_pointee = pointee.is_const
+            return "{0} {1}".format(
+                "*const" if is_const_pointee else "*mut", pointee_type
+            )
+
+        if c_type.is_size_integer:
+            return "usize" if c_type.is_unsigned_integer else "isize"
+        if c_type.is_pointer_integer:
+            return "usize" if c_type.is_unsigned_integer else "isize"
+        if c_type.is_bool:
+            return "bool"
+        if c_type.is_char:
+            return "core::ffi::c_char"
+        if c_type.is_wchar:
+            wchar_size = c_type.get_size(self.abi)
+            return {2: "u16", 4: "u32"}[wchar_size]
+        if c_type.is_floating_point:
+            return {2: "u16", 4: "f32", 8: "f64"}[c_type.get_size(self.abi)]
+        if c_type.is_signed_integer:
+            return {1: "i8", 2: "i16", 4: "i32", 8: "i64"}[c_type.get_size(self.abi)]
+        if c_type.is_unsigned_integer:
+            return {1: "u8", 2: "u16", 4: "u32", 8: "u64"}[c_type.get_size(self.abi)]
+
+        raise ValueError("Unsupported Rust FFI type for {0}".format(c_type))
+
+    @property
+    def rust_extern_declaration(self):
+        args = ", ".join(
+            "{0}: {1}".format(argument.name, self._rust_ffi_type(argument.c_type))
+            for argument in self.arguments
+        )
+        signature = "pub fn {0}({1})".format(self.name, args)
+        if self.return_type is not None:
+            signature += " -> {0}".format(self._rust_ffi_type(self.return_type))
+        return signature + ";"
+
+    @property
+    def rust_extern(self):
+        return "unsafe extern \"C\" {{\n    {0}\n}}\n".format(
+            self.rust_extern_declaration
+        )
+
+    @property
+    def rust_module(self):
+        return self.global_asm + "\n" + self.rust_extern
 
     def _generate_gas_assembly(self):
         """Generate assembly code in GNU Assembler (GAS) format."""

{pynerva-0.0.6 → pynerva-0.0.8}/nervapy/arm/generic.py

@@ -9509,6 +9509,47 @@ class BitFieldInstruction(Instruction):
     def get_output_registers_list(self):
         return self.operands[0].get_registers_list()
 
+
+class UnsignedExtendHalfwordInstruction(Instruction):
+    """UXTH - zero-extend the low halfword of a register."""
+
+    def __init__(self, destination, source, origin=None):
+        from nervapy.arm.function import active_function
+        from nervapy.arm.isa import Extension
+
+        if not (
+            destination.is_general_purpose_register()
+            and source.is_general_purpose_register()
+        ):
+            raise ValueError(
+                "UXTH destination and source operands must be general-purpose registers"
+            )
+        if active_function and Extension.V6 not in active_function.target.extensions:
+            raise ValueError("UXTH is not supported on the current target")
+        super(UnsignedExtendHalfwordInstruction, self).__init__(
+            "UXTH", [destination, source], origin=origin
+        )
+
+    def get_input_registers_list(self):
+        return self.operands[1].get_registers_list()
+
+    def get_output_registers_list(self):
+        return self.operands[0].get_registers_list()
+
+
+def UXTH(destination, source):
+    """UXTH - zero-extend bits 0-15 of *source* into *destination*."""
+    origin = (
+        inspect.stack() if nervapy.arm.function.active_function.collect_origin else None
+    )
+    instruction = UnsignedExtendHalfwordInstruction(
+        Operand(destination), Operand(source), origin=origin
+    )
+    if nervapy.stream.active_stream is not None:
+        nervapy.stream.active_stream.add_instruction(instruction)
+    return instruction
+
+
 def BFI(destination, source, lsb, width):
     """BFI - Bit Field Insert  (Thumb-2 / ARMv7-M, ARMv8-M.main).
 

{pynerva-0.0.6 → pynerva-0.0.8}/pyproject.toml

@@ -1,6 +1,6 @@
 [project]
 name = "PyNerva"
-version = "0.0.6"
+version = "0.0.8"
 description = "Framework for exploring advanced program synthesis and transformation techniques"
 authors = [{ name = "Kris Kwiatkowski", email = "kris@amongbytes.com" }]
 keywords = [
@@ -15,7 +15,7 @@ keywords = [
     "code transformation",
 ]
 readme = "README.rst"
-requires-python = ">=3.8"
+requires-python = ">=3.10"
 classifiers = [
     "Development Status :: 3 - Alpha",
     "Intended Audience :: Developers",
@@ -39,7 +39,7 @@ classifiers = [
     "Topic :: Software Development :: Compilers",
     "Topic :: Software Development :: Libraries",
 ]
-dependencies = ["click>=8.1.8", "requests>=2.32.4"]
+dependencies = ["click>=8.1.8", "requests>=2.34.2"]
 
 [project.urls]
 Homepage = "https://github.com/kriskwiatkowski/NervaPy.git"

{pynerva-0.0.6 → pynerva-0.0.8}/tests/arm/test_armv8m.py

@@ -446,6 +446,25 @@ class TestRustOutput(unittest.TestCase):
             RETURN()
         return f
 
+    def _make_accumulate(self, target):
+        data_arg = Argument(ptr(const_uint32_t))
+        n_arg = Argument(size_t)
+        with Function('accumulate', (data_arg, n_arg), uint32_t,
+                      target=target, abi=arm_gnueabihf,
+                      report_generation=False) as f:
+            (data, n) = LOAD.ARGUMENTS()
+            acc = GeneralPurposeRegister()
+            MOV(acc, 0)
+            with Loop() as loop:
+                word = GeneralPurposeRegister()
+                LDR(word, [data], 4)
+                ADD(acc, acc, word)
+                SUBS(n, n, 1)
+                BNE(loop.begin)
+            MOV(r0, acc)
+            RETURN()
+        return f
+
     def test_global_asm_macro_wrapping(self):
         """global_asm property wraps GAS output in core::arch::global_asm!(r#"..."#)."""
         f = self._make_copy_words(Microarchitecture.CortexM33)
@@ -456,12 +475,49 @@ class TestRustOutput(unittest.TestCase):
         self.assertIn('copy_words:', out)
         self.assertIn('.arch armv8-m.main', out)
 
-    def test_global_asm_matches_gas_assembly(self):
-        """global_asm content is identical to function.assembly."""
+    def test_global_asm_matches_escaped_gas_assembly(self):
+        """global_asm content is Rust-escaped GAS assembly."""
         f = self._make_copy_words(Microarchitecture.CortexM33)
         gas = f.assembly
         global_asm = f.global_asm
-        self.assertIn(gas, global_asm)
+        self.assertIn(gas.replace('{', '{{').replace('}', '}}'), global_asm)
+
+    def test_global_asm_escapes_register_lists(self):
+        """global_asm escapes braces so register lists are valid Rust asm templates."""
+        from nervapy.arm.registers import lr, r4, r5
+        with Function('push_pop', (), None,
+                      target=Microarchitecture.CortexM33, abi=arm_gnueabihf,
+                      report_generation=False) as f:
+            PUSH((r4, r5))
+            POP((r4, r5))
+            BX(lr)
+
+        out = f.global_asm
+        self.assertIn('{{r4, r5}}', out)
+
+    def test_rust_extern_declaration_for_arguments(self):
+        """rust_extern_declaration maps pointer and size arguments to Rust FFI types."""
+        f = self._make_copy_words(Microarchitecture.CortexM33)
+        self.assertEqual(
+            f.rust_extern_declaration,
+            'pub fn copy_words(src: *const u32, dst: *mut u32, len: usize);'
+        )
+
+    def test_rust_extern_declaration_for_return_value(self):
+        """rust_extern_declaration includes the Rust return type."""
+        f = self._make_accumulate(Microarchitecture.CortexM33)
+        self.assertEqual(
+            f.rust_extern_declaration,
+            'pub fn accumulate(data: *const u32, n: usize) -> u32;'
+        )
+
+    def test_rust_module_combines_asm_and_extern(self):
+        """rust_module emits both the assembly body and the typed extern declaration."""
+        f = self._make_accumulate(Microarchitecture.CortexM33)
+        out = f.rust_module
+        self.assertIn('core::arch::global_asm!(r#"', out)
+        self.assertIn('unsafe extern "C" {', out)
+        self.assertIn('pub fn accumulate(data: *const u32, n: usize) -> u32;', out)
 
     def test_gas_output_usable_as_s_file(self):
         """GAS output has directives required for a Rust .s file."""

pynerva-0.0.8/tests/arm/test_uxth.py

@@ -0,0 +1,43 @@
+import unittest
+
+from nervapy import *
+from nervapy.arm import *
+from nervapy.arm.abi import arm_gnueabihf
+from nervapy.arm.microarchitecture import Microarchitecture
+
+
+class TestUXTH(unittest.TestCase):
+    def test_emits_zero_extend_halfword(self):
+        with Function(
+            "zero_extend_halfword",
+            (),
+            target=Microarchitecture.ARM11,
+            abi=arm_gnueabihf,
+            report_generation=False,
+        ) as function:
+            UXTH(r0, r1)
+            RETURN()
+
+        self.assertIn("UXTH r0, r1", function.assembly)
+
+    def test_requires_armv6(self):
+        with self.assertRaisesRegex(ValueError, "not supported"):
+            with Function(
+                "unsupported_uxth",
+                (),
+                target=Microarchitecture.ARM9,
+                abi=arm_gnueabihf,
+                report_generation=False,
+            ):
+                UXTH(r0, r1)
+
+    def test_rejects_non_register_operands(self):
+        with self.assertRaisesRegex(ValueError, "general-purpose registers"):
+            with Function(
+                "invalid_uxth",
+                (),
+                target=Microarchitecture.ARM11,
+                abi=arm_gnueabihf,
+                report_generation=False,
+            ):
+                UXTH(r0, 1)