@tscircuit/fake-snippets 0.0.203 → 0.0.205
This diff represents the content of publicly available package versions that have been released to one of the supported registries. The information contained in this diff is provided for informational purposes only and reflects changes between package versions as they appear in their respective public registries.
- package/dist/bundle.js +385 -39
- package/dist/index.js +277 -4
- package/package.json +1 -1
package/dist/index.js
CHANGED
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@@ -1623,8 +1623,17 @@ Added value prop support.`,
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content_text: `import { formatResistance, DEFAULT_RESISTANCE } from "./utils"
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import type { ComponentProps } from "./types"
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-
export const TestComponent = ({
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-
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export const TestComponent = ({
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name,
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value = DEFAULT_RESISTANCE,
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}: ComponentProps) => (
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<board width="10mm" height="10mm">
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<resistor
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footprint="0402"
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name={name}
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resistance={formatResistance(value)}
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/>
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</board>
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)`,
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created_at: (/* @__PURE__ */ new Date()).toISOString(),
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is_text: true
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@@ -1663,6 +1672,261 @@ import { TestComponent } from "@tsci/testuser.test2-package"
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created_at: (/* @__PURE__ */ new Date()).toISOString(),
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is_text: true
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});
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db.addPackageFile({
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package_release_id: test2PackageReleaseId4,
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file_path: "dist/index/circuit.json",
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content_text: JSON.stringify([
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{
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type: "source_project_metadata",
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source_project_metadata_id: "source_project_metadata_0",
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software_used_string: "@tscircuit/core@0.0.1065"
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},
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{
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type: "source_group",
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source_group_id: "source_group_0",
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is_subcircuit: true,
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was_automatically_named: true,
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subcircuit_id: "subcircuit_source_group_0"
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},
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{
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type: "source_port",
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source_port_id: "source_port_0",
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name: "pin1",
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pin_number: 1,
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port_hints: ["pin1", "anode", "pos", "left", "1"],
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source_component_id: "source_component_0",
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subcircuit_id: "subcircuit_source_group_0"
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},
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{
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type: "source_port",
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source_port_id: "source_port_1",
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name: "pin2",
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pin_number: 2,
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port_hints: ["pin2", "cathode", "neg", "right", "2"],
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source_component_id: "source_component_0",
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subcircuit_id: "subcircuit_source_group_0"
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},
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{
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type: "source_component",
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source_component_id: "source_component_0",
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ftype: "simple_resistor",
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name: "unnamed_resistor1",
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supplier_part_numbers: { jlcpcb: [] },
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resistance: 4e4,
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display_resistance: "40k\u03A9",
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are_pins_interchangeable: true,
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source_group_id: "source_group_0"
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},
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{
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type: "source_board",
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source_board_id: "source_board_0",
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source_group_id: "source_group_0"
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},
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{
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type: "source_pin_missing_trace_warning",
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source_pin_missing_trace_warning_id: "source_pin_missing_trace_warning_0",
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message: "Port pin1 on undefined is missing a trace",
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source_component_id: "source_component_0",
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source_port_id: "source_port_0",
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subcircuit_id: "subcircuit_source_group_0",
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warning_type: "source_pin_missing_trace_warning"
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},
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{
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type: "source_pin_missing_trace_warning",
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source_pin_missing_trace_warning_id: "source_pin_missing_trace_warning_1",
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message: "Port pin2 on undefined is missing a trace",
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source_component_id: "source_component_0",
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source_port_id: "source_port_1",
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subcircuit_id: "subcircuit_source_group_0",
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warning_type: "source_pin_missing_trace_warning"
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},
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{
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type: "schematic_component",
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schematic_component_id: "schematic_component_0",
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center: { x: 0, y: 0 },
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size: { width: 1.1, height: 0.388910699999999 },
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source_component_id: "source_component_0",
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is_box_with_pins: true,
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symbol_name: "boxresistor_right",
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symbol_display_value: "40k\u03A9",
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schematic_group_id: "schematic_group_0"
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},
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{
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type: "schematic_group",
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schematic_group_id: "schematic_group_0",
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is_subcircuit: true,
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subcircuit_id: "subcircuit_source_group_0",
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name: "unnamed_board1",
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center: { x: 0, y: 0 },
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width: 0,
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height: 0,
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schematic_component_ids: [],
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source_group_id: "source_group_0"
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},
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{
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type: "schematic_port",
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schematic_port_id: "schematic_port_0",
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schematic_component_id: "schematic_component_0",
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center: { x: -0.55, y: 0 },
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source_port_id: "source_port_0",
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facing_direction: "left",
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distance_from_component_edge: 0.4,
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pin_number: 1,
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display_pin_label: "anode",
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is_connected: false
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},
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{
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type: "schematic_port",
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schematic_port_id: "schematic_port_1",
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schematic_component_id: "schematic_component_0",
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center: { x: 0.55, y: 0 },
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source_port_id: "source_port_1",
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facing_direction: "right",
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distance_from_component_edge: 0.4,
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pin_number: 2,
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display_pin_label: "cathode",
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is_connected: false
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},
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{
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type: "pcb_component",
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pcb_component_id: "pcb_component_0",
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center: { x: 0, y: 0 },
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width: 1.56,
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height: 0.64,
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layer: "top",
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rotation: 0,
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source_component_id: "source_component_0",
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subcircuit_id: "subcircuit_source_group_0",
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do_not_place: false,
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obstructs_within_bounds: true
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},
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{
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type: "pcb_board",
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pcb_board_id: "pcb_board_0",
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source_board_id: "source_board_0",
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center: { x: 0, y: 0 },
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thickness: 1.4,
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num_layers: 2,
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width: 10,
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height: 10,
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material: "fr4"
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},
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{
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type: "pcb_smtpad",
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pcb_smtpad_id: "pcb_smtpad_0",
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pcb_component_id: "pcb_component_0",
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pcb_port_id: "pcb_port_0",
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layer: "top",
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shape: "rect",
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width: 0.54,
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height: 0.64,
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port_hints: ["1", "left"],
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is_covered_with_solder_mask: false,
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x: -0.51,
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y: 0,
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subcircuit_id: "subcircuit_source_group_0"
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},
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{
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type: "pcb_solder_paste",
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pcb_solder_paste_id: "pcb_solder_paste_0",
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layer: "top",
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shape: "rect",
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width: 0.378,
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height: 0.44799999999999995,
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x: -0.51,
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y: 0,
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pcb_component_id: "pcb_component_0",
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pcb_smtpad_id: "pcb_smtpad_0",
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subcircuit_id: "subcircuit_source_group_0"
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},
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{
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type: "pcb_smtpad",
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pcb_smtpad_id: "pcb_smtpad_1",
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pcb_component_id: "pcb_component_0",
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pcb_port_id: "pcb_port_1",
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layer: "top",
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shape: "rect",
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width: 0.54,
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height: 0.64,
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port_hints: ["2", "right"],
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is_covered_with_solder_mask: false,
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x: 0.51,
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y: 0,
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subcircuit_id: "subcircuit_source_group_0"
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},
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{
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type: "pcb_solder_paste",
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pcb_solder_paste_id: "pcb_solder_paste_1",
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layer: "top",
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shape: "rect",
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width: 0.378,
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height: 0.44799999999999995,
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x: 0.51,
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y: 0,
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pcb_component_id: "pcb_component_0",
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pcb_smtpad_id: "pcb_smtpad_1",
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subcircuit_id: "subcircuit_source_group_0"
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},
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{
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type: "pcb_silkscreen_path",
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pcb_silkscreen_path_id: "pcb_silkscreen_path_0",
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pcb_component_id: "pcb_component_0",
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layer: "top",
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route: [
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{ x: 0.51, y: 0.72 },
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{ x: -0.98, y: 0.72 },
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{ x: -0.98, y: -0.72 },
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{ x: 0.51, y: -0.72 }
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],
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stroke_width: 0.1,
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subcircuit_id: "subcircuit_source_group_0"
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},
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{
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type: "pcb_silkscreen_text",
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pcb_silkscreen_text_id: "pcb_silkscreen_text_0",
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anchor_alignment: "center",
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anchor_position: { x: 0, y: 1.22 },
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font: "tscircuit2024",
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font_size: 0.4,
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layer: "top",
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text: "Resistor",
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ccw_rotation: 0,
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pcb_component_id: "pcb_component_0",
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subcircuit_id: "subcircuit_source_group_0"
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},
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{
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type: "pcb_port",
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pcb_port_id: "pcb_port_0",
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pcb_component_id: "pcb_component_0",
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layers: ["top"],
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subcircuit_id: "subcircuit_source_group_0",
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x: -0.51,
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y: 0,
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source_port_id: "source_port_0"
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},
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{
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type: "pcb_port",
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pcb_port_id: "pcb_port_1",
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pcb_component_id: "pcb_component_0",
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layers: ["top"],
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subcircuit_id: "subcircuit_source_group_0",
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x: 0.51,
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y: 0,
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source_port_id: "source_port_1"
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},
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{
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type: "cad_component",
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cad_component_id: "cad_component_0",
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position: { x: 0, y: 0, z: 0.7 },
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rotation: { x: 0, y: 0, z: 0 },
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pcb_component_id: "pcb_component_0",
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source_component_id: "source_component_0",
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1924
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+
footprinter_string: "0402"
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1925
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+
}
|
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1926
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+
]),
|
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1927
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+
created_at: (/* @__PURE__ */ new Date()).toISOString(),
|
|
1928
|
+
is_text: true
|
|
1929
|
+
});
|
|
1666
1930
|
db.addPackageFile({
|
|
1667
1931
|
package_release_id: test2PackageReleaseIdPr1,
|
|
1668
1932
|
file_path: "index.tsx",
|
|
@@ -1708,8 +1972,17 @@ export const DEFAULT_RESISTANCE = 50`,
|
|
|
1708
1972
|
content_text: `import { formatResistance, DEFAULT_RESISTANCE } from "./utils"
|
|
1709
1973
|
import type { ComponentProps } from "./types"
|
|
1710
1974
|
|
|
1711
|
-
export const TestComponent = ({
|
|
1712
|
-
|
|
1975
|
+
export const TestComponent = ({
|
|
1976
|
+
name,
|
|
1977
|
+
value = DEFAULT_RESISTANCE,
|
|
1978
|
+
}: ComponentProps) => (
|
|
1979
|
+
<board width="10mm" height="10mm">
|
|
1980
|
+
<resistor
|
|
1981
|
+
footprint="0402"
|
|
1982
|
+
name={name}
|
|
1983
|
+
resistance={formatResistance(value)}
|
|
1984
|
+
/>
|
|
1985
|
+
</board>
|
|
1713
1986
|
)`,
|
|
1714
1987
|
created_at: (/* @__PURE__ */ new Date()).toISOString(),
|
|
1715
1988
|
is_text: true
|