@simten/ui 0.1.1

package/dist/editor/types/circuit.d.ts

@@ -0,0 +1,207 @@
+/**
+ * Intermediate Representation (IR) v0.1 - TypeScript Type Definitions
+ *
+ * This is the formal IR specification in TypeScript.
+ * See /docs/circuit-spec.md for detailed documentation.
+ */
+export interface BitType {
+    kind: 'bit';
+}
+export interface BusType {
+    kind: 'bus';
+    width: number;
+}
+export type PortType = BitType | BusType;
+export interface PortDescriptor {
+    name: string;
+    portType: PortType;
+    description?: string;
+    /** Default value for unconnected inputs. If specified, port is optional. */
+    defaultValue?: BitValue | BusValue;
+    widthParam?: string;
+    widthMultiplier?: number;
+}
+export type BitValue = boolean;
+export type BusValue = number;
+export interface PortInstance {
+    id: string;
+    name: string;
+    portType: PortType;
+    value?: BitValue | BusValue;
+}
+export interface ClockDescriptor {
+    name: string;
+    description?: string;
+}
+export interface ClockState {
+    value: boolean;
+    edge: 'rising' | 'falling' | 'none';
+}
+export interface ClockInstance {
+    id: string;
+    name: string;
+    state?: ClockState;
+}
+export interface MemoryType {
+    kind: 'memory';
+    addressWidth: number;
+    dataWidth: number;
+}
+export type StateType = BitType | BusType | MemoryType;
+export interface MemoryValue {
+    data: Map<number, number>;
+    addressWidth: number;
+    dataWidth: number;
+}
+export type StateValue = BitValue | BusValue | MemoryValue | string;
+export interface StateBlock {
+    id: string;
+    name: string;
+    stateType: StateType;
+    initialValue: StateValue;
+    currentValue?: StateValue;
+    clockRef?: string;
+    edge?: 'rising' | 'falling';
+}
+export interface PortPath {
+    nodeId: string;
+    portName: string;
+}
+export interface Connection {
+    id: string;
+    source: PortPath;
+    target: PortPath;
+    portType: PortType;
+}
+export type ArgumentValue = number | string | boolean | number[] | Record<number, number>;
+export interface Node {
+    id: string;
+    label?: string;
+    componentRef: string;
+    arguments: Record<string, ArgumentValue>;
+    inputs: PortInstance[];
+    outputs: PortInstance[];
+    clocks: ClockInstance[];
+}
+export interface PrimitiveImpl {
+    kind: 'primitive';
+}
+export interface CompositeImpl {
+    kind: 'composite';
+}
+export interface IntrinsicImpl {
+    kind: 'intrinsic';
+    intrinsicType: string;
+}
+export type Implementation = PrimitiveImpl | CompositeImpl | IntrinsicImpl;
+export type ParameterType = 'int' | 'string' | 'bool';
+export interface Parameter {
+    name: string;
+    paramType: ParameterType;
+    defaultValue?: number | string | boolean;
+    options?: (number | string | boolean)[];
+}
+export interface TestCase {
+    name: string;
+    inputs: Record<string, BitValue | BusValue>;
+    expectedOutputs: Record<string, BitValue | BusValue>;
+}
+/**
+ * Component Kind - determines evaluation order and cycle detection
+ *
+ * - combinational: Pure logic, no state, must be acyclic
+ * - sequential: Has state (registers, RAM), updates on clock edges
+ * - sink: Consumes signals but outputs don't feed back (Screen, audio, UART)
+ */
+export type ComponentKind = 'combinational' | 'sequential' | 'sink';
+export interface CircuitMetadata {
+    source?: {
+        filename?: string;
+        lineNumber?: number;
+    };
+    description?: string;
+    author?: string;
+    version?: string;
+    testCases?: TestCase[];
+    tags?: string[];
+    /** Timing classification: combinational, sequential, or sink. */
+    timing?: ComponentKind;
+    /**
+     * For sequential components: how outputs are computed
+     * - 'state-only': Outputs come purely from state (DFlipFlop, Register)
+     * - 'state+inputs': Outputs depend on state AND combinational inputs (RAM/ROM - address-based read)
+     * - 'input-dependent': Outputs depend only on current inputs (pure combinational)
+     *
+     * Used for topological sorting. Evaluation order:
+     * 1. state-only nodes (registers output .q)
+     * 2. combinational logic (address calc, muxes, ALU)
+     * 3. state+inputs nodes (RAM/ROM read using computed address)
+     * 4. sinks
+     */
+    outputDependency?: 'state-only' | 'state+inputs' | 'input-dependent';
+}
+export interface Circuit {
+    /** Schema version for the Circuit IR. */
+    version: 1;
+    name: string;
+    inputs: PortDescriptor[];
+    outputs: PortDescriptor[];
+    clocks: ClockDescriptor[];
+    state: StateBlock[];
+    nodes: Node[];
+    connections: Connection[];
+    implementation: Implementation;
+    metadata?: CircuitMetadata;
+}
+export interface CircuitFile {
+    version: string;
+    circuit: Circuit;
+}
+export type ValidationErrorType = 'type_mismatch' | 'multiple_drivers' | 'combinational_loop' | 'undefined_component' | 'undefined_port' | 'invalid_clock_ref' | 'parameter_mismatch' | 'missing_required_connection';
+export interface ValidationError {
+    type: ValidationErrorType;
+    location: {
+        circuitId: string;
+        nodeId?: string;
+        connectionId?: string;
+        portPath?: PortPath;
+    };
+    message: string;
+    suggestions?: string[];
+}
+export interface SimulationState {
+    portValues: Map<string, BitValue | BusValue>;
+    stateValues: Map<string, StateValue>;
+    clockStates: Map<string, ClockState>;
+    cycle: number;
+    evaluationOrder: string[];
+}
+/**
+ * Create a port path from components
+ */
+export declare function createPortPath(nodeId: string, portName: string): PortPath;
+/**
+ * Create a port path key for Map lookups
+ */
+export declare function portPathKey(path: PortPath): string;
+/**
+ * Check if two port types are compatible
+ */
+export declare function isPortTypeCompatible(a: PortType, b: PortType): boolean;
+/**
+ * Get default value for a port type
+ */
+export declare function getDefaultValue(portType: PortType): BitValue | BusValue;
+/**
+ * Create a bit type
+ */
+export declare function bitType(): BitType;
+/**
+ * Create a bus type
+ */
+export declare function busType(width: number): BusType;
+/**
+ * Create a memory type
+ */
+export declare function memoryType(addressWidth: number, dataWidth: number): MemoryType;
+//# sourceMappingURL=circuit.d.ts.map

package/dist/editor/types/circuit.d.ts.map

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package/dist/editor/types/circuit.js

@@ -0,0 +1,62 @@
+/**
+ * Intermediate Representation (IR) v0.1 - TypeScript Type Definitions
+ *
+ * This is the formal IR specification in TypeScript.
+ * See /docs/circuit-spec.md for detailed documentation.
+ */
+// ============================================================================
+// Helper Functions
+// ============================================================================
+/**
+ * Create a port path from components
+ */
+export function createPortPath(nodeId, portName) {
+    return { nodeId, portName };
+}
+/**
+ * Create a port path key for Map lookups
+ */
+export function portPathKey(path) {
+    return path.nodeId === '' ? `circuit.${path.portName}` : `${path.nodeId}.${path.portName}`;
+}
+/**
+ * Check if two port types are compatible
+ */
+export function isPortTypeCompatible(a, b) {
+    if (a.kind !== b.kind)
+        return false;
+    if (a.kind === 'bus' && b.kind === 'bus') {
+        return a.width === b.width;
+    }
+    return true;
+}
+/**
+ * Get default value for a port type
+ */
+export function getDefaultValue(portType) {
+    if (portType.kind === 'bit') {
+        return false;
+    }
+    else {
+        return 0;
+    }
+}
+/**
+ * Create a bit type
+ */
+export function bitType() {
+    return { kind: 'bit' };
+}
+/**
+ * Create a bus type
+ */
+export function busType(width) {
+    return { kind: 'bus', width };
+}
+/**
+ * Create a memory type
+ */
+export function memoryType(addressWidth, dataWidth) {
+    return { kind: 'memory', addressWidth, dataWidth };
+}
+//# sourceMappingURL=circuit.js.map

package/dist/editor/types/circuit.js.map

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package/dist/editor/types/index.d.ts

@@ -0,0 +1,12 @@
+/**
+ * Type Exports
+ *
+ * Central export point for all type definitions.
+ */
+export type { BitType, BusType, PortType, PortDescriptor, BitValue, BusValue, ClockDescriptor, ClockState, ClockInstance, StateBlock, StateValue, PortPath, Node, Parameter, Implementation, CircuitMetadata, Circuit, ValidationError, } from './circuit';
+export { createPortPath, portPathKey, isPortTypeCompatible, getDefaultValue, bitType, busType, memoryType, } from './circuit';
+export * from './ui-model';
+export * from './visual';
+export * from './ui';
+export * from './testing';
+//# sourceMappingURL=index.d.ts.map

package/dist/editor/types/index.d.ts.map

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package/dist/editor/types/index.js

@@ -0,0 +1,11 @@
+/**
+ * Type Exports
+ *
+ * Central export point for all type definitions.
+ */
+export { createPortPath, portPathKey, isPortTypeCompatible, getDefaultValue, bitType, busType, memoryType, } from './circuit';
+export * from './ui-model';
+export * from './visual';
+export * from './ui';
+export * from './testing';
+//# sourceMappingURL=index.js.map

package/dist/editor/types/index.js.map

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package/dist/editor/types/testbench.d.ts

@@ -0,0 +1,150 @@
+/**
+ * Testbench Intermediate Representation (IR)
+ *
+ * This is the compiled, executable representation of testbenches.
+ * The testbench IR is generated from testbench AST by the testbench compiler.
+ *
+ * Design:
+ * - Bit-level stimulus core (cycle-by-cycle value assignments)
+ * - VCD waveform capture configuration
+ * - Future-proof for multi-clock and assertions
+ */
+import { BitValue, BusValue, Circuit } from './circuit';
+/**
+ * Compiled testbench ready for execution
+ */
+export interface Testbench {
+    name: string;
+    circuitRef: string;
+    dutInstanceId: string;
+    circuit: Circuit;
+    stimulus: StimulusSchedule;
+    capture?: CaptureConfig;
+    assertions?: AssertionSchedule;
+    maxCycles: number;
+}
+/**
+ * Compiled stimulus schedule
+ *
+ * Maps cycle number -> signal assignments for that cycle
+ * Signals hold their previous value unless explicitly changed
+ */
+export interface StimulusSchedule {
+    clockRef: string;
+    events: Map<number, StimulusAction[]>;
+}
+/**
+ * Single stimulus action (apply value to signal)
+ */
+export interface StimulusAction {
+    nodeId: string;
+    portName: string;
+    value: BitValue | BusValue;
+}
+/**
+ * Configuration for waveform capture
+ */
+export interface CaptureConfig {
+    signals: SignalRef[];
+    format: 'vcd';
+    filename: string;
+}
+/**
+ * Reference to a signal to capture
+ */
+export interface SignalRef {
+    nodeId: string;
+    portName: string;
+    displayName: string;
+    width: number;
+}
+/**
+ * Compiled assertion schedule
+ */
+export interface AssertionSchedule {
+    clockRef: string;
+    assertions: Map<number, CompiledAssertion[]>;
+}
+/**
+ * Single assertion to check at a cycle
+ */
+export interface CompiledAssertion {
+    id: string;
+    condition: (state: TestbenchState) => boolean;
+    message: string;
+}
+/**
+ * Testbench execution state
+ */
+export interface TestbenchState {
+    cycle: number;
+    portValues: Map<string, BitValue | BusValue>;
+    assertionResults: AssertionResult[];
+    captureData?: CaptureData;
+    status: 'running' | 'passed' | 'failed' | 'timeout';
+    failureReason?: string;
+}
+/**
+ * Result of an assertion check
+ */
+export interface AssertionResult {
+    assertionId: string;
+    cycle: number;
+    passed: boolean;
+    message: string;
+}
+/**
+ * Captured waveform data
+ */
+export interface CaptureData {
+    config: CaptureConfig;
+    traces: Map<string, TraceData>;
+}
+/**
+ * Trace data for a single signal
+ */
+export interface TraceData {
+    signal: SignalRef;
+    values: (BitValue | BusValue)[];
+    changes: Array<{
+        cycle: number;
+        value: BitValue | BusValue;
+    }>;
+}
+/**
+ * Create a stimulus schedule
+ */
+export declare function createStimulusSchedule(clockRef: string): StimulusSchedule;
+/**
+ * Add stimulus action to schedule
+ */
+export declare function addStimulusAction(schedule: StimulusSchedule, cycle: number, action: StimulusAction): void;
+/**
+ * Get stimulus actions for a cycle
+ */
+export declare function getStimulusActions(schedule: StimulusSchedule, cycle: number): StimulusAction[];
+/**
+ * Create signal reference key for maps
+ */
+export declare function signalKey(signal: SignalRef): string;
+/**
+ * Create a testbench state
+ */
+export declare function createTestbenchState(): TestbenchState;
+/**
+ * Check if testbench has passed all assertions
+ */
+export declare function hasPassed(state: TestbenchState): boolean;
+/**
+ * Check if testbench has failed any assertions
+ */
+export declare function hasFailed(state: TestbenchState): boolean;
+/**
+ * Get all failed assertions
+ */
+export declare function getFailedAssertions(state: TestbenchState): AssertionResult[];
+/**
+ * Get the maximum cycle number in the stimulus schedule
+ */
+export declare function getMaxStimulusCycle(schedule: StimulusSchedule): number;
+//# sourceMappingURL=testbench.d.ts.map

package/dist/editor/types/testbench.d.ts.map

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package/dist/editor/types/testbench.js

@@ -0,0 +1,85 @@
+/**
+ * Testbench Intermediate Representation (IR)
+ *
+ * This is the compiled, executable representation of testbenches.
+ * The testbench IR is generated from testbench AST by the testbench compiler.
+ *
+ * Design:
+ * - Bit-level stimulus core (cycle-by-cycle value assignments)
+ * - VCD waveform capture configuration
+ * - Future-proof for multi-clock and assertions
+ */
+// ============================================================================
+// Helper Functions
+// ============================================================================
+/**
+ * Create a stimulus schedule
+ */
+export function createStimulusSchedule(clockRef) {
+    return {
+        clockRef,
+        events: new Map(),
+    };
+}
+/**
+ * Add stimulus action to schedule
+ */
+export function addStimulusAction(schedule, cycle, action) {
+    if (!schedule.events.has(cycle)) {
+        schedule.events.set(cycle, []);
+    }
+    schedule.events.get(cycle).push(action);
+}
+/**
+ * Get stimulus actions for a cycle
+ */
+export function getStimulusActions(schedule, cycle) {
+    return schedule.events.get(cycle) || [];
+}
+/**
+ * Create signal reference key for maps
+ */
+export function signalKey(signal) {
+    return signal.nodeId === '' ? signal.portName : `${signal.nodeId}.${signal.portName}`;
+}
+/**
+ * Create a testbench state
+ */
+export function createTestbenchState() {
+    return {
+        cycle: 0,
+        portValues: new Map(),
+        assertionResults: [],
+        status: 'running',
+    };
+}
+/**
+ * Check if testbench has passed all assertions
+ */
+export function hasPassed(state) {
+    return state.status === 'passed' ||
+        (state.assertionResults.length > 0 &&
+            state.assertionResults.every(r => r.passed));
+}
+/**
+ * Check if testbench has failed any assertions
+ */
+export function hasFailed(state) {
+    return state.status === 'failed' ||
+        state.assertionResults.some(r => !r.passed);
+}
+/**
+ * Get all failed assertions
+ */
+export function getFailedAssertions(state) {
+    return state.assertionResults.filter(r => !r.passed);
+}
+/**
+ * Get the maximum cycle number in the stimulus schedule
+ */
+export function getMaxStimulusCycle(schedule) {
+    if (schedule.events.size === 0)
+        return 0;
+    return Math.max(...Array.from(schedule.events.keys()));
+}
+//# sourceMappingURL=testbench.js.map

package/dist/editor/types/testbench.js.map

@@ -0,0 +1 @@
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package/dist/editor/types/testing.d.ts

@@ -0,0 +1,88 @@
+/**
+ * Testing system types for the visual circuit editor
+ * Enables users to define test cases with expected inputs/outputs
+ */
+export type TestStatus = 'pending' | 'running' | 'passed' | 'failed' | 'error';
+/**
+ * Represents a single input or output value in a test case
+ */
+export interface TestValue {
+    /** Component label (e.g., "A", "B", "Sum") */
+    label: string;
+    /** Expected boolean value */
+    value: boolean;
+}
+/**
+ * Comparison result for a single output
+ */
+export interface OutputComparison {
+    label: string;
+    expected: boolean;
+    actual: boolean;
+    passed: boolean;
+}
+/**
+ * Test case definition
+ */
+export interface TestCase {
+    id: string;
+    name: string;
+    description?: string;
+    enabled: boolean;
+    inputs: TestValue[];
+    outputs: TestValue[];
+    createdAt: number;
+    updatedAt: number;
+}
+/**
+ * Result from executing a test case
+ */
+export interface TestResult {
+    testCaseId: string;
+    status: TestStatus;
+    /** Detailed comparison for each output */
+    comparisons?: OutputComparison[];
+    /** Error message if status is 'error' */
+    errorMessage?: string;
+    /** Timestamp of test execution */
+    executedAt: number;
+    /** Execution time in milliseconds */
+    duration: number;
+}
+/**
+ * State for the test store
+ */
+export interface TestState {
+    /** All test cases, keyed by ID */
+    testCases: Record<string, TestCase>;
+    /** Test results, keyed by test case ID */
+    results: Record<string, TestResult>;
+    /** Whether tests are currently running */
+    isRunning: boolean;
+    /** ID of currently editing test case (for modal) */
+    editingTestId: string | null;
+}
+/**
+ * Actions for the test store
+ */
+export interface TestActions {
+    /** Add a new test case */
+    addTestCase: (testCase: Omit<TestCase, 'id' | 'createdAt' | 'updatedAt'>) => string;
+    /** Update an existing test case */
+    updateTestCase: (id: string, updates: Partial<Omit<TestCase, 'id' | 'createdAt'>>) => void;
+    /** Remove a test case */
+    removeTestCase: (id: string) => void;
+    /** Toggle test case enabled/disabled */
+    toggleTestCase: (id: string) => void;
+    /** Duplicate a test case */
+    duplicateTestCase: (id: string) => string;
+    /** Set test result */
+    setTestResult: (testCaseId: string, result: TestResult) => void;
+    /** Clear all test results */
+    clearResults: () => void;
+    /** Set running state */
+    setIsRunning: (isRunning: boolean) => void;
+    /** Set editing test ID */
+    setEditingTestId: (id: string | null) => void;
+}
+//# sourceMappingURL=testing.d.ts.map

package/dist/editor/types/testing.d.ts.map

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package/dist/editor/types/testing.js

@@ -0,0 +1,6 @@
+/**
+ * Testing system types for the visual circuit editor
+ * Enables users to define test cases with expected inputs/outputs
+ */
+export {};
+//# sourceMappingURL=testing.js.map

package/dist/editor/types/testing.js.map

@@ -0,0 +1 @@
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