systemrdl 0.1.0 → 0.2.0

checksums.yaml

@@ -1,7 +1,7 @@
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data/README.md

@@ -105,8 +105,38 @@ end
 
 ## Scope
 
-This gem currently supports only the basic syntax needed to describe register maps that consist of address maps, registers, and fields.
-More advanced constructs of the SystemRDL language are not supported yet.
+### Supported Features
+
+The following SystemRDL 2.0 language features are supported (parsed and evaluated).
+
+#### Components
+
+* The `addrmap`, `regfile`, `reg`, `field`, and `mem` components
+* Definitive and anonymous component definitions/instances
+* Arrays of instances
+* Address allocation operators (`@`, `+=`, `%=`)
+* `internal` / `external` instance types
+
+#### Properties
+
+* Most built-in properties of the supported components, except the `counter` and `interrupt` property groups (see below)
+* Property assignment in all three forms: direct assignment, default assignment (`default`), and dynamic assignment (`->`)
+* Property references and instance references as property values
+
+### Unsupported Features
+
+The following features are not supported. Some of their keywords are recognized by the lexer (reserved), but they are not evaluated.
+
+* `signal` component
+* User-defined properties (`property` definitions)
+* Enumerations (`enum`) and `encode`
+* `struct` types
+* `constraint`
+* `alias` registers
+* Counter field properties
+* Interrupt field properties
+* Component parameters
+* Preprocessing, both embedded Perl preprocessing and Verilog-style directives
 
 ## Design notes
 

data/lib/systemrdl/evaluator/address_allocation.rb

@@ -8,8 +8,7 @@ module SystemRDL
       def allocate_addresses(instance)
         address = 0
         instance.instances.each do |child_inst|
-          # For now, support reg only
-          next unless child_inst.reg?
+          next unless addressable_inst?(child_inst)
 
           assign_address(address, instance, child_inst)
           address = calc_next_address(child_inst)
@@ -31,19 +30,29 @@ module SystemRDL
       end
 
       def calc_alignment(inst, child_inst)
-        inst_alignment = child_inst.alignment&.value
-        return inst_alignment if inst_alignment
+        alignment = child_inst.alignment&.value
+        return alignment if alignment
 
         alignments = [
-          inst.property_value(:alignment)&.value || 0,
+          inst_alignment(inst),
           child_inst.accesswidth / 8,
           alignment_by_addressing(inst, child_inst)
         ]
         alignments.max
       end
 
+      def inst_alignment(inst)
+        alignment =
+          if inst.mem?
+            inst.parent.property_value(:alignment)
+          else
+            inst.property_value(:alignment)
+          end
+        alignment&.value || 0
+      end
+
       def alignment_by_addressing(inst, child_inst)
-        addressing = inst.property_value(:addressing).value
+        addressing = effective_addressing(inst)
         case addressing
         when :compact then child_inst.accesswidth / 8
         when :regalign then aligned_size(child_inst)
@@ -51,6 +60,11 @@ module SystemRDL
         end
       end
 
+      def effective_addressing(inst)
+        addrmap = inst.find_addrmap
+        addrmap.property_value(:addressing).value
+      end
+
       def calc_fullalign_alignment(child_inst)
         return aligned_size(child_inst) unless child_inst.array?
 
@@ -72,26 +86,25 @@ module SystemRDL
         child_inst.address.value + delta
       end
 
-      def check_overlapping_regs(instance)
-        # For now, support reg only but not regfile
-        regs = instance.instances.select { |reg| reg.reg? && reg.first_element? }
-        regs.combination(2).each do |(reg_a, reg_b)|
-          next unless overlapping_pair?(reg_a, reg_b)
+      def check_overlapping_address_ranges(instance)
+        insts = instance.instances.select { |inst| addressable_inst?(inst) && inst.first_element? }
+        insts.combination(2).each do |(inst_a, inst_b)|
+          next unless overlapping_pair?(inst_a, inst_b)
 
-          message = 'overlapping regs not allowed'
-          raise_evaluation_error message, reg_a.token_range, reg_b.token_range
+          message = 'overlapping address ranges not allowed'
+          raise_evaluation_error message, inst_a.token_range, inst_b.token_range
         end
       end
 
-      def overlapping_pair?(reg_a, reg_b)
-        range_a = calc_address_range(reg_a)
-        range_b = calc_address_range(reg_b)
+      def overlapping_pair?(inst_a, inst_b)
+        range_a = calc_address_range(inst_a)
+        range_b = calc_address_range(inst_b)
         return false unless range_a.include?(range_b.begin) || range_b.include?(range_a.begin)
 
-        r_a = reg_a.sw_readable?
-        w_a = reg_a.sw_writable?
-        r_b = reg_b.sw_readable?
-        w_b = reg_b.sw_writable?
+        r_a = inst_a.sw_readable?
+        w_a = inst_a.sw_writable?
+        r_b = inst_b.sw_readable?
+        w_b = inst_b.sw_writable?
         (r_a && r_b) || (w_a && w_b)
       end
 
@@ -121,6 +134,10 @@ module SystemRDL
       def element_stride(child_inst)
         child_inst.stride&.value || aligned_size(child_inst)
       end
+
+      def addressable_inst?(inst)
+        inst.addrmap? || inst.regfile? || inst.mem? || inst.reg?
+      end
     end
   end
 end

data/lib/systemrdl/evaluator/address_operation.rb

@@ -77,7 +77,7 @@ module SystemRDL
 
         message =
           "stride less than #{instance.layer} size: " \
-          "stride 0x#{stride.value.to_s(16)} #{instance.layer} size #{size}"
+          "stride 0x#{stride.value.to_s(16)} size #{size}"
         raise_evaluation_error message, stride.token_range
       end
 

data/lib/systemrdl/evaluator/addrmap.rb

@@ -3,12 +3,11 @@
 module SystemRDL
   module Evaluator
     class AddrMapDefinition < ComponentDefinition
-      include AddressAllocation
-      include ContainerComponent
+      include BlockComponent
 
       def evaluate(instance, **optargs)
         if instance.root?
-          create_instance(instance, @id, nil, nil, nil, **optargs)
+          create_instance(instance, InstArgs.new(@id, nil, nil), nil, nil, **optargs)
         else
           super
         end
@@ -16,7 +15,7 @@ module SystemRDL
 
       def validate(instance)
         check_structural_component_instances(instance)
-        check_alignment(instance)
+        check_alignment_property(instance)
         check_endianness_exclusivity(instance)
         check_rsvdset_exclusivity(instance)
         check_bit_ordering_exclusivity(instance)
@@ -24,21 +23,29 @@ module SystemRDL
 
       def finalize(instance)
         allocate_addresses(instance)
-        check_overlapping_regs(instance)
+        check_address_operations(instance)
+        check_overlapping_address_ranges(instance)
       end
 
       def layer
         :addrmap
       end
 
+      def support_inst_type?(inst_type)
+        inst_type.nil?
+      end
+
       private
 
       def instance_class
         AddrMapInstance
       end
 
-      def check_alignment(instance)
-        check_power_of_2(instance, :alignment, 1)
+      def apply_inst_values(instance, inst_values)
+        return if instance.parent.root?
+
+        apply_address_operations(instance, inst_values)
+        check_range(inst_values)
       end
 
       def check_endianness_exclusivity(instance)
@@ -55,12 +62,14 @@ module SystemRDL
     end
 
     class AddrMapInstance < Instance
+      include BlockInstance
+
       def definable?(definition)
-        definition.layer in :addrmap | :regfile | :reg | :field
+        definition.layer in :addrmap | :regfile | :mem | :reg | :field
       end
 
       def instantiable?(definition)
-        definition.layer in :addrmap | :regfile | :reg
+        definition.layer in :addrmap | :regfile | :mem | :reg
       end
     end
   end

data/lib/systemrdl/evaluator/array_component.rb

@@ -11,6 +11,10 @@ module SystemRDL
     module ArrayComponent
       private
 
+      def apply_array(instance, array_info)
+        instance.array_info = array_info
+      end
+
       def eval_array(inst_values)
         array = inst_values[:array]
         return super unless array
@@ -24,8 +28,8 @@ module SystemRDL
 
         index_list =
           sizes
-            .map { |size| size.times.to_a }
-            .then { |list| list[0].product(*list[1..]) }
+          .map { |size| size.times.to_a }
+          .then { |list| list[0].product(*list[1..]) }
         id = array_id
         index_list.each.with_index(1) do |indices, i|
           info = ArrayInfo.new(id, indices, sizes, i == 1, i == index_list.size)
@@ -38,5 +42,29 @@ module SystemRDL
         @array_id += 1
       end
     end
+
+    module ArrayInstance
+      attr_accessor :array_info
+
+      def array?
+        !array_info.nil?
+      end
+
+      def array_indices
+        array_info&.indices
+      end
+
+      def array_sizes
+        array_info&.sizes
+      end
+
+      def first_element?
+        !array? || array_info.first
+      end
+
+      def last_element?
+        !array? || array_info.last
+      end
+    end
   end
 end

data/lib/systemrdl/evaluator/block_component.rb

@@ -0,0 +1,42 @@
+# frozen_string_literal: true
+
+module SystemRDL
+  module Evaluator
+    module BlockComponent
+      include ArrayComponent
+      include AddressOperation
+      include ContainerComponent
+      include AddressAllocation
+
+      private
+
+      def check_alignment_property(instance)
+        check_power_of_2(instance, :alignment, 1)
+      end
+    end
+
+    module BlockInstance
+      include ArrayInstance
+
+      attr_accessor :address
+      attr_accessor :stride
+      attr_accessor :alignment
+
+      def accesswidth
+        @accesswidth ||= instances.map(&:accesswidth).max
+      end
+
+      def size
+        @size ||= instances.map { |inst| inst.address.value + inst.size }.max
+      end
+
+      def sw_readable?
+        true
+      end
+
+      def sw_writable?
+        true
+      end
+    end
+  end
+end

data/lib/systemrdl/evaluator/builtin_properties.rb

@@ -23,6 +23,7 @@ module SystemRDL
       #
       def_property :accesswidth do |prop|
         prop.targets = [:reg]
+        prop.exist = true
         prop.types = [:longint]
         prop.dynamic_assign = true
         prop.ref_target = false
@@ -31,6 +32,7 @@ module SystemRDL
 
       def_property :addressing do |prop|
         prop.targets = [:addrmap]
+        prop.exist = true
         prop.types = [:addressingtype]
         prop.dynamic_assign = false
         prop.ref_target = false
@@ -40,14 +42,19 @@ module SystemRDL
 
       def_property :alignment do |prop|
         prop.targets = [:addrmap, :regfile]
+        prop.exist = true
         prop.types = [:longint]
         prop.dynamic_assign = false
         prop.ref_target = false
         prop.per_element_assign = false
+        prop.default_value = proc do |inst|
+          (inst.regfile? && inst.parent.property_value(:alignment)) || nil
+        end
       end
 
       def_property :anded do |prop|
         prop.targets = [:field]
+        prop.exist = true
         prop.types = [:boolean]
         prop.dynamic_assign = true
         prop.ref_target = true
@@ -57,6 +64,7 @@ module SystemRDL
 
       def_property :bigendian do |prop|
         prop.targets = [:addrmap]
+        prop.exist = true
         prop.types = [:boolean]
         prop.dynamic_assign = true
         prop.ref_target = false
@@ -66,6 +74,7 @@ module SystemRDL
 
       def_property :desc do |prop|
         prop.types = [:string]
+        prop.exist = true
         prop.dynamic_assign = true
         prop.ref_target = false
         prop.per_element_assign = true
@@ -74,6 +83,7 @@ module SystemRDL
 
       def_property :errextbus do |prop|
         prop.targets = [:addrmap, :regfile, :reg]
+        prop.exist = true
         prop.types = [:boolean]
         prop.dynamic_assign = false
         prop.ref_target = false
@@ -83,6 +93,7 @@ module SystemRDL
 
       def_property :fieldwidth do |prop|
         prop.targets = [:field]
+        prop.exist = true
         prop.types = [:longint]
         prop.dynamic_assign = false
         prop.per_element_assign = false
@@ -91,6 +102,7 @@ module SystemRDL
 
       def_property :hw do |prop|
         prop.targets = [:field]
+        prop.exist = true
         prop.types = [:accesstype]
         prop.dynamic_assign = false
         prop.ref_target = false
@@ -100,6 +112,7 @@ module SystemRDL
 
       def_property :hwclr do |prop|
         prop.targets = [:field]
+        prop.exist = true
         prop.types = [:boolean, :field_reference, :property_reference]
         prop.dynamic_assign = true
         prop.ref_target = proc { set? }
@@ -109,6 +122,7 @@ module SystemRDL
 
       def_property :hwenable do |prop|
         prop.targets = [:field]
+        prop.exist = true
         prop.types = [:field_reference, :property_reference]
         prop.dynamic_assign = true
         prop.ref_target = proc { set? }
@@ -117,6 +131,7 @@ module SystemRDL
 
       def_property :hwmask do |prop|
         prop.targets = [:field]
+        prop.exist = true
         prop.types = [:field_reference, :property_reference]
         prop.dynamic_assign = true
         prop.ref_target = proc { set? }
@@ -125,6 +140,7 @@ module SystemRDL
 
       def_property :hwset do |prop|
         prop.targets = [:field]
+        prop.exist = true
         prop.types = [:boolean, :field_reference, :property_reference]
         prop.dynamic_assign = true
         prop.ref_target = proc { set? }
@@ -134,6 +150,7 @@ module SystemRDL
 
       def_property :littleendian do |prop|
         prop.targets = [:addrmap]
+        prop.exist = true
         prop.types = [:boolean]
         prop.dynamic_assign = true
         prop.ref_target = false
@@ -143,6 +160,7 @@ module SystemRDL
 
       def_property :lsb0 do |prop|
         prop.targets = [:addrmap]
+        prop.exist = true
         prop.types = [:boolean]
         prop.dynamic_assign = false
         prop.ref_target = false
@@ -150,8 +168,28 @@ module SystemRDL
         prop.default_value = false
       end
 
+      def_property :mementries do |prop|
+        prop.targets = [:mem]
+        prop.exist = true
+        prop.types = [:longint]
+        prop.dynamic_assign = false
+        prop.ref_target = false
+        prop.per_element_assign = false
+        prop.default_value = 1
+      end
+
+      def_property :memwidth do |prop|
+        prop.targets = [:mem]
+        prop.exist = true
+        prop.types = [:longint]
+        prop.dynamic_assign = false
+        prop.ref_target = false
+        prop.per_element_assign = false
+      end
+
       def_property :msb0 do |prop|
         prop.targets = [:addrmap]
+        prop.exist = true
         prop.types = [:boolean]
         prop.dynamic_assign = false
         prop.ref_target = false
@@ -161,6 +199,7 @@ module SystemRDL
 
       def_property :name do |prop|
         prop.types = [:string]
+        prop.exist = true
         prop.dynamic_assign = true
         prop.ref_target = false
         prop.per_element_assign = true
@@ -169,6 +208,7 @@ module SystemRDL
 
       def_property :next do |prop|
         prop.targets = [:field]
+        prop.exist = true
         prop.types = [:field_reference, :property_reference]
         prop.dynamic_assign = true
         prop.per_element_assign = false
@@ -177,6 +217,7 @@ module SystemRDL
 
       def_property :onread do |prop|
         prop.targets = [:field]
+        prop.exist = proc { |inst| !inst.virtual_field? }
         prop.types = [:onreadtype]
         prop.dynamic_assign = true
         prop.ref_target = false
@@ -185,6 +226,7 @@ module SystemRDL
 
       def_property :onwrite do |prop|
         prop.targets = [:field]
+        prop.exist = proc { |inst| !inst.virtual_field? }
         prop.types = [:onwritetype]
         prop.dynamic_assign = true
         prop.ref_target = false
@@ -193,6 +235,7 @@ module SystemRDL
 
       def_property :ored do |prop|
         prop.targets = [:field]
+        prop.exist = true
         prop.types = [:boolean]
         prop.dynamic_assign = true
         prop.ref_target = true
@@ -202,6 +245,7 @@ module SystemRDL
 
       def_property :paritycheck do |prop|
         prop.targets = [:field]
+        prop.exist = true
         prop.types = [:boolean]
         prop.dynamic_assign = false
         prop.ref_target = false
@@ -211,6 +255,7 @@ module SystemRDL
 
       def_property :precedence do |prop|
         prop.targets = [:field]
+        prop.exist = true
         prop.types = [:precedencetype]
         prop.dynamic_assign = true
         prop.ref_target = false
@@ -220,6 +265,7 @@ module SystemRDL
 
       def_property :rclr do |prop|
         prop.targets = [:field]
+        prop.exist = proc { |inst| !inst.virtual_field? }
         prop.types = [:boolean]
         prop.dynamic_assign = true
         prop.ref_target = false
@@ -229,6 +275,7 @@ module SystemRDL
 
       def_property :regwidth do |prop|
         prop.targets = [:reg]
+        prop.exist = true
         prop.types = [:longint]
         prop.dynamic_assign = false
         prop.ref_target = false
@@ -238,6 +285,7 @@ module SystemRDL
 
       def_property :reset do |prop|
         prop.targets = [:field]
+        prop.exist = true
         prop.types = [:bit, :field_reference, :property_reference]
         prop.dynamic_assign = true
         prop.ref_target = proc { set? }
@@ -246,6 +294,7 @@ module SystemRDL
 
       def_property :resetsignal do |prop|
         prop.targets = [:field]
+        prop.exist = true
         prop.types = [:field_reference, :property_reference]
         prop.dynamic_assign = true
         prop.ref_target = proc { set? }
@@ -254,6 +303,7 @@ module SystemRDL
 
       def_property :rset do |prop|
         prop.targets = [:field]
+        prop.exist = proc { |inst| !inst.virtual_field? }
         prop.types = [:boolean]
         prop.dynamic_assign = true
         prop.ref_target = false
@@ -263,6 +313,7 @@ module SystemRDL
 
       def_property :rsvdset do |prop|
         prop.targets = [:addrmap]
+        prop.exist = true
         prop.types = [:boolean]
         prop.dynamic_assign = false
         prop.ref_target = false
@@ -272,6 +323,7 @@ module SystemRDL
 
       def_property :rsvdsetX do |prop|
         prop.targets = [:addrmap]
+        prop.exist = true
         prop.types = [:boolean]
         prop.dynamic_assign = false
         prop.ref_target = false
@@ -281,6 +333,7 @@ module SystemRDL
 
       def_property :shared do |prop|
         prop.targets = [:reg]
+        prop.exist = true
         prop.types = [:boolean]
         prop.dynamic_assign = false
         prop.ref_target = false
@@ -290,6 +343,7 @@ module SystemRDL
 
       def_property :sharedextbus do |prop|
         prop.targets = [:addrmap, :regfile]
+        prop.exist = true
         prop.types = [:boolean]
         prop.dynamic_assign = false
         prop.ref_target = false
@@ -299,6 +353,7 @@ module SystemRDL
 
       def_property :singlepulse do |prop|
         prop.targets = [:field]
+        prop.exist = proc { |inst| !inst.virtual_field? }
         prop.types = [:boolean]
         prop.dynamic_assign = true
         prop.ref_target = false
@@ -307,7 +362,8 @@ module SystemRDL
       end
 
       def_property :sw do |prop|
-        prop.targets = [:field]
+        prop.targets = [:mem, :field]
+        prop.exist = true
         prop.types = [:accesstype]
         prop.dynamic_assign = true
         prop.ref_target = false
@@ -317,6 +373,7 @@ module SystemRDL
 
       def_property :swacc do |prop|
         prop.targets = [:field]
+        prop.exist = proc { |inst| !inst.virtual_field? }
         prop.types = [:boolean]
         prop.dynamic_assign = true
         prop.ref_target = true
@@ -326,6 +383,7 @@ module SystemRDL
 
       def_property :swmod do |prop|
         prop.targets = [:field]
+        prop.exist = proc { |inst| !inst.virtual_field? }
         prop.types = [:boolean]
         prop.dynamic_assign = true
         prop.ref_target = true
@@ -335,6 +393,7 @@ module SystemRDL
 
       def_property :swwe do |prop|
         prop.targets = [:field]
+        prop.exist = proc { |inst| !inst.virtual_field? }
         prop.types = [:boolean, :field_reference, :property_reference]
         prop.dynamic_assign = true
         prop.ref_target = proc { set? }
@@ -344,6 +403,7 @@ module SystemRDL
 
       def_property :swwel do |prop|
         prop.targets = [:field]
+        prop.exist = proc { |inst| !inst.virtual_field? }
         prop.types = [:boolean, :field_reference, :property_reference]
         prop.dynamic_assign = true
         prop.ref_target = proc { set? }
@@ -353,6 +413,7 @@ module SystemRDL
 
       def_property :we do |prop|
         prop.targets = [:field]
+        prop.exist = true
         prop.types = [:boolean, :field_reference, :property_reference]
         prop.dynamic_assign = true
         prop.ref_target = proc { set? }
@@ -362,6 +423,7 @@ module SystemRDL
 
       def_property :wel do |prop|
         prop.targets = [:field]
+        prop.exist = true
         prop.types = [:boolean, :field_reference, :property_reference]
         prop.dynamic_assign = true
         prop.ref_target = proc { set? }
@@ -371,6 +433,7 @@ module SystemRDL
 
       def_property :woclr do |prop|
         prop.targets = [:field]
+        prop.exist = proc { |inst| !inst.virtual_field? }
         prop.types = [:boolean]
         prop.dynamic_assign = true
         prop.ref_target = false
@@ -380,6 +443,7 @@ module SystemRDL
 
       def_property :woset do |prop|
         prop.targets = [:field]
+        prop.exist = proc { |inst| !inst.virtual_field? }
         prop.types = [:boolean]
         prop.dynamic_assign = true
         prop.ref_target = false
@@ -389,6 +453,7 @@ module SystemRDL
 
       def_property :xored do |prop|
         prop.targets = [:field]
+        prop.exist = true
         prop.types = [:boolean]
         prop.dynamic_assign = true
         prop.ref_target = true