ruby-vpi 10.0.0 → 11.0.0

data/HISTORY

@@ -12,6 +12,36 @@ We _strictly_ follow the RubyGems project's "rational versioning policy":http://
 fn1. C. Gross, "Explaining Open Source Version Numbers", [Online document], 2005 Nov 28, [cited 2006 Aug 27], Available HTTP: "http://ablog.apress.com/?p=738":http://ablog.apress.com/?p=738
 
 
+h1. Version 11.0.0 (2006-11-05)
+
+h2. Summary
+
+This release shortens generated Ruby benches and uses the less confusing notation for defining "singleton methods":http://wiki.rubygarden.org/Ruby/page/show/SingletonTutorial in generated designs and prototypes.
+
+h2. Notice
+
+* The arguments for the "@RubyVPI.init_bench@ method":ref/ruby/classes/RubyVpi.html have changed.
+
+* *generate_test.rb* no longer emits undocumented status indicators: _name_ and _format_.
+
+* The source code is no longer distributed as a *zip* package, because it seems to be quite underutilized in comparison to the *tgz* and *gem* packages.
+
+h2. Detail
+
+* Generated Ruby benches have been shortened to just _one_ line of code!
+
+* The less confusing notation of <pre>def some_object.a_singleton_method
+  do_stuff
+end</pre> is now used instead of the <pre>class << some_object
+  def a_singleton_method
+    do_stuff
+  end
+end</pre> notation.
+** The tutorial and examples have been updated accordingly.
+
+* The pipelined ALU example now has an updated @IntegerGenerator@ class.
+
+
 h1. Version 10.0.0 (2006-11-05)
 
 h2. Summary

data/Rakefile

@@ -244,7 +244,6 @@ spec = Gem::Specification.new do |s|
 end
 
 Rake::GemPackageTask.new(spec) do |pkg|
-  pkg.need_zip = true
   pkg.need_tar = true
 end
 

data/bin/generate_test.rb

@@ -8,9 +8,10 @@
 # skip:: File will be skipped because it is already up to date.
 # update:: File will be updated because it is out of date. A backup copy will be made before the file is updated. Use a text merging tool (see MERGER) or manually transfer any necessary information from the backup copy to the updated file.
 # backup:: A backup copy of a file is being made.
+# module:: A Verilog module has been identified.
 #
 # = Environment variables
-# MERGER:: A command that invokes a text merging tool with two arguments: old file, new file. The tool's output should be written to the new file.
+# MERGER:: A command that invokes a text merging tool with two arguments: (1) old file, (2) new file. The tool's output should be written to the new file.
 
 
 =begin
@@ -170,15 +171,12 @@ if File.basename($0) == File.basename(__FILE__)
       optSpecFmt = :rSpec if val
     end
 
-    opts.on '-n', '--name NAME', 'attach NAME indentifier to generated test' do |val|
+    opts.on '-n', '--name NAME', 'insert NAME into the names of generated files' do |val|
       optTestName = val
     end
 
     opts.parse! ARGV
 
-    notify :name, optTestName
-    notify :format, optSpecFmt
-
 
   v = VerilogParser.new(ARGF.read)
 

data/bin/generate_test_tpl/bench.rb

@@ -1,31 +1,7 @@
 # This file is the Ruby side of the bench.
 
-require 'ruby-vpi'
-<%
-  case aOutputInfo.specFormat
-    when :xUnit
-%>
-require 'test/unit'
-<%
-    when :rSpec
-%>
-require 'ruby-vpi/rspec'
-<%
-  end
-%>
+RubyVpi.init_bench :<%= aOutputInfo.designClassName %>, :<%= aOutputInfo.specFormat %>
+<% if aOutputInfo.specFormat == :generic %>
 
-RubyVpi.init_bench '<%= aModuleInfo.name + aOutputInfo.suffix %>', :<%= aOutputInfo.designClassName %>
-
-# service the $ruby_relay callback
-<%
-  case aOutputInfo.specFormat
-    when :xUnit, :rSpec
-%>
-  # The <%= aOutputInfo.specFormat %> library will take control henceforth.
-<%
-  else
-%>
-  <%= aOutputInfo.specClassName + '.new' %>
-<%
-  end
-%>
+<%= aOutputInfo.specClassName + '.new' %>
+<% end %>

data/bin/generate_test_tpl/bench.v

@@ -31,9 +31,7 @@ module <%= aOutputInfo.verilogBenchName %>;
   // connect to the Ruby side of this bench
     initial begin
       <%= clockSignal %> = 0;
-      $ruby_init("ruby", "-w", "-rubygems", "<%= aOutputInfo.rubyBenchPath %>"<%=
-        %{, "-f", "s"} if aOutputInfo.specFormat == :rSpec
-      %>);
+      $ruby_init("ruby", "-w", "-rubygems", "-rruby-vpi", "<%= aOutputInfo.rubyBenchPath %>");
     end
 
     always begin

data/bin/generate_test_tpl/design.rb

@@ -3,10 +3,9 @@
 <%= var.name.to_ruby_const_name %> = <%= var.value.verilog_to_ruby %>
 <% end %>
 
-class << <%= aOutputInfo.designClassName %>
-  def reset!
+# This method resets the design under test.
+def <%= aOutputInfo.designClassName %>.reset!
 <% aModuleInfo.ports.select { |p| p.input? }[1..-1].each do |port| # using [1..] because the first signal is the clock %>
-    <%= port.name %>.hexStrVal = 'x'
+  <%= port.name %>.hexStrVal = 'x'
 <% end %>
-  end
 end

data/bin/generate_test_tpl/proto.rb

@@ -1,15 +1,14 @@
 # This is a prototype of the design under test.
-class << <%= aOutputInfo.designClassName %>
-  # When prototyping is enabled, this method is invoked
-  # instead of Vpi::relay_verilog to simulate the design.
-  def simulate!
-    # discard old outputs
+
+# When prototyping is enabled, relay_verilog invokes this method
+# instead of transferring control to the Verilog simulator.
+def <%= aOutputInfo.designClassName %>.simulate!
+  # discard old outputs
 <% aModuleInfo.ports.reject { |p| p.input? }.each do |port| %>
-      <%= port.name %>.hexStrVal = 'x'
+    <%= port.name %>.hexStrVal = 'x'
 <% end %>
 
-    # process new inputs
+  # process new inputs
 
-    # produce new outputs
-  end
+  # produce new outputs
 end

data/doc/manual.txt

@@ -1033,12 +1033,10 @@ end
                 and counter_xunit_design.rb with the following code. This code
                 defines the reset! method which resets our Verilog design.
 
-                class << Counter
-                  def reset!
-                    reset.intVal = 1
-                    relay_verilog # advance the clock
-                    reset.intVal = 0
-                  end
+                def Counter.reset!
+                  reset.intVal = 1
+                  relay_verilog # advance the clock
+                  reset.intVal = 0
                 end
 
 
@@ -1052,13 +1050,11 @@ Verilog design” shows the completed prototype for our design.
 
 Figure 4.6. Ruby prototype of our Verilog design
 
-class << Counter
-  def simulate!
-    if reset.intVal == 1
-      count.intVal = 0
-    else
-      count.intVal += 1
-    end
+def Counter.simulate!
+  if reset.intVal == 1
+    count.intVal = 0
+  else
+    count.intVal += 1
   end
 end
 

data/doc/src/manual.xml

@@ -1306,12 +1306,10 @@ kdiff3 --auto --merge --output "$2" "$@" 2>/dev/null
               <para>Replace the contents of the files named <filename>counter_rspec_design.rb</filename> and <filename>counter_xunit_design.rb</filename> with the following code. This code defines the <function>reset!</function> method which resets our &v; design.</para>
 
 <programlisting>
-<token>class</token> &lt;&lt; <constant>Counter</constant>
-  <token>def</token> <function>reset!</function>
-    <function>reset</function>.<function>intVal</function> = <literal>1</literal>
-    <function>relay_verilog</function> <remark># advance the clock</remark>
-    <function>reset</function>.<function>intVal</function> = <literal>0</literal>
-  <token>end</token>
+<token>def</token> <constant>Counter</constant>.<function>reset!</function>
+  <function>reset</function>.<function>intVal</function> = <literal>1</literal>
+  <function>relay_verilog</function> <remark># advance the clock</remark>
+  <function>reset</function>.<function>intVal</function> = <literal>0</literal>
 <token>end</token>
 </programlisting>
             </listitem>
@@ -1327,13 +1325,11 @@ kdiff3 --auto --merge --output "$2" "$@" 2>/dev/null
         <figure id="fig..counter_proto.rb">
           <title>Ruby prototype of our &v; design</title>
 <programlisting>
-<token>class</token> &lt;&lt; <constant>Counter</constant>
-  <token>def</token> <function>simulate!</function>
-    <token>if</token> <function>reset</function>.<function>intVal</function> == <literal>1</literal>
-      <function>count</function>.<function>intVal</function> = <literal>0</literal>
-    <token>else</token>
-      <function>count</function>.<function>intVal</function> += <literal>1</literal>
-    <token>end</token>
+<token>def</token> <constant>Counter</constant>.<function>simulate!</function>
+  <token>if</token> <function>reset</function>.<function>intVal</function> == <literal>1</literal>
+    <function>count</function>.<function>intVal</function> = <literal>0</literal>
+  <token>else</token>
+    <function>count</function>.<function>intVal</function> += <literal>1</literal>
   <token>end</token>
 <token>end</token>
 </programlisting>

data/doc/usage.tutorial.html

@@ -116,21 +116,17 @@
   <span class="token">end</span>
 <span class="token">end</span>
 </pre></div><div class="important" style="margin-left: 0.5in; margin-right: 0.5in;"><table border="0" summary="Important: Before we continue…"><tr><td rowspan="2" align="center" valign="top" width="25"><img alt="[Important]" src="images/important.png" /></td><th align="left">Before we continue…</th></tr><tr><td align="left" valign="top"><div class="itemizedlist"><ul type="disc"><li><p>Replace the contents of the file named <code class="filename">counter_rspec_spec.rb</code> with the source code shown in <a href="usage.tutorial.html#fig..counter_rspec_spec.rb" title="Figure 4.4. Specification implemented in rSpec format">Figure 4.4, “Specification implemented in rSpec format”</a>.</p></li><li><p>Replace the contents of the file named <code class="filename">counter_xunit_spec.rb</code> with the source code shown in <a href="usage.tutorial.html#fig..counter_xunit_spec.rb" title="Figure 4.5. Specification implemented in xUnit format">Figure 4.5, “Specification implemented in xUnit format”</a>.</p></li><li><p>Replace the contents of the files named <code class="filename">counter_rspec_design.rb</code> and <code class="filename">counter_xunit_design.rb</code> with the following code. This code defines the <code class="function">reset!</code> method which resets our Verilog design.</p><pre class="programlisting">
-<span class="token">class</span> &lt;&lt; <code class="constant">Counter</code>
-  <span class="token">def</span> <code class="function">reset!</code>
-    <code class="function">reset</code>.<code class="function">intVal</code> = <code class="literal">1</code>
-    <code class="function">relay_verilog</code> <em><span class="remark"># advance the clock</span></em>
-    <code class="function">reset</code>.<code class="function">intVal</code> = <code class="literal">0</code>
-  <span class="token">end</span>
+<span class="token">def</span> <code class="constant">Counter</code>.<code class="function">reset!</code>
+  <code class="function">reset</code>.<code class="function">intVal</code> = <code class="literal">1</code>
+  <code class="function">relay_verilog</code> <em><span class="remark"># advance the clock</span></em>
+  <code class="function">reset</code>.<code class="function">intVal</code> = <code class="literal">0</code>
 <span class="token">end</span>
 </pre></li></ul></div></td></tr></table></div></div><div class="section" lang="en" xml:lang="en"><div class="titlepage"><div><div><h3 class="title"><a id="usage.tutorial.implement-proto"></a>Implement the prototype</h3></div></div></div><p>Now that we have a <a href="glossary.html#term..specification">Specification</a> against which to verify our <a href="glossary.html#term..design">Design</a>, let us build a prototype of our design. By doing so, we exercise our specification, experience potential problems that may arise when we later implement our design in Verilog, and gain confidence in our work. <a href="usage.tutorial.html#fig..counter_proto.rb" title="Figure 4.6. Ruby prototype of our Verilog design">Figure 4.6, “Ruby prototype of our Verilog design”</a> shows the completed prototype for our design.</p><div class="figure"><a id="fig..counter_proto.rb"></a><p class="title"><b>Figure 4.6. Ruby prototype of our Verilog design</b></p><pre class="programlisting">
-<span class="token">class</span> &lt;&lt; <code class="constant">Counter</code>
-  <span class="token">def</span> <code class="function">simulate!</code>
-    <span class="token">if</span> <code class="function">reset</code>.<code class="function">intVal</code> == <code class="literal">1</code>
-      <code class="function">count</code>.<code class="function">intVal</code> = <code class="literal">0</code>
-    <span class="token">else</span>
-      <code class="function">count</code>.<code class="function">intVal</code> += <code class="literal">1</code>
-    <span class="token">end</span>
+<span class="token">def</span> <code class="constant">Counter</code>.<code class="function">simulate!</code>
+  <span class="token">if</span> <code class="function">reset</code>.<code class="function">intVal</code> == <code class="literal">1</code>
+    <code class="function">count</code>.<code class="function">intVal</code> = <code class="literal">0</code>
+  <span class="token">else</span>
+    <code class="function">count</code>.<code class="function">intVal</code> += <code class="literal">1</code>
   <span class="token">end</span>
 <span class="token">end</span>
 </pre></div><div class="important" style="margin-left: 0.5in; margin-right: 0.5in;"><table border="0" summary="Important: Before we continue…"><tr><td rowspan="2" align="center" valign="top" width="25"><img alt="[Important]" src="images/important.png" /></td><th align="left">Before we continue…</th></tr><tr><td align="left" valign="top"><p>Replace the contents of the files named <code class="filename">counter_rspec_proto.rb</code> and <code class="filename">counter_xunit_proto.rb</code> with the source code shown in <a href="usage.tutorial.html#fig..counter_proto.rb" title="Figure 4.6. Ruby prototype of our Verilog design">Figure 4.6, “Ruby prototype of our Verilog design”</a>.</p></td></tr></table></div></div><div class="section" lang="en" xml:lang="en"><div class="titlepage"><div><div><h3 class="title"><a id="usage.tutorial.test-proto"></a>Verify the prototype</h3></div></div></div><p>Now that we have implemented our prototype, we are ready to verify it against our <a href="glossary.html#term..specification">Specification</a> by running the <a href="glossary.html#term..test">Test</a>. <a href="usage.tutorial.html#fig..test-proto.rspec" title="Figure 4.7. Running a test with specification in rSpec format">Figure 4.7, “Running a test with specification in rSpec format”</a> and <a href="usage.tutorial.html#fig..test-proto.unit-test" title="Figure 4.8. Running a test with specification in xUnit format">Figure 4.8, “Running a test with specification in xUnit format”</a> illustrate this process.</p><div class="tip" style="margin-left: 0.5in; margin-right: 0.5in;"><table border="0" summary="Tip: Reuse your past efforts!"><tr><td rowspan="2" align="center" valign="top" width="25"><img alt="[Tip]" src="images/tip.png" /></td><th align="left">Reuse your past efforts!</th></tr><tr><td align="left" valign="top"><p>The <span class="emphasis"><em>same</em></span> specification can be used to verify both prototype and design.</p></td></tr></table></div><p>Here, the <code class="varname">PROTOTYPE</code> environment variable is assigned a non-empty value while running the test, so that, instead of our design, our prototype is verified against our specification. You can also assign a value to <code class="varname">PROTOTYPE</code> before running the test, by using your shell's <span><strong class="command">export</strong></span> or <span><strong class="command">setenv</strong></span> command. Finally, the Icarus Verilog simulator, denoted by <em class="replaceable"><code>cver</code></em>, is used to run the simulation.</p><div class="tip" style="margin-left: 0.5in; margin-right: 0.5in;"><table border="0" summary="Tip: What can the test runner do?"><tr><td rowspan="2" align="center" valign="top" width="25"><img alt="[Tip]" src="images/tip.png" /></td><th align="left">What can the test runner do?</th></tr><tr><td align="left" valign="top"><p>If you invoke the test runner (1) without any arguments or (2) with the <code class="option">-T</code> option, it will show you a list of tasks that it can perform for you.</p></td></tr></table></div><div class="figure"><a id="fig..test-proto.rspec"></a><p class="title"><b>Figure 4.7. Running a test with specification in rSpec format</b></p><pre class="screen">

data/history.html

@@ -113,6 +113,60 @@ We <em>strictly</em> follow the RubyGems project&#8217;s <a href="http://www.rub
 	<p id="fn1"><sup>1</sup> C. Gross, &#8220;Explaining Open Source Version Numbers&#8221;, [Online document], 2005 Nov 28, [cited 2006 Aug 27], Available <span class="caps">HTTP</span>: <a href="http://ablog.apress.com/?p=738">http://ablog.apress.com/?p=738</a></p>
 
 
+	<h1>Version 11.0.0 (2006-11-05)</h1>
+
+
+	<h2>Summary</h2>
+
+
+	<p>This release shortens generated Ruby benches and uses the less confusing notation for defining <a href="http://wiki.rubygarden.org/Ruby/page/show/SingletonTutorial">singleton methods</a> in generated designs and prototypes.</p>
+
+
+	<h2>Notice</h2>
+
+
+	<ul>
+	<li>The arguments for the <a href="ref/ruby/classes/RubyVpi.html"><code>RubyVPI.init_bench</code> method</a> have changed.</li>
+	</ul>
+
+
+	<ul>
+	<li><strong>generate_test.rb</strong> no longer emits undocumented status indicators: <em>name</em> and <em>format</em>.</li>
+	</ul>
+
+
+	<ul>
+	<li>The source code is no longer distributed as a <strong>zip</strong> package, because it seems to be quite underutilized in comparison to the <strong>tgz</strong> and <strong>gem</strong> packages.</li>
+	</ul>
+
+
+	<h2>Detail</h2>
+
+
+	<ul>
+	<li>Generated Ruby benches have been shortened to just <em>one</em> line of code!</li>
+	</ul>
+
+
+	<ul>
+	<li>The less confusing notation of <pre>def some_object.a_singleton_method
+  do_stuff
+end</pre> is now used instead of the <pre>class &lt;&lt; some_object
+  def a_singleton_method
+    do_stuff
+  end
+end</pre> notation.
+	<ul>
+	<li>The tutorial and examples have been updated accordingly.</li>
+	</ul></li>
+	</ul>
+
+
+	<ul>
+	<li>The pipelined <span class="caps">ALU</span> example now has an updated <code>IntegerGenerator</code> class.</li>
+	</ul>
+
+
 	<h1>Version 10.0.0 (2006-11-05)</h1>
 
 

data/history.part.html

@@ -18,6 +18,60 @@ We <em>strictly</em> follow the RubyGems project&#8217;s <a href="http://www.rub
 	<p id="fn1"><sup>1</sup> C. Gross, &#8220;Explaining Open Source Version Numbers&#8221;, [Online document], 2005 Nov 28, [cited 2006 Aug 27], Available <span class="caps">HTTP</span>: <a href="http://ablog.apress.com/?p=738">http://ablog.apress.com/?p=738</a></p>
 
 
+	<h1>Version 11.0.0 (2006-11-05)</h1>
+
+
+	<h2>Summary</h2>
+
+
+	<p>This release shortens generated Ruby benches and uses the less confusing notation for defining <a href="http://wiki.rubygarden.org/Ruby/page/show/SingletonTutorial">singleton methods</a> in generated designs and prototypes.</p>
+
+
+	<h2>Notice</h2>
+
+
+	<ul>
+	<li>The arguments for the <a href="ref/ruby/classes/RubyVpi.html"><code>RubyVPI.init_bench</code> method</a> have changed.</li>
+	</ul>
+
+
+	<ul>
+	<li><strong>generate_test.rb</strong> no longer emits undocumented status indicators: <em>name</em> and <em>format</em>.</li>
+	</ul>
+
+
+	<ul>
+	<li>The source code is no longer distributed as a <strong>zip</strong> package, because it seems to be quite underutilized in comparison to the <strong>tgz</strong> and <strong>gem</strong> packages.</li>
+	</ul>
+
+
+	<h2>Detail</h2>
+
+
+	<ul>
+	<li>Generated Ruby benches have been shortened to just <em>one</em> line of code!</li>
+	</ul>
+
+
+	<ul>
+	<li>The less confusing notation of <pre>def some_object.a_singleton_method
+  do_stuff
+end</pre> is now used instead of the <pre>class &lt;&lt; some_object
+  def a_singleton_method
+    do_stuff
+  end
+end</pre> notation.
+	<ul>
+	<li>The tutorial and examples have been updated accordingly.</li>
+	</ul></li>
+	</ul>
+
+
+	<ul>
+	<li>The pipelined <span class="caps">ALU</span> example now has an updated <code>IntegerGenerator</code> class.</li>
+	</ul>
+
+
 	<h1>Version 10.0.0 (2006-11-05)</h1>
 
 

data/lib/ruby-vpi.rb

@@ -18,10 +18,21 @@
   Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
 =end
 
-# Provides configuration information of the Ruby-VPI project.
 module RubyVpi
-  # Initializes the current bench using the given parameters.
-  def RubyVpi.init_bench aTestPrefix, aDesignClassId
+  # Initializes the current bench by loading:
+  # 1. the design.rb file
+  # 2. the proto.rb file (if prototyping is enabled)
+  # 3. the spec.rb file
+  #
+  # aDesignId:: The name of the Ruby interface to the design under test.
+  # aSpecFormat:: The format of the specification.
+  def RubyVpi.init_bench aDesignId, aSpecFormat
+    if caller.find {|s| s =~ /^(.*?)_bench.rb:/}
+      testName = $1
+    else
+      raise 'Unable to determine name of test.'
+    end
+
     # set up the VPI utility layer
       require 'ruby-vpi/vpi'
 
@@ -29,8 +40,18 @@ module RubyVpi
         include Vpi
       end
 
-      # service the $ruby_init() callback
-        relay_verilog
+    # set up the specification library
+      case aSpecFormat
+        when :xUnit
+          require 'test/unit'
+
+        when :rSpec
+          ARGV.concat %w[-f s]
+          require 'ruby-vpi/rspec'
+      end
+
+    # service the $ruby_init() task
+      relay_verilog
 
     # set up code coverage analysis
       unless (ENV['COVERAGE'] || '').empty?
@@ -39,22 +60,22 @@ module RubyVpi
         RubyVpi.with_coverage_analysis do |a|
           a.dump_coverage_info [
             Rcov::TextReport.new,
-            Rcov::HTMLCoverage.new(:destdir => "#{aTestPrefix}_coverage")
+            Rcov::HTMLCoverage.new(:destdir => "#{testName}_coverage")
           ]
         end
       end
 
     # load the design under test
-      unless design = vpi_handle_by_name("#{aTestPrefix}_bench", nil)
-        raise "Verilog bench for test #{aTestPrefix.inspect} is inaccessible."
+      unless design = vpi_handle_by_name("#{testName}_bench", nil)
+        raise "Verilog bench for test #{testName.inspect} is inaccessible."
       end
 
-      Kernel.const_set(aDesignClassId, design)
-      require "#{aTestPrefix}_design.rb"
+      Kernel.const_set(aDesignId, design)
+      require "#{testName}_design.rb"
 
     # load the design's prototype
       unless (ENV['PROTOTYPE'] || '').empty?
-        require "#{aTestPrefix}_proto.rb"
+        require "#{testName}_proto.rb"
 
         Vpi.class_eval do
           define_method :relay_verilog do
@@ -62,12 +83,14 @@ module RubyVpi
           end
         end
 
-        puts "#{Config::PROJECT_NAME}: prototype has been enabled for test #{aTestPrefix.inspect}"
+        puts "#{Config::PROJECT_NAME}: prototype has been enabled for test #{testName.inspect}"
       end
 
-    require "#{aTestPrefix}_spec.rb"
+    # load the design's specification
+      require "#{testName}_spec.rb"
   end
 
+  # Provides information about the Ruby-VPI project's configuration.
   module Config
     PROJECT_ID = 'ruby-vpi'
     PROJECT_NAME = 'Ruby-VPI'
@@ -76,6 +99,8 @@ module RubyVpi
     PROJECT_DETAIL = "#{PROJECT_NAME} is a #{PROJECT_SUMMARY}. It lets you create complex Verilog test benches easily and wholly in Ruby."
 
     Simulator = Struct.new(:id, :name, :compiler_args, :linker_args)
+
+    # List of supported Verilog simulators.
     SIMULATORS = [
       Simulator.new(:cver, 'GPL Cver', '-DPRAGMATIC_CVER', ''),
       Simulator.new(:ivl, 'Icarus Verilog', '-DICARUS_VERILOG', ''),

data/samp/counter/counter_rspec_bench.rb

@@ -1,9 +1,3 @@
 # This file is the Ruby side of the bench.
 
-require 'ruby-vpi'
-require 'ruby-vpi/rspec'
-
-RubyVpi.init_bench 'counter_rspec', :Counter
-
-# service the $ruby_relay callback
-  # The rSpec library will take control henceforth.
+RubyVpi.init_bench :Counter, :rSpec

data/samp/counter/counter_rspec_bench.v

@@ -12,7 +12,7 @@ module counter_rspec_bench;
   // connect to the Ruby side of this bench
     initial begin
       clock = 0;
-      $ruby_init("ruby", "-w", "-rubygems", "counter_rspec_bench.rb", "-f", "s");
+      $ruby_init("ruby", "-w", "-rubygems", "-rruby-vpi", "counter_rspec_bench.rb");
     end
 
     always begin

data/samp/counter/counter_rspec_design.rb

@@ -1,8 +1,8 @@
 # This is a Ruby interface to the design under test.
-class << Counter
-  def reset!
-    reset.intVal = 1
-    relay_verilog
-    reset.intVal = 0
-  end
+
+# This method resets the design under test.
+def Counter.reset!
+  reset.intVal = 1
+  relay_verilog
+  reset.intVal = 0
 end

data/samp/counter/counter_rspec_proto.rb

@@ -1,12 +1,11 @@
 # This is a prototype of the design under test.
-class << Counter
-  # When prototyping is enabled, this method is invoked
-  # instead of Vpi::relay_verilog to simulate the design.
-  def simulate!
-    if reset.intVal == 1
-      count.intVal = 0
-    else
-      count.intVal += 1
-    end
+
+# When prototyping is enabled, relay_verilog invokes this method
+# instead of transferring control to the Verilog simulator.
+def Counter.simulate!
+  if reset.intVal == 1
+    count.intVal = 0
+  else
+    count.intVal += 1
   end
 end

data/samp/counter/counter_xunit_bench.rb

@@ -1,9 +1,3 @@
 # This file is the Ruby side of the bench.
 
-require 'ruby-vpi'
-require 'test/unit'
-
-RubyVpi.init_bench 'counter_xunit', :Counter
-
-# service the $ruby_relay callback
-  # The xUnit library will take control henceforth.
+RubyVpi.init_bench :Counter, :xUnit

data/samp/counter/counter_xunit_bench.v

@@ -12,7 +12,7 @@ module counter_xunit_bench;
   // connect to the Ruby side of this bench
     initial begin
       clock = 0;
-      $ruby_init("ruby", "-w", "-rubygems", "counter_xunit_bench.rb");
+      $ruby_init("ruby", "-w", "-rubygems", "-rruby-vpi", "counter_xunit_bench.rb");
     end
 
     always begin

data/samp/counter/counter_xunit_design.rb

@@ -1,8 +1,8 @@
 # This is a Ruby interface to the design under test.
-class << Counter
-  def reset!
-    reset.intVal = 1
-    relay_verilog
-    reset.intVal = 0
-  end
+
+# This method resets the design under test.
+def Counter.reset!
+  reset.intVal = 1
+  relay_verilog
+  reset.intVal = 0
 end

data/samp/counter/counter_xunit_proto.rb

@@ -1,12 +1,11 @@
 # This is a prototype of the design under test.
-class << Counter
-  # When prototyping is enabled, this method is invoked
-  # instead of Vpi::relay_verilog to simulate the design.
-  def simulate!
-    if reset.intVal == 1
-      count.intVal = 0
-    else
-      count.intVal += 1
-    end
+
+# When prototyping is enabled, relay_verilog invokes this method
+# instead of transferring control to the Verilog simulator.
+def Counter.simulate!
+  if reset.intVal == 1
+    count.intVal = 0
+  else
+    count.intVal += 1
   end
 end

data/samp/pipelined_alu/hw5_unit_test_bench.rb

@@ -1,9 +1,3 @@
 # This file is the Ruby side of the bench.
 
-require 'ruby-vpi'
-require 'test/unit'
-
-RubyVpi.init_bench 'hw5_unit_test', :Hw5_unit
-
-# service the $ruby_relay callback
-  # The xUnit library will take control henceforth.
+RubyVpi.init_bench :Hw5_unit, :xUnit

data/samp/pipelined_alu/hw5_unit_test_bench.v

@@ -17,7 +17,7 @@ module hw5_unit_test_bench;
   // connect to the Ruby side of this bench
     initial begin
       clk = 0;
-      $ruby_init("ruby", "-w", "-rubygems", "hw5_unit_test_bench.rb");
+      $ruby_init("ruby", "-w", "-rubygems", "-rruby-vpi", "hw5_unit_test_bench.rb");
     end
 
     always begin

data/samp/pipelined_alu/hw5_unit_test_design.rb

@@ -11,23 +11,22 @@ OPERATIONS = (OP_NOP..OP_MULT).to_a
 # Number of cycles needed to reset this design.
 RESET_DELAY = 5
 
-class << Hw5_unit
-  def reset!
-    reset.hexStrVal = 'x'
-    in_databits.hexStrVal = 'x'
-    a.hexStrVal = 'x'
-    b.hexStrVal = 'x'
-    in_op.hexStrVal = 'x'
+# This method resets the design under test.
+def Hw5_unit.reset!
+  reset.hexStrVal = 'x'
+  in_databits.hexStrVal = 'x'
+  a.hexStrVal = 'x'
+  b.hexStrVal = 'x'
+  in_op.hexStrVal = 'x'
 
 
-    reset.intVal = 1
+  reset.intVal = 1
 
-    RESET_DELAY.times do
-      relay_verilog
-    end
-
-    reset.intVal = 0
+  RESET_DELAY.times do
+    relay_verilog
   end
+
+  reset.intVal = 0
 end
 
 

data/samp/pipelined_alu/hw5_unit_test_proto.rb

@@ -1,17 +1,7 @@
 # This is a prototype of the design under test.
-class << Hw5_unit
-  # When prototyping is enabled, this method is invoked
-  # instead of Vpi::relay_verilog to simulate the design.
-  def simulate!
-    raise NotImplementedError, "Prototype is not yet implemented."
 
-    # discard old outputs
-      res.hexStrVal = 'x'
-      out_databits.hexStrVal = 'x'
-      out_op.hexStrVal = 'x'
-
-    # process new inputs
-
-    # produce new outputs
-  end
+# When prototyping is enabled, relay_verilog invokes this method
+# instead of transferring control to the Verilog simulator.
+def Hw5_unit.simulate!
+  raise NotImplementedError, "Prototype is not yet implemented."
 end

data/samp/pipelined_alu/hw5_unit_test_spec.rb

@@ -20,7 +20,7 @@
 
 # This file is a behavioral specification for the design under test.
 
-require 'InputGenerator'
+require 'int_gen'
 
 class Hw5_unit_test_spec < Test::Unit::TestCase
   # Number of input sequences to test.
@@ -34,7 +34,7 @@ class Hw5_unit_test_spec < Test::Unit::TestCase
 
   def setup
     Hw5_unit.reset!
-    @inputGen = InputGenerator.new(WIDTH)
+    @intGen = IntegerGenerator.new(WIDTH)
   end
 
   def test_pipeline
@@ -47,8 +47,8 @@ class Hw5_unit_test_spec < Test::Unit::TestCase
           op = Operation.new(
             OPERATIONS[rand(OPERATIONS.size)],
             numIssued % OPERATION_TAG_LIMIT,
-            @inputGen.gen,
-            @inputGen.gen
+            @intGen.random,
+            @intGen.random
           )
 
           Hw5_unit.a.intVal = op.arg1

data/samp/pipelined_alu/{InputGenerator.rb → int_gen.rb}

@@ -18,52 +18,43 @@
   Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
 =end
 
-# Generates random input sequences of configurable length.
-class InputGenerator
+# Generates random integers of configurable length.
+class IntegerGenerator
   # the first 1000 prime numbers, gotten from <http://en.wikipedia.org/wiki/List_of_prime_numbers#The_first_1000_prime_numbers>
-  PrimeNums = [
+  PRIMES = [
     2, 3, 5, 7, 11, 13, 17, 19, 23, 29, 31, 37, 41, 43, 47, 53, 59, 61, 67, 71, 73, 79, 83, 89, 97, 101, 103, 107, 109, 113, 127, 131, 137, 139, 149, 151, 157, 163, 167, 173, 179, 181, 191, 193, 197, 199, 211, 223, 227, 229, 233, 239, 241, 251, 257, 263, 269, 271, 277, 281, 283, 293, 307, 311, 313, 317, 331, 337, 347, 349, 353, 359, 367, 373, 379, 383, 389, 397, 401, 409, 419, 421, 431, 433, 439, 443, 449, 457, 461, 463, 467, 479, 487, 491, 499, 503, 509, 521, 523, 541, 547, 557, 563, 569, 571, 577, 587, 593, 599, 601, 607, 613, 617, 619, 631, 641, 643, 647, 653, 659, 661, 673, 677, 683, 691, 701, 709, 719, 727, 733, 739, 743, 751, 757, 761, 769, 773, 787, 797, 809, 811, 821, 823, 827, 829, 839, 853, 857, 859, 863, 877, 881, 883, 887, 907, 911, 919, 929, 937, 941, 947, 953, 967, 971, 977, 983, 991, 997, 1009, 1013, 1019, 1021, 1031, 1033, 1039, 1049, 1051, 1061, 1063, 1069, 1087, 1091, 1093, 1097, 1103, 1109, 1117, 1123, 1129, 1151, 1153, 1163, 1171, 1181, 1187, 1193, 1201, 1213, 1217, 1223, 1229, 1231, 1237, 1249, 1259, 1277, 1279, 1283, 1289, 1291, 1297, 1301, 1303, 1307, 1319, 1321, 1327, 1361, 1367, 1373, 1381, 1399, 1409, 1423, 1427, 1429, 1433, 1439, 1447, 1451, 1453, 1459, 1471, 1481, 1483, 1487, 1489, 1493, 1499, 1511, 1523, 1531, 1543, 1549, 1553, 1559, 1567, 1571, 1579, 1583, 1597, 1601, 1607, 1609, 1613, 1619, 1621, 1627, 1637, 1657, 1663, 1667, 1669, 1693, 1697, 1699, 1709, 1721, 1723, 1733, 1741, 1747, 1753, 1759, 1777, 1783, 1787, 1789, 1801, 1811, 1823, 1831, 1847, 1861, 1867, 1871, 1873, 1877, 1879, 1889, 1901, 1907, 1913, 1931, 1933, 1949, 1951, 1973, 1979, 1987, 1993, 1997, 1999, 2003, 2011, 2017, 2027, 2029, 2039, 2053, 2063, 2069, 2081, 2083, 2087, 2089, 2099, 2111, 2113, 2129, 2131, 2137, 2141, 2143, 2153, 2161, 2179, 2203, 2207, 2213, 2221, 2237, 2239, 2243, 2251, 2267, 2269, 2273, 2281, 2287, 2293, 2297, 2309, 2311, 2333, 2339, 2341, 2347, 2351, 2357, 2371, 2377, 2381, 2383, 2389, 2393, 2399, 2411, 2417, 2423, 2437, 2441, 2447, 2459, 2467, 2473, 2477, 2503, 2521, 2531, 2539, 2543, 2549, 2551, 2557, 2579, 2591, 2593, 2609, 2617, 2621, 2633, 2647, 2657, 2659, 2663, 2671, 2677, 2683, 2687, 2689, 2693, 2699, 2707, 2711, 2713, 2719, 2729, 2731, 2741, 2749, 2753, 2767, 2777, 2789, 2791, 2797, 2801, 2803, 2819, 2833, 2837, 2843, 2851, 2857, 2861, 2879, 2887, 2897, 2903, 2909, 2917, 2927, 2939, 2953, 2957, 2963, 2969, 2971, 2999, 3001, 3011, 3019, 3023, 3037, 3041, 3049, 3061, 3067, 3079, 3083, 3089, 3109, 3119, 3121, 3137, 3163, 3167, 3169, 3181, 3187, 3191, 3203, 3209, 3217, 3221, 3229, 3251, 3253, 3257, 3259, 3271, 3299, 3301, 3307, 3313, 3319, 3323, 3329, 3331, 3343, 3347, 3359, 3361, 3371, 3373, 3389, 3391, 3407, 3413, 3433, 3449, 3457, 3461, 3463, 3467, 3469, 3491, 3499, 3511, 3517, 3527, 3529, 3533, 3539, 3541, 3547, 3557, 3559, 3571, 3581, 3583, 3593, 3607, 3613, 3617, 3623, 3631, 3637, 3643, 3659, 3671, 3673, 3677, 3691, 3697, 3701, 3709, 3719, 3727, 3733, 3739, 3761, 3767, 3769, 3779, 3793, 3797, 3803, 3821, 3823, 3833, 3847, 3851, 3853, 3863, 3877, 3881, 3889, 3907, 3911, 3917, 3919, 3923, 3929, 3931, 3943, 3947, 3967, 3989, 4001, 4003, 4007, 4013, 4019, 4021, 4027, 4049, 4051, 4057, 4073, 4079, 4091, 4093, 4099, 4111, 4127, 4129, 4133, 4139, 4153, 4157, 4159, 4177, 4201, 4211, 4217, 4219, 4229, 4231, 4241, 4243, 4253, 4259, 4261, 4271, 4273, 4283, 4289, 4297, 4327, 4337, 4339, 4349, 4357, 4363, 4373, 4391, 4397, 4409, 4421, 4423, 4441, 4447, 4451, 4457, 4463, 4481, 4483, 4493, 4507, 4513, 4517, 4519, 4523, 4547, 4549, 4561, 4567, 4583, 4591, 4597, 4603, 4621, 4637, 4639, 4643, 4649, 4651, 4657, 4663, 4673, 4679, 4691, 4703, 4721, 4723, 4729, 4733, 4751, 4759, 4783, 4787, 4789, 4793, 4799, 4801, 4813, 4817, 4831, 4861, 4871, 4877, 4889, 4903, 4909, 4919, 4931, 4933, 4937, 4943, 4951, 4957, 4967, 4969, 4973, 4987, 4993, 4999, 5003, 5009, 5011, 5021, 5023, 5039, 5051, 5059, 5077, 5081, 5087, 5099, 5101, 5107, 5113, 5119, 5147, 5153, 5167, 5171, 5179, 5189, 5197, 5209, 5227, 5231, 5233, 5237, 5261, 5273, 5279, 5281, 5297, 5303, 5309, 5323, 5333, 5347, 5351, 5381, 5387, 5393, 5399, 5407, 5413, 5417, 5419, 5431, 5437, 5441, 5443, 5449, 5471, 5477, 5479, 5483, 5501, 5503, 5507, 5519, 5521, 5527, 5531, 5557, 5563, 5569, 5573, 5581, 5591, 5623, 5639, 5641, 5647, 5651, 5653, 5657, 5659, 5669, 5683, 5689, 5693, 5701, 5711, 5717, 5737, 5741, 5743, 5749, 5779, 5783, 5791, 5801, 5807, 5813, 5821, 5827, 5839, 5843, 5849, 5851, 5857, 5861, 5867, 5869, 5879, 5881, 5897, 5903, 5923, 5927, 5939, 5953, 5981, 5987, 6007, 6011, 6029, 6037, 6043, 6047, 6053, 6067, 6073, 6079, 6089, 6091, 6101, 6113, 6121, 6131, 6133, 6143, 6151, 6163, 6173, 6197, 6199, 6203, 6211, 6217, 6221, 6229, 6247, 6257, 6263, 6269, 6271, 6277, 6287, 6299, 6301, 6311, 6317, 6323, 6329, 6337, 6343, 6353, 6359, 6361, 6367, 6373, 6379, 6389, 6397, 6421, 6427, 6449, 6451, 6469, 6473, 6481, 6491, 6521, 6529, 6547, 6551, 6553, 6563, 6569, 6571, 6577, 6581, 6599, 6607, 6619, 6637, 6653, 6659, 6661, 6673, 6679, 6689, 6691, 6701, 6703, 6709, 6719, 6733, 6737, 6761, 6763, 6779, 6781, 6791, 6793, 6803, 6823, 6827, 6829, 6833, 6841, 6857, 6863, 6869, 6871, 6883, 6899, 6907, 6911, 6917, 6947, 6949, 6959, 6961, 6967, 6971, 6977, 6983, 6991, 6997, 7001, 7013, 7019, 7027, 7039, 7043, 7057, 7069, 7079, 7103, 7109, 7121, 7127, 7129, 7151, 7159, 7177, 7187, 7193, 7207, 7211, 7213, 7219, 7229, 7237, 7243, 7247, 7253, 7283, 7297, 7307, 7309, 7321, 7331, 7333, 7349, 7351, 7369, 7393, 7411, 7417, 7433, 7451, 7457, 7459, 7477, 7481, 7487, 7489, 7499, 7507, 7517, 7523, 7529, 7537, 7541, 7547, 7549, 7559, 7561, 7573, 7577, 7583, 7589, 7591, 7603, 7607, 7621, 7639, 7643, 7649, 7669, 7673, 7681, 7687, 7691, 7699, 7703, 7717, 7723, 7727, 7741, 7753, 7757, 7759, 7789, 7793, 7817, 7823, 7829, 7841, 7853, 7867, 7873, 7877, 7879, 7883, 7901, 7907, 7919
   ]
 
-  # Constructs a new input sequence generator.
-  # bits:: Number of bits that can be used to represent a generated input sequence
-  def initialize(bits)
-    self.bits = bits
-  end
+  attr_reader :bits
 
-  # returns the number of bits that can be used to represent a generated input sequence
-  def bits
-    @inputBits
-  end
+  # Generates random integers representable by the given number of bits.
+  def initialize aBits
+    @bits = aBits
+    @limit = 2 ** @bits
 
-  # sets the number of bits that can be used to represent a generated input sequence
-  def bits=(num)
-    @inputBits = num
-    @inputLimit = 2 ** @inputBits
+    PRIMES.reject! {|i| i > @limit}
   end
 
-  # generates a random input sequence
-  def gen
+  # returns a random input sequence
+  def random
     choices = [
       0,
       1,
-      gen_prime,
-      gen_power_of_two,
-      rand(@inputLimit),
+      prime,
+      power_of_two,
+      rand(@limit),
     ]
 
     choices[rand(choices.length)]
   end
 
-  # generates a random prime number
-  def gen_prime
-    prime = PrimeNums[rand(PrimeNums.length)]
-    prime < @inputLimit ? prime : 2
+  # returns a random prime integer
+  def prime
+    PRIMES[rand(PRIMES.length)]
   end
 
-  # generates a random power-of-two number
-  def gen_power_of_two
-    power = rand(@inputBits) + 1
-    (2 ** power) - 1
+  # returns a random power-of-two integer
+  def power_of_two
+    2 ** rand(@bits)
   end
 end

metadata

@@ -3,7 +3,7 @@ rubygems_version: 0.9.0
 specification_version: 1
 name: ruby-vpi
 version: !ruby/object:Gem::Version 
-  version: 10.0.0
+  version: 11.0.0
 date: 2006-11-05 00:00:00 -08:00
 summary: Ruby interface to Verilog VPI.
 require_paths: 
@@ -188,7 +188,6 @@ files:
 - samp/counter
 - samp/pipelined_alu/TestHw5UnitModel.rb
 - samp/pipelined_alu/Hw5UnitModel.rb
-- samp/pipelined_alu/InputGenerator.rb
 - samp/pipelined_alu/README
 - samp/pipelined_alu/hw5_unit.v
 - samp/pipelined_alu/Rakefile
@@ -198,6 +197,7 @@ files:
 - samp/pipelined_alu/hw5_unit_test_bench.rb
 - samp/pipelined_alu/hw5_unit_test_design.rb
 - samp/pipelined_alu/hw5_unit_test_proto.rb
+- samp/pipelined_alu/int_gen.rb
 - samp/counter/counter.v
 - samp/counter/Rakefile
 - samp/counter/counter_xunit_bench.v
@@ -207,10 +207,10 @@ files:
 - samp/counter/counter_xunit_bench.rb
 - samp/counter/counter_xunit_runner.rake
 - samp/counter/counter_xunit_spec.rb
-- samp/counter/counter_rspec_bench.rb
 - samp/counter/counter_xunit_proto.rb
 - samp/counter/counter_rspec_design.rb
 - samp/counter/counter_rspec_bench.v
+- samp/counter/counter_rspec_bench.rb
 - samp/counter/counter_rspec_runner.rake
 test_files: []