rggen 0.6.0 → 0.6.1

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Files changed (26) hide show
  1. checksums.yaml +4 -4
  2. data/lib/rggen/builtins.rb +1 -0
  3. data/lib/rggen/builtins/bit_field/rtl_top.rb +11 -0
  4. data/lib/rggen/builtins/bit_field/type.rb +6 -6
  5. data/lib/rggen/builtins/bit_field/types/ro.erb +2 -2
  6. data/lib/rggen/builtins/bit_field/types/ro.rb +2 -2
  7. data/lib/rggen/builtins/bit_field/types/rw.erb +2 -2
  8. data/lib/rggen/builtins/bit_field/types/rw.rb +2 -6
  9. data/lib/rggen/builtins/bit_field/types/rwl_rwe.erb +2 -2
  10. data/lib/rggen/builtins/bit_field/types/rwl_rwe.rb +1 -1
  11. data/lib/rggen/builtins/bit_field/types/w0c_w1c.erb +2 -2
  12. data/lib/rggen/builtins/bit_field/types/w0c_w1c.rb +1 -3
  13. data/lib/rggen/builtins/bit_field/types/w0s_w1s.erb +2 -2
  14. data/lib/rggen/builtins/bit_field/types/w0s_w1s.rb +1 -3
  15. data/lib/rggen/builtins/register/types/default.erb +1 -1
  16. data/lib/rggen/builtins/register/types/external.erb +1 -1
  17. data/lib/rggen/builtins/register/types/indirect.erb +1 -1
  18. data/lib/rggen/core_components/verilog_utility/local_scope.rb +9 -2
  19. data/lib/rggen/version.rb +1 -1
  20. data/sample/sample_0.sv +222 -190
  21. data/sample/sample_0_ral_pkg.sv +16 -16
  22. data/sample/sample_1.sv +62 -52
  23. data/sample/sample_1_ral_pkg.sv +5 -5
  24. data/sample/sample_setup.rb +1 -0
  25. data/setup/default.rb +1 -0
  26. metadata +3 -2
checksums.yaml CHANGED
@@ -1,7 +1,7 @@
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  SHA1:
3
- metadata.gz: ad6fc3632abba4953ce0e0fe205a009db33e7b8d
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- data.tar.gz: '068dffc83856248d9042c658766e3eaa3423cb1e'
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+ metadata.gz: d33b1f653bd2968858ddf63a333f4f14b6886556
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+ data.tar.gz: ef5da01aa0b3ec7a1c5097e1ffdcf14e1c1848ab
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5
  SHA512:
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- metadata.gz: 71fcd5f1de2247416ceecf9adfe5a32f0e1b8e9c130cc1b7ec562cec34288594eafd1d788edede1775e7dfbf2f939e6c7cc89cd2d048981ecfebeb030c17dcca
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- data.tar.gz: 7e9124eac17384c66e967beefa5da946e466e9798fb01d07270c6175c565d1af7e2fd28f2ff644c212a1f371f9141f9b330a00b7ae07b5ac3ba6e01de6811e4c
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+ metadata.gz: 16848790ca403c61edc82245bc55b4d6c3edd6ff2638bb08305d5c8df4789d4bf5c71fd9ed06e469023be7fb6d107ed66c53f8348c41ec13ed67328c51d91efd
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+ data.tar.gz: 6b89fa0fe23b35b41052335784b0b9de65d1b4d890e3b906707c84ce35ff2b227496613b611de011de991ef7a834946d35f96bef13f1517ac3af302026e00a4a
data/lib/rggen/builtins.rb CHANGED
@@ -12,6 +12,7 @@ require_relative 'builtins/bit_field/field_model'
12
12
  require_relative 'builtins/bit_field/initial_value'
13
13
  require_relative 'builtins/bit_field/name'
14
14
  require_relative 'builtins/bit_field/reference'
15
+ require_relative 'builtins/bit_field/rtl_top'
15
16
  require_relative 'builtins/bit_field/type'
16
17
  require_relative 'builtins/bit_field/types/rw'
17
18
  require_relative 'builtins/bit_field/types/rwl_rwe'
data/lib/rggen/builtins/bit_field/rtl_top.rb ADDED
@@ -0,0 +1,11 @@
1
+ simple_item :bit_field, :rtl_top do
2
+ rtl do
3
+ generate_code :register do
4
+ local_scope "g_#{bit_field.name}" do |s|
5
+ s.signals bit_field.signal_declarations(:bit_field)
6
+ s.without_generate_keyword
7
+ s.body { |c| bit_field.generate_code(:bit_field, :top_down, c) }
8
+ end
9
+ end
10
+ end
11
+ end
data/lib/rggen/builtins/bit_field/type.rb CHANGED
@@ -169,7 +169,7 @@ list_item :bit_field, :type do
169
169
  export :value
170
170
 
171
171
  delegate [
172
- :name, :width, :msb, :lsb, :reserved?
172
+ :name, :width, :msb, :lsb, :type, :reserved?
173
173
  ] => :bit_field
174
174
  delegate [
175
175
  :dimensions, :index, :local_index, :loop_variables
@@ -178,15 +178,15 @@ list_item :bit_field, :type do
178
178
  available? { !bit_field.reserved? }
179
179
 
180
180
  build do
181
- interface :register, :bit_field_if,
181
+ interface :bit_field, :bit_field_sub_if,
182
182
  type: :rggen_bit_field_if,
183
- name: "#{name}_if",
183
+ name: :bit_field_sub_if,
184
184
  parameters: [width]
185
185
  end
186
186
 
187
- generate_pre_code :register do |c|
187
+ generate_pre_code :bit_field do |c|
188
188
  c << subroutine_call(:'`rggen_connect_bit_field_if', [
189
- register.bit_field_if, bit_field_if, msb, lsb
189
+ register.bit_field_if, bit_field_sub_if, msb, lsb
190
190
  ]) << nl
191
191
  end
192
192
 
@@ -232,7 +232,7 @@ list_item :bit_field, :type do
232
232
  end
233
233
 
234
234
  def hdl_path
235
- "u_#{bit_field.name}.value"
235
+ "g_#{bit_field.name}.u_bit_field.value"
236
236
  end
237
237
  end
238
238
 
data/lib/rggen/builtins/bit_field/types/ro.erb CHANGED
@@ -1,6 +1,6 @@
1
1
  rggen_bit_field_ro #(
2
2
  .WIDTH (<%= width %>)
3
- ) u_<%= bit_field.name %> (
4
- .bit_field_if (<%= bit_field_if %>),
3
+ ) u_bit_field (
4
+ .bit_field_if (<%= bit_field_sub_if %>),
5
5
  .i_value (<%= value_in[loop_variables] %>)
6
6
  );
data/lib/rggen/builtins/bit_field/types/ro.rb CHANGED
@@ -11,10 +11,10 @@ list_item :bit_field, :type, :ro do
11
11
  dimensions: dimensions
12
12
  end
13
13
 
14
- generate_code_from_template :register
14
+ generate_code_from_template :bit_field
15
15
  end
16
16
 
17
17
  ral do
18
- hdl_path { "u_#{bit_field.name}.i_value" }
18
+ hdl_path { "g_#{bit_field.name}.u_bit_field.i_value" }
19
19
  end
20
20
  end
data/lib/rggen/builtins/bit_field/types/rw.erb CHANGED
@@ -1,9 +1,9 @@
1
1
  rggen_bit_field_rw #(
2
2
  .WIDTH (<%= width %>),
3
3
  .INITIAL_VALUE (<%= initial_value %>)
4
- ) u_<%= bit_field.name %> (
4
+ ) u_bit_field (
5
5
  .clk (<%= register_block.clock %>),
6
6
  .rst_n (<%= register_block.reset %>),
7
- .bit_field_if (<%= bit_field_if %>),
7
+ .bit_field_if (<%= bit_field_sub_if %>),
8
8
  .o_value (<%= value_out[loop_variables] %>)
9
9
  );
data/lib/rggen/builtins/bit_field/types/rw.rb CHANGED
@@ -7,16 +7,12 @@ list_item :bit_field, :type, :rw do
7
7
  rtl do
8
8
  build do
9
9
  output :register_block, :value_out,
10
- name: port_name,
10
+ name: "o_#{bit_field.name}",
11
11
  width: width,
12
12
  dimensions: dimensions
13
13
  end
14
14
 
15
- generate_code_from_template :register
16
-
17
- def port_name
18
- "o_#{bit_field.name}"
19
- end
15
+ generate_code_from_template :bit_field
20
16
 
21
17
  def initial_value
22
18
  hex(bit_field.initial_value, bit_field.width)
data/lib/rggen/builtins/bit_field/types/rwl_rwe.erb CHANGED
@@ -2,10 +2,10 @@ rggen_bit_field_rwl_rwe #(
2
2
  .MODE (rggen_rtl_pkg::<%= mode %>),
3
3
  .WIDTH (<%= width %>),
4
4
  .INITIAL_VALUE (<%= initial_value %>)
5
- ) u_<%= bit_field.name %> (
5
+ ) u_bit_field (
6
6
  .clk (<%= register_block.clock %>),
7
7
  .rst_n (<%= register_block.reset %>),
8
8
  .i_lock_or_enable (<%= lock_or_enable %>),
9
- .bit_field_if (<%= bit_field_if %>),
9
+ .bit_field_if (<%= bit_field_sub_if %>),
10
10
  .o_value (<%= value_out[loop_variables] %>)
11
11
  );
data/lib/rggen/builtins/bit_field/types/rwl_rwe.rb CHANGED
@@ -13,7 +13,7 @@ list_item :bit_field, :type, [:rwl, :rwe] do
13
13
  dimensions: dimensions
14
14
  end
15
15
 
16
- generate_code_from_template :register
16
+ generate_code_from_template :bit_field
17
17
 
18
18
  def mode
19
19
  {
data/lib/rggen/builtins/bit_field/types/w0c_w1c.erb CHANGED
@@ -3,10 +3,10 @@ rggen_bit_field_w01s_w01c #(
3
3
  .SET_CLEAR_VALUE (<%= clear_value %>),
4
4
  .WIDTH (<%= width %>),
5
5
  .INITIAL_VALUE (<%= initial_value %>)
6
- ) u_<%= name%> (
6
+ ) u_bit_field (
7
7
  .clk (<%= register_block.clock %>),
8
8
  .rst_n (<%= register_block.reset %>),
9
9
  .i_set_or_clear (<%= set[loop_variables] %>),
10
- .bit_field_if (<%= bit_field_if %>),
10
+ .bit_field_if (<%= bit_field_sub_if %>),
11
11
  .o_value ()
12
12
  );
data/lib/rggen/builtins/bit_field/types/w0c_w1c.rb CHANGED
@@ -7,8 +7,6 @@ list_item :bit_field, :type, [:w0c, :w1c] do
7
7
  end
8
8
 
9
9
  rtl do
10
- delegate [:name, :type] => :bit_field
11
-
12
10
  build do
13
11
  input :register_block, :set,
14
12
  name: "i_#{name}_set",
@@ -16,7 +14,7 @@ list_item :bit_field, :type, [:w0c, :w1c] do
16
14
  dimensions: dimensions
17
15
  end
18
16
 
19
- generate_code_from_template :register
17
+ generate_code_from_template :bit_field
20
18
 
21
19
  def initial_value
22
20
  hex(bit_field.initial_value, width)
data/lib/rggen/builtins/bit_field/types/w0s_w1s.erb CHANGED
@@ -3,10 +3,10 @@ rggen_bit_field_w01s_w01c #(
3
3
  .SET_CLEAR_VALUE (<%= set_value %>),
4
4
  .WIDTH (<%= width %>),
5
5
  .INITIAL_VALUE (<%= initial_value %>)
6
- ) u_<%= name %> (
6
+ ) u_bit_field (
7
7
  .clk (<%= register_block.clock %>),
8
8
  .rst_n (<%= register_block.reset %>),
9
9
  .i_set_or_clear (<%= clear[loop_variables] %>),
10
- .bit_field_if (<%= bit_field_if %>),
10
+ .bit_field_if (<%= bit_field_sub_if %>),
11
11
  .o_value (<%= value_out[loop_variables] %>)
12
12
  );
data/lib/rggen/builtins/bit_field/types/w0s_w1s.rb CHANGED
@@ -5,8 +5,6 @@ list_item :bit_field, :type, [:w0s, :w1s] do
5
5
  end
6
6
 
7
7
  rtl do
8
- delegate [:name, :type] => :bit_field
9
-
10
8
  build do
11
9
  output :register_block, :value_out,
12
10
  name: "o_#{name}",
@@ -18,7 +16,7 @@ list_item :bit_field, :type, [:w0s, :w1s] do
18
16
  dimensions: dimensions
19
17
  end
20
18
 
21
- generate_code_from_template :register
19
+ generate_code_from_template :bit_field
22
20
 
23
21
  def initial_value
24
22
  hex(bit_field.initial_value, width)
data/lib/rggen/builtins/register/types/default.erb CHANGED
@@ -4,7 +4,7 @@ rggen_default_register #(
4
4
  .END_ADDRESS (<%= end_address %>),
5
5
  .DATA_WIDTH (<%= data_width %>),
6
6
  .VALID_BITS (<%= valid_bits %>)
7
- ) u_<%= register.name %> (
7
+ ) u_register (
8
8
  .register_if (<%= register.register_if %>),
9
9
  .bit_field_if (<%= bit_field_if %>)
10
10
  );
data/lib/rggen/builtins/register/types/external.erb CHANGED
@@ -3,7 +3,7 @@ rggen_external_register #(
3
3
  .START_ADDRESS (<%= start_address %>),
4
4
  .END_ADDRESS (<%= end_address %>),
5
5
  .DATA_WIDTH (<%= configuration.data_width %>)
6
- ) u_<%= register.name %> (
6
+ ) u_register (
7
7
  .clk (<%= register_block.clock %>),
8
8
  .rst_n (<%= register_block.reset %>),
9
9
  .register_if (<%= register.register_if %>),
data/lib/rggen/builtins/register/types/indirect.erb CHANGED
@@ -6,7 +6,7 @@ rggen_indirect_register #(
6
6
  .INDEX_VALUE (<%= indirect_index_value %>),
7
7
  .DATA_WIDTH (<%= data_width %>),
8
8
  .VALID_BITS (<%= valid_bits %>)
9
- ) u_<%= register.name %> (
9
+ ) u_register (
10
10
  .register_if (<%= register.register_if %>),
11
11
  .bit_field_if (<%= bit_field_if %>),
12
12
  .i_index (<%= indirect_index %>)
data/lib/rggen/core_components/verilog_utility/local_scope.rb CHANGED
@@ -4,6 +4,10 @@ module RgGen
4
4
  attr_setter :signals
5
5
  attr_setter :loops
6
6
 
7
+ def without_generate_keyword
8
+ @without_generate_keyword = true
9
+ end
10
+
7
11
  def to_code
8
12
  bodies.unshift(signal_declarations) if signals?
9
13
  code_block do |c|
@@ -16,13 +20,16 @@ module RgGen
16
20
  private
17
21
 
18
22
  def header_code(code)
19
- code << :'generate if (1) begin : ' << @name << nl
23
+ code << :generate << space unless @without_generate_keyword
24
+ code << :'if (1) begin : ' << @name << nl
20
25
  loops? && generate_for_header(code)
21
26
  end
22
27
 
23
28
  def footer_code(code)
24
29
  loops? && generate_for_footer(code)
25
- code << :'end endgenerate' << nl
30
+ code << :end
31
+ code << space << :endgenerate unless @without_generate_keyword
32
+ code << nl
26
33
  end
27
34
 
28
35
  def loops?
data/lib/rggen/version.rb CHANGED
@@ -1,6 +1,6 @@
1
1
  module RgGen
2
2
  MAJOR = 0
3
3
  MINOR = 6
4
- TEENY = 0
4
+ TEENY = 1
5
5
  VERSION = "#{MAJOR}.#{MINOR}.#{TEENY}".freeze
6
6
  end
data/sample/sample_0.sv CHANGED
@@ -56,149 +56,165 @@ module sample_0 (
56
56
  );
57
57
  generate if (1) begin : g_register_0
58
58
  rggen_bit_field_if #(32) bit_field_if();
59
- rggen_bit_field_if #(16) bit_field_0_0_if();
60
- rggen_bit_field_if #(16) bit_field_0_1_if();
61
59
  rggen_default_register #(
62
60
  .ADDRESS_WIDTH (8),
63
61
  .START_ADDRESS (8'h00),
64
62
  .END_ADDRESS (8'h03),
65
63
  .DATA_WIDTH (32),
66
64
  .VALID_BITS (32'hffffffff)
67
- ) u_register_0 (
65
+ ) u_register (
68
66
  .register_if (register_if[0]),
69
67
  .bit_field_if (bit_field_if)
70
68
  );
71
- `rggen_connect_bit_field_if(bit_field_if, bit_field_0_0_if, 31, 16)
72
- rggen_bit_field_rw #(
73
- .WIDTH (16),
74
- .INITIAL_VALUE (16'h0000)
75
- ) u_bit_field_0_0 (
76
- .clk (clk),
77
- .rst_n (rst_n),
78
- .bit_field_if (bit_field_0_0_if),
79
- .o_value (o_bit_field_0_0)
80
- );
81
- `rggen_connect_bit_field_if(bit_field_if, bit_field_0_1_if, 15, 0)
82
- rggen_bit_field_rw #(
83
- .WIDTH (16),
84
- .INITIAL_VALUE (16'h0000)
85
- ) u_bit_field_0_1 (
86
- .clk (clk),
87
- .rst_n (rst_n),
88
- .bit_field_if (bit_field_0_1_if),
89
- .o_value (o_bit_field_0_1)
90
- );
69
+ if (1) begin : g_bit_field_0_0
70
+ rggen_bit_field_if #(16) bit_field_sub_if();
71
+ `rggen_connect_bit_field_if(bit_field_if, bit_field_sub_if, 31, 16)
72
+ rggen_bit_field_rw #(
73
+ .WIDTH (16),
74
+ .INITIAL_VALUE (16'h0000)
75
+ ) u_bit_field (
76
+ .clk (clk),
77
+ .rst_n (rst_n),
78
+ .bit_field_if (bit_field_sub_if),
79
+ .o_value (o_bit_field_0_0)
80
+ );
81
+ end
82
+ if (1) begin : g_bit_field_0_1
83
+ rggen_bit_field_if #(16) bit_field_sub_if();
84
+ `rggen_connect_bit_field_if(bit_field_if, bit_field_sub_if, 15, 0)
85
+ rggen_bit_field_rw #(
86
+ .WIDTH (16),
87
+ .INITIAL_VALUE (16'h0000)
88
+ ) u_bit_field (
89
+ .clk (clk),
90
+ .rst_n (rst_n),
91
+ .bit_field_if (bit_field_sub_if),
92
+ .o_value (o_bit_field_0_1)
93
+ );
94
+ end
91
95
  end endgenerate
92
96
  generate if (1) begin : g_register_1
93
97
  rggen_bit_field_if #(32) bit_field_if();
94
- rggen_bit_field_if #(32) bit_field_1_0_if();
95
98
  rggen_default_register #(
96
99
  .ADDRESS_WIDTH (8),
97
100
  .START_ADDRESS (8'h04),
98
101
  .END_ADDRESS (8'h07),
99
102
  .DATA_WIDTH (32),
100
103
  .VALID_BITS (32'hffffffff)
101
- ) u_register_1 (
104
+ ) u_register (
102
105
  .register_if (register_if[1]),
103
106
  .bit_field_if (bit_field_if)
104
107
  );
105
- `rggen_connect_bit_field_if(bit_field_if, bit_field_1_0_if, 31, 0)
106
- rggen_bit_field_rw #(
107
- .WIDTH (32),
108
- .INITIAL_VALUE (32'h00000000)
109
- ) u_bit_field_1_0 (
110
- .clk (clk),
111
- .rst_n (rst_n),
112
- .bit_field_if (bit_field_1_0_if),
113
- .o_value (o_bit_field_1_0)
114
- );
108
+ if (1) begin : g_bit_field_1_0
109
+ rggen_bit_field_if #(32) bit_field_sub_if();
110
+ `rggen_connect_bit_field_if(bit_field_if, bit_field_sub_if, 31, 0)
111
+ rggen_bit_field_rw #(
112
+ .WIDTH (32),
113
+ .INITIAL_VALUE (32'h00000000)
114
+ ) u_bit_field (
115
+ .clk (clk),
116
+ .rst_n (rst_n),
117
+ .bit_field_if (bit_field_sub_if),
118
+ .o_value (o_bit_field_1_0)
119
+ );
120
+ end
115
121
  end endgenerate
116
122
  generate if (1) begin : g_register_2
117
123
  rggen_bit_field_if #(32) bit_field_if();
118
- rggen_bit_field_if #(1) bit_field_2_0_if();
119
- rggen_bit_field_if #(1) bit_field_2_1_if();
120
124
  rggen_default_register #(
121
125
  .ADDRESS_WIDTH (8),
122
126
  .START_ADDRESS (8'h08),
123
127
  .END_ADDRESS (8'h0b),
124
128
  .DATA_WIDTH (32),
125
129
  .VALID_BITS (32'h00010001)
126
- ) u_register_2 (
130
+ ) u_register (
127
131
  .register_if (register_if[2]),
128
132
  .bit_field_if (bit_field_if)
129
133
  );
130
- `rggen_connect_bit_field_if(bit_field_if, bit_field_2_0_if, 16, 16)
131
- rggen_bit_field_ro #(
132
- .WIDTH (1)
133
- ) u_bit_field_2_0 (
134
- .bit_field_if (bit_field_2_0_if),
135
- .i_value (i_bit_field_2_0)
136
- );
137
- `rggen_connect_bit_field_if(bit_field_if, bit_field_2_1_if, 0, 0)
138
- rggen_bit_field_rw #(
139
- .WIDTH (1),
140
- .INITIAL_VALUE (1'h0)
141
- ) u_bit_field_2_1 (
142
- .clk (clk),
143
- .rst_n (rst_n),
144
- .bit_field_if (bit_field_2_1_if),
145
- .o_value (o_bit_field_2_1)
146
- );
134
+ if (1) begin : g_bit_field_2_0
135
+ rggen_bit_field_if #(1) bit_field_sub_if();
136
+ `rggen_connect_bit_field_if(bit_field_if, bit_field_sub_if, 16, 16)
137
+ rggen_bit_field_ro #(
138
+ .WIDTH (1)
139
+ ) u_bit_field (
140
+ .bit_field_if (bit_field_sub_if),
141
+ .i_value (i_bit_field_2_0)
142
+ );
143
+ end
144
+ if (1) begin : g_bit_field_2_1
145
+ rggen_bit_field_if #(1) bit_field_sub_if();
146
+ `rggen_connect_bit_field_if(bit_field_if, bit_field_sub_if, 0, 0)
147
+ rggen_bit_field_rw #(
148
+ .WIDTH (1),
149
+ .INITIAL_VALUE (1'h0)
150
+ ) u_bit_field (
151
+ .clk (clk),
152
+ .rst_n (rst_n),
153
+ .bit_field_if (bit_field_sub_if),
154
+ .o_value (o_bit_field_2_1)
155
+ );
156
+ end
147
157
  end endgenerate
148
158
  generate if (1) begin : g_register_3
149
159
  rggen_bit_field_if #(32) bit_field_if();
150
- rggen_bit_field_if #(32) bit_field_3_0_if();
151
160
  rggen_default_register #(
152
161
  .ADDRESS_WIDTH (8),
153
162
  .START_ADDRESS (8'h0c),
154
163
  .END_ADDRESS (8'h0f),
155
164
  .DATA_WIDTH (32),
156
165
  .VALID_BITS (32'hffffffff)
157
- ) u_register_3 (
166
+ ) u_register (
158
167
  .register_if (register_if[3]),
159
168
  .bit_field_if (bit_field_if)
160
169
  );
161
- `rggen_connect_bit_field_if(bit_field_if, bit_field_3_0_if, 31, 0)
162
- rggen_bit_field_ro #(
163
- .WIDTH (32)
164
- ) u_bit_field_3_0 (
165
- .bit_field_if (bit_field_3_0_if),
166
- .i_value (i_bit_field_3_0)
167
- );
170
+ if (1) begin : g_bit_field_3_0
171
+ rggen_bit_field_if #(32) bit_field_sub_if();
172
+ `rggen_connect_bit_field_if(bit_field_if, bit_field_sub_if, 31, 0)
173
+ rggen_bit_field_ro #(
174
+ .WIDTH (32)
175
+ ) u_bit_field (
176
+ .bit_field_if (bit_field_sub_if),
177
+ .i_value (i_bit_field_3_0)
178
+ );
179
+ end
168
180
  end endgenerate
169
181
  generate if (1) begin : g_register_4
170
182
  genvar g_i;
171
183
  for (g_i = 0;g_i < 4;++g_i) begin : g
172
184
  rggen_bit_field_if #(32) bit_field_if();
173
- rggen_bit_field_if #(16) bit_field_4_0_if();
174
- rggen_bit_field_if #(16) bit_field_4_1_if();
175
185
  rggen_default_register #(
176
186
  .ADDRESS_WIDTH (8),
177
187
  .START_ADDRESS (8'h10 + 8'h04 * g_i),
178
188
  .END_ADDRESS (8'h13 + 8'h04 * g_i),
179
189
  .DATA_WIDTH (32),
180
190
  .VALID_BITS (32'hffffffff)
181
- ) u_register_4 (
191
+ ) u_register (
182
192
  .register_if (register_if[4+g_i]),
183
193
  .bit_field_if (bit_field_if)
184
194
  );
185
- `rggen_connect_bit_field_if(bit_field_if, bit_field_4_0_if, 31, 16)
186
- rggen_bit_field_ro #(
187
- .WIDTH (16)
188
- ) u_bit_field_4_0 (
189
- .bit_field_if (bit_field_4_0_if),
190
- .i_value (i_bit_field_4_0[g_i])
191
- );
192
- `rggen_connect_bit_field_if(bit_field_if, bit_field_4_1_if, 15, 0)
193
- rggen_bit_field_rw #(
194
- .WIDTH (16),
195
- .INITIAL_VALUE (16'h0000)
196
- ) u_bit_field_4_1 (
197
- .clk (clk),
198
- .rst_n (rst_n),
199
- .bit_field_if (bit_field_4_1_if),
200
- .o_value (o_bit_field_4_1[g_i])
201
- );
195
+ if (1) begin : g_bit_field_4_0
196
+ rggen_bit_field_if #(16) bit_field_sub_if();
197
+ `rggen_connect_bit_field_if(bit_field_if, bit_field_sub_if, 31, 16)
198
+ rggen_bit_field_ro #(
199
+ .WIDTH (16)
200
+ ) u_bit_field (
201
+ .bit_field_if (bit_field_sub_if),
202
+ .i_value (i_bit_field_4_0[g_i])
203
+ );
204
+ end
205
+ if (1) begin : g_bit_field_4_1
206
+ rggen_bit_field_if #(16) bit_field_sub_if();
207
+ `rggen_connect_bit_field_if(bit_field_if, bit_field_sub_if, 15, 0)
208
+ rggen_bit_field_rw #(
209
+ .WIDTH (16),
210
+ .INITIAL_VALUE (16'h0000)
211
+ ) u_bit_field (
212
+ .clk (clk),
213
+ .rst_n (rst_n),
214
+ .bit_field_if (bit_field_sub_if),
215
+ .o_value (o_bit_field_4_1[g_i])
216
+ );
217
+ end
202
218
  end
203
219
  end endgenerate
204
220
  generate if (1) begin : g_register_5
@@ -208,8 +224,6 @@ module sample_0 (
208
224
  for (g_j = 0;g_j < 4;++g_j) begin : g
209
225
  rggen_bit_field_if #(32) bit_field_if();
210
226
  logic [32:0] indirect_index;
211
- rggen_bit_field_if #(16) bit_field_5_0_if();
212
- rggen_bit_field_if #(16) bit_field_5_1_if();
213
227
  assign indirect_index = {register_if[2].value[0], register_if[0].value[31:16], register_if[0].value[15:0]};
214
228
  rggen_indirect_register #(
215
229
  .ADDRESS_WIDTH (8),
@@ -219,151 +233,169 @@ module sample_0 (
219
233
  .INDEX_VALUE ({1'h1, g_i[15:0], g_j[15:0]}),
220
234
  .DATA_WIDTH (32),
221
235
  .VALID_BITS (32'hffffffff)
222
- ) u_register_5 (
236
+ ) u_register (
223
237
  .register_if (register_if[8+4*g_i+g_j]),
224
238
  .bit_field_if (bit_field_if),
225
239
  .i_index (indirect_index)
226
240
  );
227
- `rggen_connect_bit_field_if(bit_field_if, bit_field_5_0_if, 31, 16)
228
- rggen_bit_field_ro #(
229
- .WIDTH (16)
230
- ) u_bit_field_5_0 (
231
- .bit_field_if (bit_field_5_0_if),
232
- .i_value (i_bit_field_5_0[g_i][g_j])
233
- );
234
- `rggen_connect_bit_field_if(bit_field_if, bit_field_5_1_if, 15, 0)
235
- rggen_bit_field_rw #(
236
- .WIDTH (16),
237
- .INITIAL_VALUE (16'h0000)
238
- ) u_bit_field_5_1 (
239
- .clk (clk),
240
- .rst_n (rst_n),
241
- .bit_field_if (bit_field_5_1_if),
242
- .o_value (o_bit_field_5_1[g_i][g_j])
243
- );
241
+ if (1) begin : g_bit_field_5_0
242
+ rggen_bit_field_if #(16) bit_field_sub_if();
243
+ `rggen_connect_bit_field_if(bit_field_if, bit_field_sub_if, 31, 16)
244
+ rggen_bit_field_ro #(
245
+ .WIDTH (16)
246
+ ) u_bit_field (
247
+ .bit_field_if (bit_field_sub_if),
248
+ .i_value (i_bit_field_5_0[g_i][g_j])
249
+ );
250
+ end
251
+ if (1) begin : g_bit_field_5_1
252
+ rggen_bit_field_if #(16) bit_field_sub_if();
253
+ `rggen_connect_bit_field_if(bit_field_if, bit_field_sub_if, 15, 0)
254
+ rggen_bit_field_rw #(
255
+ .WIDTH (16),
256
+ .INITIAL_VALUE (16'h0000)
257
+ ) u_bit_field (
258
+ .clk (clk),
259
+ .rst_n (rst_n),
260
+ .bit_field_if (bit_field_sub_if),
261
+ .o_value (o_bit_field_5_1[g_i][g_j])
262
+ );
263
+ end
244
264
  end
245
265
  end
246
266
  end endgenerate
247
267
  generate if (1) begin : g_register_6
248
268
  rggen_bit_field_if #(32) bit_field_if();
249
- rggen_bit_field_if #(1) bit_field_6_0_if();
250
- rggen_bit_field_if #(1) bit_field_6_1_if();
251
269
  rggen_default_register #(
252
270
  .ADDRESS_WIDTH (8),
253
271
  .START_ADDRESS (8'h24),
254
272
  .END_ADDRESS (8'h27),
255
273
  .DATA_WIDTH (32),
256
274
  .VALID_BITS (32'h00000101)
257
- ) u_register_6 (
275
+ ) u_register (
258
276
  .register_if (register_if[16]),
259
277
  .bit_field_if (bit_field_if)
260
278
  );
261
- `rggen_connect_bit_field_if(bit_field_if, bit_field_6_0_if, 8, 8)
262
- rggen_bit_field_w01s_w01c #(
263
- .MODE (rggen_rtl_pkg::RGGEN_CLEAR_MODE),
264
- .SET_CLEAR_VALUE (0),
265
- .WIDTH (1),
266
- .INITIAL_VALUE (1'h0)
267
- ) u_bit_field_6_0 (
268
- .clk (clk),
269
- .rst_n (rst_n),
270
- .i_set_or_clear (i_bit_field_6_0_set),
271
- .bit_field_if (bit_field_6_0_if),
272
- .o_value ()
273
- );
274
- `rggen_connect_bit_field_if(bit_field_if, bit_field_6_1_if, 0, 0)
275
- rggen_bit_field_w01s_w01c #(
276
- .MODE (rggen_rtl_pkg::RGGEN_CLEAR_MODE),
277
- .SET_CLEAR_VALUE (1),
278
- .WIDTH (1),
279
- .INITIAL_VALUE (1'h0)
280
- ) u_bit_field_6_1 (
281
- .clk (clk),
282
- .rst_n (rst_n),
283
- .i_set_or_clear (i_bit_field_6_1_set),
284
- .bit_field_if (bit_field_6_1_if),
285
- .o_value ()
286
- );
279
+ if (1) begin : g_bit_field_6_0
280
+ rggen_bit_field_if #(1) bit_field_sub_if();
281
+ `rggen_connect_bit_field_if(bit_field_if, bit_field_sub_if, 8, 8)
282
+ rggen_bit_field_w01s_w01c #(
283
+ .MODE (rggen_rtl_pkg::RGGEN_CLEAR_MODE),
284
+ .SET_CLEAR_VALUE (0),
285
+ .WIDTH (1),
286
+ .INITIAL_VALUE (1'h0)
287
+ ) u_bit_field (
288
+ .clk (clk),
289
+ .rst_n (rst_n),
290
+ .i_set_or_clear (i_bit_field_6_0_set),
291
+ .bit_field_if (bit_field_sub_if),
292
+ .o_value ()
293
+ );
294
+ end
295
+ if (1) begin : g_bit_field_6_1
296
+ rggen_bit_field_if #(1) bit_field_sub_if();
297
+ `rggen_connect_bit_field_if(bit_field_if, bit_field_sub_if, 0, 0)
298
+ rggen_bit_field_w01s_w01c #(
299
+ .MODE (rggen_rtl_pkg::RGGEN_CLEAR_MODE),
300
+ .SET_CLEAR_VALUE (1),
301
+ .WIDTH (1),
302
+ .INITIAL_VALUE (1'h0)
303
+ ) u_bit_field (
304
+ .clk (clk),
305
+ .rst_n (rst_n),
306
+ .i_set_or_clear (i_bit_field_6_1_set),
307
+ .bit_field_if (bit_field_sub_if),
308
+ .o_value ()
309
+ );
310
+ end
287
311
  end endgenerate
288
312
  generate if (1) begin : g_register_7
289
313
  rggen_bit_field_if #(32) bit_field_if();
290
- rggen_bit_field_if #(1) bit_field_7_0_if();
291
- rggen_bit_field_if #(1) bit_field_7_1_if();
292
314
  rggen_default_register #(
293
315
  .ADDRESS_WIDTH (8),
294
316
  .START_ADDRESS (8'h28),
295
317
  .END_ADDRESS (8'h2b),
296
318
  .DATA_WIDTH (32),
297
319
  .VALID_BITS (32'h00000101)
298
- ) u_register_7 (
320
+ ) u_register (
299
321
  .register_if (register_if[17]),
300
322
  .bit_field_if (bit_field_if)
301
323
  );
302
- `rggen_connect_bit_field_if(bit_field_if, bit_field_7_0_if, 8, 8)
303
- rggen_bit_field_w01s_w01c #(
304
- .MODE (rggen_rtl_pkg::RGGEN_SET_MODE),
305
- .SET_CLEAR_VALUE (0),
306
- .WIDTH (1),
307
- .INITIAL_VALUE (1'h0)
308
- ) u_bit_field_7_0 (
309
- .clk (clk),
310
- .rst_n (rst_n),
311
- .i_set_or_clear (i_bit_field_7_0_clear),
312
- .bit_field_if (bit_field_7_0_if),
313
- .o_value (o_bit_field_7_0)
314
- );
315
- `rggen_connect_bit_field_if(bit_field_if, bit_field_7_1_if, 0, 0)
316
- rggen_bit_field_w01s_w01c #(
317
- .MODE (rggen_rtl_pkg::RGGEN_SET_MODE),
318
- .SET_CLEAR_VALUE (1),
319
- .WIDTH (1),
320
- .INITIAL_VALUE (1'h0)
321
- ) u_bit_field_7_1 (
322
- .clk (clk),
323
- .rst_n (rst_n),
324
- .i_set_or_clear (i_bit_field_7_1_clear),
325
- .bit_field_if (bit_field_7_1_if),
326
- .o_value (o_bit_field_7_1)
327
- );
324
+ if (1) begin : g_bit_field_7_0
325
+ rggen_bit_field_if #(1) bit_field_sub_if();
326
+ `rggen_connect_bit_field_if(bit_field_if, bit_field_sub_if, 8, 8)
327
+ rggen_bit_field_w01s_w01c #(
328
+ .MODE (rggen_rtl_pkg::RGGEN_SET_MODE),
329
+ .SET_CLEAR_VALUE (0),
330
+ .WIDTH (1),
331
+ .INITIAL_VALUE (1'h0)
332
+ ) u_bit_field (
333
+ .clk (clk),
334
+ .rst_n (rst_n),
335
+ .i_set_or_clear (i_bit_field_7_0_clear),
336
+ .bit_field_if (bit_field_sub_if),
337
+ .o_value (o_bit_field_7_0)
338
+ );
339
+ end
340
+ if (1) begin : g_bit_field_7_1
341
+ rggen_bit_field_if #(1) bit_field_sub_if();
342
+ `rggen_connect_bit_field_if(bit_field_if, bit_field_sub_if, 0, 0)
343
+ rggen_bit_field_w01s_w01c #(
344
+ .MODE (rggen_rtl_pkg::RGGEN_SET_MODE),
345
+ .SET_CLEAR_VALUE (1),
346
+ .WIDTH (1),
347
+ .INITIAL_VALUE (1'h0)
348
+ ) u_bit_field (
349
+ .clk (clk),
350
+ .rst_n (rst_n),
351
+ .i_set_or_clear (i_bit_field_7_1_clear),
352
+ .bit_field_if (bit_field_sub_if),
353
+ .o_value (o_bit_field_7_1)
354
+ );
355
+ end
328
356
  end endgenerate
329
357
  generate if (1) begin : g_register_8
330
358
  rggen_bit_field_if #(32) bit_field_if();
331
- rggen_bit_field_if #(16) bit_field_8_0_if();
332
- rggen_bit_field_if #(16) bit_field_8_1_if();
333
359
  rggen_default_register #(
334
360
  .ADDRESS_WIDTH (8),
335
361
  .START_ADDRESS (8'h2c),
336
362
  .END_ADDRESS (8'h2f),
337
363
  .DATA_WIDTH (32),
338
364
  .VALID_BITS (32'hffffffff)
339
- ) u_register_8 (
365
+ ) u_register (
340
366
  .register_if (register_if[18]),
341
367
  .bit_field_if (bit_field_if)
342
368
  );
343
- `rggen_connect_bit_field_if(bit_field_if, bit_field_8_0_if, 31, 16)
344
- rggen_bit_field_rwl_rwe #(
345
- .MODE (rggen_rtl_pkg::RGGEN_LOCK_MODE),
346
- .WIDTH (16),
347
- .INITIAL_VALUE (16'h0000)
348
- ) u_bit_field_8_0 (
349
- .clk (clk),
350
- .rst_n (rst_n),
351
- .i_lock_or_enable (register_if[2].value[0]),
352
- .bit_field_if (bit_field_8_0_if),
353
- .o_value (o_bit_field_8_0)
354
- );
355
- `rggen_connect_bit_field_if(bit_field_if, bit_field_8_1_if, 15, 0)
356
- rggen_bit_field_rwl_rwe #(
357
- .MODE (rggen_rtl_pkg::RGGEN_ENABLE_MODE),
358
- .WIDTH (16),
359
- .INITIAL_VALUE (16'h0000)
360
- ) u_bit_field_8_1 (
361
- .clk (clk),
362
- .rst_n (rst_n),
363
- .i_lock_or_enable (register_if[2].value[0]),
364
- .bit_field_if (bit_field_8_1_if),
365
- .o_value (o_bit_field_8_1)
366
- );
369
+ if (1) begin : g_bit_field_8_0
370
+ rggen_bit_field_if #(16) bit_field_sub_if();
371
+ `rggen_connect_bit_field_if(bit_field_if, bit_field_sub_if, 31, 16)
372
+ rggen_bit_field_rwl_rwe #(
373
+ .MODE (rggen_rtl_pkg::RGGEN_LOCK_MODE),
374
+ .WIDTH (16),
375
+ .INITIAL_VALUE (16'h0000)
376
+ ) u_bit_field (
377
+ .clk (clk),
378
+ .rst_n (rst_n),
379
+ .i_lock_or_enable (register_if[2].value[0]),
380
+ .bit_field_if (bit_field_sub_if),
381
+ .o_value (o_bit_field_8_0)
382
+ );
383
+ end
384
+ if (1) begin : g_bit_field_8_1
385
+ rggen_bit_field_if #(16) bit_field_sub_if();
386
+ `rggen_connect_bit_field_if(bit_field_if, bit_field_sub_if, 15, 0)
387
+ rggen_bit_field_rwl_rwe #(
388
+ .MODE (rggen_rtl_pkg::RGGEN_ENABLE_MODE),
389
+ .WIDTH (16),
390
+ .INITIAL_VALUE (16'h0000)
391
+ ) u_bit_field (
392
+ .clk (clk),
393
+ .rst_n (rst_n),
394
+ .i_lock_or_enable (register_if[2].value[0]),
395
+ .bit_field_if (bit_field_sub_if),
396
+ .o_value (o_bit_field_8_1)
397
+ );
398
+ end
367
399
  end endgenerate
368
400
  generate if (1) begin : g_register_9
369
401
  rggen_external_register #(
@@ -371,7 +403,7 @@ module sample_0 (
371
403
  .START_ADDRESS (8'h80),
372
404
  .END_ADDRESS (8'hff),
373
405
  .DATA_WIDTH (32)
374
- ) u_register_9 (
406
+ ) u_register (
375
407
  .clk (clk),
376
408
  .rst_n (rst_n),
377
409
  .register_if (register_if[19]),
data/sample/sample_0_ral_pkg.sv CHANGED
@@ -12,8 +12,8 @@ package sample_0_ral_pkg;
12
12
  super.new(name, 32, 0);
13
13
  endfunction
14
14
  function void create_fields();
15
- `rggen_ral_create_field_model(bit_field_0_0, "bit_field_0_0", 16, 16, "RW", 0, 16'h0000, 1, "u_bit_field_0_0.value")
16
- `rggen_ral_create_field_model(bit_field_0_1, "bit_field_0_1", 16, 0, "RW", 0, 16'h0000, 1, "u_bit_field_0_1.value")
15
+ `rggen_ral_create_field_model(bit_field_0_0, "bit_field_0_0", 16, 16, "RW", 0, 16'h0000, 1, "g_bit_field_0_0.u_bit_field.value")
16
+ `rggen_ral_create_field_model(bit_field_0_1, "bit_field_0_1", 16, 0, "RW", 0, 16'h0000, 1, "g_bit_field_0_1.u_bit_field.value")
17
17
  endfunction
18
18
  endclass
19
19
  class register_1_reg_model extends rggen_ral_reg;
@@ -22,7 +22,7 @@ package sample_0_ral_pkg;
22
22
  super.new(name, 32, 0);
23
23
  endfunction
24
24
  function void create_fields();
25
- `rggen_ral_create_field_model(bit_field_1_0, "bit_field_1_0", 32, 0, "RW", 0, 32'h00000000, 1, "u_bit_field_1_0.value")
25
+ `rggen_ral_create_field_model(bit_field_1_0, "bit_field_1_0", 32, 0, "RW", 0, 32'h00000000, 1, "g_bit_field_1_0.u_bit_field.value")
26
26
  endfunction
27
27
  endclass
28
28
  class register_2_reg_model extends rggen_ral_reg;
@@ -32,8 +32,8 @@ package sample_0_ral_pkg;
32
32
  super.new(name, 24, 0);
33
33
  endfunction
34
34
  function void create_fields();
35
- `rggen_ral_create_field_model(bit_field_2_0, "bit_field_2_0", 1, 16, "RO", 0, 1'h0, 0, "u_bit_field_2_0.i_value")
36
- `rggen_ral_create_field_model(bit_field_2_1, "bit_field_2_1", 1, 0, "RW", 0, 1'h0, 1, "u_bit_field_2_1.value")
35
+ `rggen_ral_create_field_model(bit_field_2_0, "bit_field_2_0", 1, 16, "RO", 0, 1'h0, 0, "g_bit_field_2_0.u_bit_field.i_value")
36
+ `rggen_ral_create_field_model(bit_field_2_1, "bit_field_2_1", 1, 0, "RW", 0, 1'h0, 1, "g_bit_field_2_1.u_bit_field.value")
37
37
  endfunction
38
38
  endclass
39
39
  class register_3_reg_model extends rggen_ral_reg;
@@ -42,7 +42,7 @@ package sample_0_ral_pkg;
42
42
  super.new(name, 32, 0);
43
43
  endfunction
44
44
  function void create_fields();
45
- `rggen_ral_create_field_model(bit_field_3_0, "bit_field_3_0", 32, 0, "RO", 0, 32'h00000000, 0, "u_bit_field_3_0.i_value")
45
+ `rggen_ral_create_field_model(bit_field_3_0, "bit_field_3_0", 32, 0, "RO", 0, 32'h00000000, 0, "g_bit_field_3_0.u_bit_field.i_value")
46
46
  endfunction
47
47
  endclass
48
48
  class register_4_reg_model extends rggen_ral_reg;
@@ -52,8 +52,8 @@ package sample_0_ral_pkg;
52
52
  super.new(name, 32, 0);
53
53
  endfunction
54
54
  function void create_fields();
55
- `rggen_ral_create_field_model(bit_field_4_0, "bit_field_4_0", 16, 16, "RO", 0, 16'h0000, 0, "u_bit_field_4_0.i_value")
56
- `rggen_ral_create_field_model(bit_field_4_1, "bit_field_4_1", 16, 0, "RW", 0, 16'h0000, 1, "u_bit_field_4_1.value")
55
+ `rggen_ral_create_field_model(bit_field_4_0, "bit_field_4_0", 16, 16, "RO", 0, 16'h0000, 0, "g_bit_field_4_0.u_bit_field.i_value")
56
+ `rggen_ral_create_field_model(bit_field_4_1, "bit_field_4_1", 16, 0, "RW", 0, 16'h0000, 1, "g_bit_field_4_1.u_bit_field.value")
57
57
  endfunction
58
58
  endclass
59
59
  class register_5_reg_model extends rggen_ral_indirect_reg;
@@ -63,8 +63,8 @@ package sample_0_ral_pkg;
63
63
  super.new(name, 32, 0);
64
64
  endfunction
65
65
  function void create_fields();
66
- `rggen_ral_create_field_model(bit_field_5_0, "bit_field_5_0", 16, 16, "RO", 0, 16'h0000, 0, "u_bit_field_5_0.i_value")
67
- `rggen_ral_create_field_model(bit_field_5_1, "bit_field_5_1", 16, 0, "RW", 0, 16'h0000, 1, "u_bit_field_5_1.value")
66
+ `rggen_ral_create_field_model(bit_field_5_0, "bit_field_5_0", 16, 16, "RO", 0, 16'h0000, 0, "g_bit_field_5_0.u_bit_field.i_value")
67
+ `rggen_ral_create_field_model(bit_field_5_1, "bit_field_5_1", 16, 0, "RW", 0, 16'h0000, 1, "g_bit_field_5_1.u_bit_field.value")
68
68
  endfunction
69
69
  function void configure_indirect_indexes();
70
70
  set_indirect_index("register_2", "bit_field_2_1", 1);
@@ -79,8 +79,8 @@ package sample_0_ral_pkg;
79
79
  super.new(name, 16, 0);
80
80
  endfunction
81
81
  function void create_fields();
82
- `rggen_ral_create_field_model(bit_field_6_0, "bit_field_6_0", 1, 8, "W0C", 0, 1'h0, 1, "u_bit_field_6_0.value")
83
- `rggen_ral_create_field_model(bit_field_6_1, "bit_field_6_1", 1, 0, "W1C", 0, 1'h0, 1, "u_bit_field_6_1.value")
82
+ `rggen_ral_create_field_model(bit_field_6_0, "bit_field_6_0", 1, 8, "W0C", 0, 1'h0, 1, "g_bit_field_6_0.u_bit_field.value")
83
+ `rggen_ral_create_field_model(bit_field_6_1, "bit_field_6_1", 1, 0, "W1C", 0, 1'h0, 1, "g_bit_field_6_1.u_bit_field.value")
84
84
  endfunction
85
85
  endclass
86
86
  class register_7_reg_model extends rggen_ral_reg;
@@ -90,8 +90,8 @@ package sample_0_ral_pkg;
90
90
  super.new(name, 16, 0);
91
91
  endfunction
92
92
  function void create_fields();
93
- `rggen_ral_create_field_model(bit_field_7_0, "bit_field_7_0", 1, 8, "W0S", 0, 1'h0, 1, "u_bit_field_7_0.value")
94
- `rggen_ral_create_field_model(bit_field_7_1, "bit_field_7_1", 1, 0, "W1S", 0, 1'h0, 1, "u_bit_field_7_1.value")
93
+ `rggen_ral_create_field_model(bit_field_7_0, "bit_field_7_0", 1, 8, "W0S", 0, 1'h0, 1, "g_bit_field_7_0.u_bit_field.value")
94
+ `rggen_ral_create_field_model(bit_field_7_1, "bit_field_7_1", 1, 0, "W1S", 0, 1'h0, 1, "g_bit_field_7_1.u_bit_field.value")
95
95
  endfunction
96
96
  endclass
97
97
  class register_8_reg_model extends rggen_ral_reg;
@@ -101,8 +101,8 @@ package sample_0_ral_pkg;
101
101
  super.new(name, 32, 0);
102
102
  endfunction
103
103
  function void create_fields();
104
- `rggen_ral_create_field_model(bit_field_8_0, "bit_field_8_0", 16, 16, "RWL", 0, 16'h0000, 1, "u_bit_field_8_0.value")
105
- `rggen_ral_create_field_model(bit_field_8_1, "bit_field_8_1", 16, 0, "RWE", 0, 16'h0000, 1, "u_bit_field_8_1.value")
104
+ `rggen_ral_create_field_model(bit_field_8_0, "bit_field_8_0", 16, 16, "RWL", 0, 16'h0000, 1, "g_bit_field_8_0.u_bit_field.value")
105
+ `rggen_ral_create_field_model(bit_field_8_1, "bit_field_8_1", 16, 0, "RWE", 0, 16'h0000, 1, "g_bit_field_8_1.u_bit_field.value")
106
106
  endfunction
107
107
  endclass
108
108
  class sample_0_block_model#(
data/sample/sample_1.sv CHANGED
@@ -28,91 +28,101 @@ module sample_1 (
28
28
  );
29
29
  generate if (1) begin : g_register_0
30
30
  rggen_bit_field_if #(32) bit_field_if();
31
- rggen_bit_field_if #(16) bit_field_0_0_if();
32
- rggen_bit_field_if #(16) bit_field_0_1_if();
33
31
  rggen_default_register #(
34
32
  .ADDRESS_WIDTH (7),
35
33
  .START_ADDRESS (7'h00),
36
34
  .END_ADDRESS (7'h03),
37
35
  .DATA_WIDTH (32),
38
36
  .VALID_BITS (32'hffffffff)
39
- ) u_register_0 (
37
+ ) u_register (
40
38
  .register_if (register_if[0]),
41
39
  .bit_field_if (bit_field_if)
42
40
  );
43
- `rggen_connect_bit_field_if(bit_field_if, bit_field_0_0_if, 31, 16)
44
- rggen_bit_field_rw #(
45
- .WIDTH (16),
46
- .INITIAL_VALUE (16'h0000)
47
- ) u_bit_field_0_0 (
48
- .clk (clk),
49
- .rst_n (rst_n),
50
- .bit_field_if (bit_field_0_0_if),
51
- .o_value (o_bit_field_0_0)
52
- );
53
- `rggen_connect_bit_field_if(bit_field_if, bit_field_0_1_if, 15, 0)
54
- rggen_bit_field_ro #(
55
- .WIDTH (16)
56
- ) u_bit_field_0_1 (
57
- .bit_field_if (bit_field_0_1_if),
58
- .i_value (i_bit_field_0_1)
59
- );
41
+ if (1) begin : g_bit_field_0_0
42
+ rggen_bit_field_if #(16) bit_field_sub_if();
43
+ `rggen_connect_bit_field_if(bit_field_if, bit_field_sub_if, 31, 16)
44
+ rggen_bit_field_rw #(
45
+ .WIDTH (16),
46
+ .INITIAL_VALUE (16'h0000)
47
+ ) u_bit_field (
48
+ .clk (clk),
49
+ .rst_n (rst_n),
50
+ .bit_field_if (bit_field_sub_if),
51
+ .o_value (o_bit_field_0_0)
52
+ );
53
+ end
54
+ if (1) begin : g_bit_field_0_1
55
+ rggen_bit_field_if #(16) bit_field_sub_if();
56
+ `rggen_connect_bit_field_if(bit_field_if, bit_field_sub_if, 15, 0)
57
+ rggen_bit_field_ro #(
58
+ .WIDTH (16)
59
+ ) u_bit_field (
60
+ .bit_field_if (bit_field_sub_if),
61
+ .i_value (i_bit_field_0_1)
62
+ );
63
+ end
60
64
  end endgenerate
61
65
  generate if (1) begin : g_register_1
62
66
  rggen_bit_field_if #(32) bit_field_if();
63
- rggen_bit_field_if #(32) bit_field_1_0_if();
64
67
  rggen_default_register #(
65
68
  .ADDRESS_WIDTH (7),
66
69
  .START_ADDRESS (7'h04),
67
70
  .END_ADDRESS (7'h07),
68
71
  .DATA_WIDTH (32),
69
72
  .VALID_BITS (32'hffffffff)
70
- ) u_register_1 (
73
+ ) u_register (
71
74
  .register_if (register_if[1]),
72
75
  .bit_field_if (bit_field_if)
73
76
  );
74
- `rggen_connect_bit_field_if(bit_field_if, bit_field_1_0_if, 31, 0)
75
- rggen_bit_field_rw #(
76
- .WIDTH (32),
77
- .INITIAL_VALUE (32'h00000000)
78
- ) u_bit_field_1_0 (
79
- .clk (clk),
80
- .rst_n (rst_n),
81
- .bit_field_if (bit_field_1_0_if),
82
- .o_value (o_bit_field_1_0)
83
- );
77
+ if (1) begin : g_bit_field_1_0
78
+ rggen_bit_field_if #(32) bit_field_sub_if();
79
+ `rggen_connect_bit_field_if(bit_field_if, bit_field_sub_if, 31, 0)
80
+ rggen_bit_field_rw #(
81
+ .WIDTH (32),
82
+ .INITIAL_VALUE (32'h00000000)
83
+ ) u_bit_field (
84
+ .clk (clk),
85
+ .rst_n (rst_n),
86
+ .bit_field_if (bit_field_sub_if),
87
+ .o_value (o_bit_field_1_0)
88
+ );
89
+ end
84
90
  end endgenerate
85
91
  generate if (1) begin : g_register_2
86
92
  rggen_bit_field_if #(32) bit_field_if();
87
- rggen_bit_field_if #(1) bit_field_2_0_if();
88
- rggen_bit_field_if #(1) bit_field_2_1_if();
89
93
  rggen_default_register #(
90
94
  .ADDRESS_WIDTH (7),
91
95
  .START_ADDRESS (7'h08),
92
96
  .END_ADDRESS (7'h0b),
93
97
  .DATA_WIDTH (32),
94
98
  .VALID_BITS (32'h00010001)
95
- ) u_register_2 (
99
+ ) u_register (
96
100
  .register_if (register_if[2]),
97
101
  .bit_field_if (bit_field_if)
98
102
  );
99
- `rggen_connect_bit_field_if(bit_field_if, bit_field_2_0_if, 16, 16)
100
- rggen_bit_field_ro #(
101
- .WIDTH (1)
102
- ) u_bit_field_2_0 (
103
- .bit_field_if (bit_field_2_0_if),
104
- .i_value (i_bit_field_2_0)
105
- );
106
- `rggen_connect_bit_field_if(bit_field_if, bit_field_2_1_if, 0, 0)
107
- rggen_bit_field_rw #(
108
- .WIDTH (1),
109
- .INITIAL_VALUE (1'h0)
110
- ) u_bit_field_2_1 (
111
- .clk (clk),
112
- .rst_n (rst_n),
113
- .bit_field_if (bit_field_2_1_if),
114
- .o_value (o_bit_field_2_1)
115
- );
103
+ if (1) begin : g_bit_field_2_0
104
+ rggen_bit_field_if #(1) bit_field_sub_if();
105
+ `rggen_connect_bit_field_if(bit_field_if, bit_field_sub_if, 16, 16)
106
+ rggen_bit_field_ro #(
107
+ .WIDTH (1)
108
+ ) u_bit_field (
109
+ .bit_field_if (bit_field_sub_if),
110
+ .i_value (i_bit_field_2_0)
111
+ );
112
+ end
113
+ if (1) begin : g_bit_field_2_1
114
+ rggen_bit_field_if #(1) bit_field_sub_if();
115
+ `rggen_connect_bit_field_if(bit_field_if, bit_field_sub_if, 0, 0)
116
+ rggen_bit_field_rw #(
117
+ .WIDTH (1),
118
+ .INITIAL_VALUE (1'h0)
119
+ ) u_bit_field (
120
+ .clk (clk),
121
+ .rst_n (rst_n),
122
+ .bit_field_if (bit_field_sub_if),
123
+ .o_value (o_bit_field_2_1)
124
+ );
125
+ end
116
126
  end endgenerate
117
127
  `undef rggen_connect_bit_field_if
118
128
  endmodule
data/sample/sample_1_ral_pkg.sv CHANGED
@@ -12,8 +12,8 @@ package sample_1_ral_pkg;
12
12
  super.new(name, 32, 0);
13
13
  endfunction
14
14
  function void create_fields();
15
- `rggen_ral_create_field_model(bit_field_0_0, "bit_field_0_0", 16, 16, "RW", 0, 16'h0000, 1, "u_bit_field_0_0.value")
16
- `rggen_ral_create_field_model(bit_field_0_1, "bit_field_0_1", 16, 0, "RO", 0, 16'h0000, 0, "u_bit_field_0_1.i_value")
15
+ `rggen_ral_create_field_model(bit_field_0_0, "bit_field_0_0", 16, 16, "RW", 0, 16'h0000, 1, "g_bit_field_0_0.u_bit_field.value")
16
+ `rggen_ral_create_field_model(bit_field_0_1, "bit_field_0_1", 16, 0, "RO", 0, 16'h0000, 0, "g_bit_field_0_1.u_bit_field.i_value")
17
17
  endfunction
18
18
  endclass
19
19
  class register_1_reg_model extends rggen_ral_reg;
@@ -22,7 +22,7 @@ package sample_1_ral_pkg;
22
22
  super.new(name, 32, 0);
23
23
  endfunction
24
24
  function void create_fields();
25
- `rggen_ral_create_field_model(bit_field_1_0, "bit_field_1_0", 32, 0, "RW", 0, 32'h00000000, 1, "u_bit_field_1_0.value")
25
+ `rggen_ral_create_field_model(bit_field_1_0, "bit_field_1_0", 32, 0, "RW", 0, 32'h00000000, 1, "g_bit_field_1_0.u_bit_field.value")
26
26
  endfunction
27
27
  endclass
28
28
  class register_2_reg_model extends rggen_ral_reg;
@@ -32,8 +32,8 @@ package sample_1_ral_pkg;
32
32
  super.new(name, 24, 0);
33
33
  endfunction
34
34
  function void create_fields();
35
- `rggen_ral_create_field_model(bit_field_2_0, "bit_field_2_0", 1, 16, "RO", 0, 1'h0, 0, "u_bit_field_2_0.i_value")
36
- `rggen_ral_create_field_model(bit_field_2_1, "bit_field_2_1", 1, 0, "RW", 0, 1'h0, 1, "u_bit_field_2_1.value")
35
+ `rggen_ral_create_field_model(bit_field_2_0, "bit_field_2_0", 1, 16, "RO", 0, 1'h0, 0, "g_bit_field_2_0.u_bit_field.i_value")
36
+ `rggen_ral_create_field_model(bit_field_2_1, "bit_field_2_1", 1, 0, "RW", 0, 1'h0, 1, "g_bit_field_2_1.u_bit_field.value")
37
37
  endfunction
38
38
  endclass
39
39
  class sample_1_block_model extends rggen_ral_block;
data/sample/sample_setup.rb CHANGED
@@ -17,6 +17,7 @@ enable :bit_field , :type, [:rw, :ro, :w0c, :w1c, :w0s, :w1s, :rwl, :rwe, :f
17
17
  enable :register_block, [:top_module, :clock_reset, :host_if, :irq_controller]
18
18
  enable :register_block, :host_if, [:apb, :bar]
19
19
  enable :register , :rtl_top
20
+ enable :bit_field , :rtl_top
20
21
  enable :register_block, [:ral_package, :block_model, :constructor, :sub_model_creator, :default_map_creator]
21
22
  enable :register , [:reg_model, :constructor, :field_model_creator, :indirect_index_configurator, :sub_block_model]
22
23
  enable :bit_field , :field_model
data/setup/default.rb CHANGED
@@ -7,6 +7,7 @@ enable :bit_field , :type, [:rw, :ro, :w0c, :w1c, :w0s, :w1s, :rwl, :rwe, :r
7
7
  enable :register_block, [:rtl_top, :clock_reset, :host_if, :irq_controller]
8
8
  enable :register_block, :host_if, [:apb, :axi4lite]
9
9
  enable :register , :rtl_top
10
+ enable :bit_field , :rtl_top
10
11
  enable :register_block, [:ral_package, :block_model, :constructor, :sub_model_creator, :default_map_creator]
11
12
  enable :register , [:reg_model, :constructor, :field_model_creator, :indirect_index_configurator, :sub_block_model]
12
13
  enable :bit_field , :field_model
metadata CHANGED
@@ -1,14 +1,14 @@
1
1
  --- !ruby/object:Gem::Specification
2
2
  name: rggen
3
3
  version: !ruby/object:Gem::Version
4
- version: 0.6.0
4
+ version: 0.6.1
5
5
  platform: ruby
6
6
  authors:
7
7
  - Taichi Ishitani
8
8
  autorequire:
9
9
  bindir: bin
10
10
  cert_chain: []
11
- date: 2017-05-25 00:00:00.000000000 Z
11
+ date: 2017-05-31 00:00:00.000000000 Z
12
12
  dependencies:
13
13
  - !ruby/object:Gem::Dependency
14
14
  name: baby_erubis
@@ -148,6 +148,7 @@ files:
148
148
  - lib/rggen/builtins/bit_field/initial_value.rb
149
149
  - lib/rggen/builtins/bit_field/name.rb
150
150
  - lib/rggen/builtins/bit_field/reference.rb
151
+ - lib/rggen/builtins/bit_field/rtl_top.rb
151
152
  - lib/rggen/builtins/bit_field/type.rb
152
153
  - lib/rggen/builtins/bit_field/types/reserved.rb
153
154
  - lib/rggen/builtins/bit_field/types/ro.erb