rggen 0.4.2 → 0.4.3

checksums.yaml

@@ -1,7 +1,7 @@
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-  data.tar.gz: 5cca3d0af73d1aa9d81d6eac43dc583fabb86491
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+  data.tar.gz: 8f8595953d40b2818c11535f6d17e181c64ee37d
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+  data.tar.gz: 53d5e50d624edc590be59916889603e12552a2ffc876d80b6780616cdb1278ca70d2ba0910520735e82cd11b077f599b96870b1732daf44baeac24d5ada1e591

data/README.md

@@ -1,5 +1,6 @@
 [![Gem Version](https://badge.fury.io/rb/rggen.svg)](https://badge.fury.io/rb/rggen)
 [![Build Status](https://travis-ci.org/taichi-ishitani/rggen.svg?branch=master)](https://travis-ci.org/taichi-ishitani/rggen)
+[![Dependency Status](https://dependencyci.com/github/taichi-ishitani/rggen/badge)](https://dependencyci.com/github/taichi-ishitani/rggen)
 [![Code Climate](https://codeclimate.com/github/taichi-ishitani/rggen/badges/gpa.svg)](https://codeclimate.com/github/taichi-ishitani/rggen)
 [![Test Coverage](https://codeclimate.com/github/taichi-ishitani/rggen/badges/coverage.svg)](https://codeclimate.com/github/taichi-ishitani/rggen/coverage)
 [![Join the chat at https://gitter.im/taichi-ishitani/rggen](https://badges.gitter.im/taichi-ishitani/rggen.svg)](https://gitter.im/taichi-ishitani/rggen?utm_source=badge&utm_medium=badge&utm_campaign=pr-badge&utm_content=badge)

data/lib/rggen.rb

@@ -10,6 +10,7 @@ module RgGen
 
   require_relative 'rggen/exceptions'
 
+  require_relative 'rggen/core_extensions/array'
   require_relative 'rggen/core_extensions/facets'
   require_relative 'rggen/core_extensions/forwardable'
   require_relative 'rggen/core_extensions/integer'

data/lib/rggen/builtins/bit_field/reference.rb

@@ -34,9 +34,7 @@ simple_item :bit_field, :reference do
 
     def find_reference
       return nil unless has_reference?
-      @found_reference  ||= register_block.bit_fields.find do |bit_field|
-        bit_field.name == @reference
-      end
+      @found_reference ||= register_block.bit_fields.find_by(name: @reference)
     end
   end
 end

data/lib/rggen/builtins/bit_field/rwl_rwe.rb

@@ -31,9 +31,7 @@ list_item :bit_field, :type, [:rwl, :rwe] do
     end
 
     def mode_field
-      register_block.bit_fields.find do |f|
-        f.name == bit_field.reference.name
-      end
+      register_block.bit_fields.find_by(name: bit_field.reference.name)
     end
   end
 

data/lib/rggen/builtins/bit_field/w0c_w1c.erb

@@ -1,11 +1,12 @@
-rggen_bit_field_w0c_w1c #(
-  .WIDTH          (<%= width %>),
-  .INITIAL_VALUE  (<%= initial_value %>),
-  .CLEAR_VALUE    (<%= clear_value %>)
+rggen_bit_field_w01s_w01c #(
+  .WIDTH            (<%= width %>),
+  .INITIAL_VALUE    (<%= initial_value %>),
+  .SET_MODE         (0),
+  .SET_CLEAR_VALUE  (<%= clear_value %>)
 ) u_<%= name%> (
   .clk              (<%= register_block.clock %>),
   .rst_n            (<%= register_block.reset %>),
-  .i_set            (<%= set[loop_variables] %>),
+  .i_set_or_clear   (<%= set[loop_variables] %>),
   .i_command_valid  (<%= register_block.host_if.command_valid %>),
   .i_select         (<%= register_block.register_select[index] %>),
   .i_write          (<%= register_block.host_if.write %>),

data/lib/rggen/builtins/bit_field/w0c_w1c.rb

@@ -20,7 +20,7 @@ list_item :bit_field, :type, [:w0c, :w1c] do
     end
 
     def clear_value
-      bin({ w0c: 0, w1c: 1 }[type], 1)
+      { w0c: 0, w1c: 1 }[type]
     end
   end
 end

data/lib/rggen/builtins/bit_field/w0s_w1s.erb

@@ -1,11 +1,12 @@
-rggen_bit_field_w0s_w1s #(
-  .WIDTH          (<%= width %>),
-  .INITIAL_VALUE  (<%= initial_value %>),
-  .SET_VALUE      (<%= set_value %>)
+rggen_bit_field_w01s_w01c #(
+  .WIDTH            (<%= width %>),
+  .INITIAL_VALUE    (<%= initial_value %>),
+  .SET_MODE         (1),
+  .SET_CLEAR_VALUE  (<%= set_value %>)
 ) u_<%= name %> (
   .clk              (<%= register_block.clock %>),
   .rst_n            (<%= register_block.reset %>),
-  .i_clear          (<%= clear[loop_variables] %>),
+  .i_set_or_clear   (<%= clear[loop_variables] %>),
   .i_command_valid  (<%= register_block.host_if.command_valid %>),
   .i_select         (<%= register_block.register_select[index] %>),
   .i_write          (<%= register_block.host_if.write %>),

data/lib/rggen/builtins/bit_field/w0s_w1s.rb

@@ -28,7 +28,7 @@ list_item :bit_field, :type, [:w0s, :w1s] do
     end
 
     def set_value
-      bin({ w0s: 0, w1s: 1 }[type], 1)
+      { w0s: 0, w1s: 1 }[type]
     end
   end
 end

data/lib/rggen/builtins/register/address_decoder.erb

@@ -6,8 +6,6 @@ rggen_address_decoder #(
   .SHADOW_INDEX_WIDTH (<%= shadow_index_width %>),
   .SHADOW_INDEX_VALUE (<%= shadow_index_value %>)
 ) u_<%= register.name%>_address_decoder (
-  .i_read         (<%= register_block.host_if.read %>),
-  .i_write        (<%= register_block.host_if.write %>),
   .i_address      (<%= register_block.host_if.address[local_address_width - 1, address_lsb] %>),
   .i_shadow_index (<%= (shadow? && shadow_index[loop_variables]) || shadow_index_value %>),
   .o_select       (<%= register_block.register_select[register.index] %>)

data/lib/rggen/builtins/register/address_decoder.rb

@@ -43,7 +43,7 @@ simple_item :register, :address_decoder do
     def shadow_index_assignment
       assign(
         shadow_index[register.loop_variables],
-        concat(*shadow_index_fields.map(&:value))
+        concat(shadow_index_fields.map(&:value))
       )
     end
 
@@ -58,14 +58,12 @@ simple_item :register, :address_decoder do
 
     def shadow_index_value
       return hex(0, 1) unless shadow?
-      concat(*shadow_index_values)
+      concat(shadow_index_values)
     end
 
     def shadow_index_fields
       @shadow_index_fields ||= shadow_indexes.map do |index|
-        register_block.bit_fields.find do |bit_field|
-          bit_field.name == index.name
-        end
+        register_block.bit_fields.find_by(name: index.name)
       end
     end
 

data/lib/rggen/builtins/register/read_data.rb

@@ -24,7 +24,7 @@ simple_item :register, :read_data do
 
     def read_data
       if register.readable?
-        concat(*read_data_expressions)
+        concat(read_data_expressions)
       else
         hex(0, configuration.data_width)
       end

data/lib/rggen/builtins/register/reg_model.rb

@@ -57,8 +57,7 @@ simple_item :register, :reg_model do
     end
 
     def array_index
-      return '\'{}' unless array?
-      array(*loop_varibles)
+      array((array? && loop_varibles) || [])
     end
 
     def offset_address

data/lib/rggen/builtins/register/shadow.rb

@@ -121,9 +121,9 @@ simple_item :register, :shadow do
 
     def shadow_index_bit_field
       @shadow_index_bit_field ||= Hash.new do |hash, index_name|
-        hash[index_name]  = register_block.bit_fields.find do |bit_field|
-          bit_field.name == index_name && !bit_field.reserved?
-        end
+        hash[index_name]  = register_block.bit_fields.find_by(
+          name: index_name, reserved?: false
+        )
       end
     end
   end

data/lib/rggen/builtins/register/shadow_index_configurator.rb

@@ -33,10 +33,7 @@ simple_item :register, :shadow_index_configurator do
     end
 
     def fild_parent_register(index_name)
-      index_field = register_block.bit_fields.find do |bit_field|
-        bit_field.name == index_name
-      end
-      index_field.register
+      register_block.bit_fields.find_by(name: index_name).register
     end
 
     def index_name(shadow_index)

data/lib/rggen/builtins/register_block/irq_controller.rb

@@ -20,11 +20,11 @@ simple_item :register_block, :irq_controller do
     end
 
     def assign_ier
-      assign(ier, concat(*ier_fields.map(&:value)))
+      assign(ier, concat(ier_fields.map(&:value)))
     end
 
     def assign_isr
-      assign(isr, concat(*isr_fields.map(&:value)))
+      assign(isr, concat(isr_fields.map(&:value)))
     end
 
     def isr_fields
@@ -38,7 +38,7 @@ simple_item :register_block, :irq_controller do
     end
 
     def find_ier_field(reference)
-      register_block.bit_fields.find { |field| field.name == reference.name }
+      register_block.bit_fields.find_by(name: reference.name)
     end
   end
 end

data/lib/rggen/core_extensions/array.rb

@@ -0,0 +1,9 @@
+class Array
+  def find_by(conditions)
+    find do |i|
+      conditions.all? do |key, value|
+        i.respond_to?(key) && (i.__send__(key) == value)
+      end
+    end
+  end
+end

data/lib/rggen/output_base/verilog_utility.rb

@@ -40,13 +40,12 @@ module RgGen
         "#{subroutine}(#{Array(arguments).join(', ')})"
       end
 
-      def concat(expression, *other_expressions)
-        expressions = Array[expression, *other_expressions]
-        "{#{expressions.join(', ')}}"
+      def concat(expression_or_expressions)
+        "{#{Array(expression_or_expressions).join(', ')}}"
       end
 
-      def array(expression, *other_expressions)
-        "'#{concat(expression, *other_expressions)}"
+      def array(expression_or_expressions)
+        "'#{concat(expression_or_expressions)}"
       end
 
       def string(expression)

data/lib/rggen/version.rb

@@ -1,6 +1,6 @@
 module RgGen
   MAJOR   = 0
   MINOR   = 4
-  TEENY   = 2
+  TEENY   = 3
   VERSION = "#{MAJOR}.#{MINOR}.#{TEENY}".freeze
 end

data/rtl/bit_field/rggen_bit_field_common.svh

@@ -0,0 +1,15 @@
+function automatic logic is_write_access(
+  input command_valid,
+  input select,
+  input write
+);
+  return (command_valid && select && write) ? 1'b1 : 1'b0;
+endfunction
+
+function automatic logic [WIDTH-1:0] get_write_data(
+  input [WIDTH-1:0] current_data,
+  input [WIDTH-1:0] write_data,
+  input [WIDTH-1:0] write_mask
+);
+  return (current_data & (~write_mask)) | (write_data & write_mask);
+endfunction

data/rtl/bit_field/rggen_bit_field_rw.sv

@@ -11,18 +11,17 @@ module rggen_bit_field_rw #(
   input   [WIDTH-1:0] i_write_mask,
   output  [WIDTH-1:0] o_value
 );
-  logic [WIDTH-1:0] write_data;
+  `include  "rggen_bit_field_common.svh"
+
   logic [WIDTH-1:0] value;
 
-  assign  o_value     = value;
-  assign  write_data  = (i_write_data & ( i_write_mask))
-                      | (value        & (~i_write_mask));
+  assign  o_value = value;
   always_ff @(posedge clk or negedge rst_n) begin
     if (!rst_n) begin
       value <= INITIAL_VALUE;
     end
-    else if (i_command_valid && i_select && i_write) begin
-      value <= write_data;
+    else if (is_write_access(i_command_valid, i_select, i_write)) begin
+      value <= get_write_data(value, i_write_data, i_write_mask);
     end
   end
 endmodule

data/rtl/bit_field/rggen_bit_field_rwl_rwe.sv

@@ -13,18 +13,37 @@ module rggen_bit_field_rwl_rwe #(
   input   [WIDTH-1:0] i_write_mask,
   output  [WIDTH-1:0] o_value
 );
+  `include  "rggen_bit_field_common.svh"
+
   logic [WIDTH-1:0] value;
-  logic             writable;
 
   assign  o_value   = value;
-  assign  writable  = (LOCK_MODE) ? !i_lock_or_enable : i_lock_or_enable;
   always_ff @(posedge clk or negedge rst_n) begin
     if (!rst_n) begin
       value <= INITIAL_VALUE;
     end
-    else if (writable && i_command_valid && i_select && i_write) begin
-      value <= (i_write_data & ( i_write_mask))
-             | (value        & (~i_write_mask));
+    else if (
+      can_write(i_lock_or_enable, i_command_valid, i_select, i_write)
+    ) begin
+      value <= get_write_data(value, i_write_data, i_write_mask);
     end
   end
+
+  function automatic logic can_write(
+    input lock_or_enable,
+    input command_valid,
+    input select,
+    input write
+  );
+    if (LOCK_MODE) begin
+      return (
+        (!lock_or_enable) && is_write_access(command_valid, select, write)
+      ) ? 1'b1 : 1'b0;
+    end
+    else begin
+      return (
+        lock_or_enable && is_write_access(command_valid, select, write)
+      ) ? 1'b1 : 1'b0;
+    end
+  endfunction
 endmodule

data/rtl/bit_field/rggen_bit_field_w01s_w01c.sv

@@ -0,0 +1,67 @@
+module rggen_bit_field_w01s_w01c #(
+  parameter WIDTH           = 1,
+  parameter INITIAL_VALUE   = 0,
+  parameter SET_MODE        = 1,
+  parameter SET_CLEAR_VALUE = 0
+)(
+  input               clk,
+  input               rst_n,
+  input   [WIDTH-1:0] i_set_or_clear,
+  input               i_command_valid,
+  input               i_select,
+  input               i_write,
+  input   [WIDTH-1:0] i_write_data,
+  input   [WIDTH-1:0] i_write_mask,
+  output  [WIDTH-1:0] o_value
+);
+  `include  "rggen_bit_field_common.svh"
+
+  logic [WIDTH-1:0] value;
+
+  assign  o_value = value;
+  always_ff @(posedge clk or negedge rst_n) begin
+    if (!rst_n) begin
+      value <= INITIAL_VALUE;
+    end
+    else begin
+      value <= get_next_value(
+        i_set_or_clear,
+        value,
+        i_command_valid,
+        i_select,
+        i_write,
+        i_write_mask,
+        i_write_data
+      );
+    end
+  end
+
+  function automatic logic [WIDTH-1:0] get_next_value(
+    input [WIDTH-1:0] set_or_clear,
+    input [WIDTH-1:0] current_value,
+    input             command_valid,
+    input             select,
+    input             write,
+    input [WIDTH-1:0] write_mask,
+    input [WIDTH-1:0] write_data
+  );
+    logic [WIDTH-1:0] control_value;
+    logic [WIDTH-1:0] set;
+    logic [WIDTH-1:0] clear;
+    if (is_write_access(command_valid, select, write)) begin
+      control_value = write_mask & ((SET_CLEAR_VALUE) ? write_data : ~write_data);
+    end
+    else begin
+      control_value = '0;
+    end
+    if (SET_MODE) begin
+      set   = control_value;
+      clear = set_or_clear;
+    end
+    else begin
+      set   = set_or_clear;
+      clear = control_value;
+    end
+    return set | (current_value & (~clear));
+  endfunction
+endmodule

data/rtl/compile.f

@@ -1,5 +1,6 @@
 +libext+.sv
 +incdir+${RGGEN_HOME}/rtl/register_block
++incdir+${RGGEN_HOME}/rtl/bit_field
 -y ${RGGEN_HOME}/rtl/bit_field
 -y ${RGGEN_HOME}/rtl/register
 -y ${RGGEN_HOME}/rtl/register_block

data/rtl/register/rggen_address_decoder.sv

@@ -6,8 +6,6 @@ module rggen_address_decoder #(
   parameter SHADOW_INDEX_WIDTH  = 1,
   parameter SHADOW_INDEX_VALUE  = 'h00
 )(
-  input                             i_read,
-  input                             i_write,
   input   [ADDRESS_WIDTH-1:0]       i_address,
   input   [SHADOW_INDEX_WIDTH-1:0]  i_shadow_index,
   output                            o_select

data/sample/sample_0.sv

@@ -139,8 +139,6 @@ module sample_0 (
     .SHADOW_INDEX_WIDTH (1),
     .SHADOW_INDEX_VALUE (1'h0)
   ) u_register_0_address_decoder (
-    .i_read         (read),
-    .i_write        (write),
     .i_address      (address[7:2]),
     .i_shadow_index (1'h0),
     .o_select       (register_select[0])
@@ -182,8 +180,6 @@ module sample_0 (
     .SHADOW_INDEX_WIDTH (1),
     .SHADOW_INDEX_VALUE (1'h0)
   ) u_register_1_address_decoder (
-    .i_read         (read),
-    .i_write        (write),
     .i_address      (address[7:2]),
     .i_shadow_index (1'h0),
     .o_select       (register_select[1])
@@ -211,8 +207,6 @@ module sample_0 (
     .SHADOW_INDEX_WIDTH (1),
     .SHADOW_INDEX_VALUE (1'h0)
   ) u_register_2_address_decoder (
-    .i_read         (read),
-    .i_write        (write),
     .i_address      (address[7:2]),
     .i_shadow_index (1'h0),
     .o_select       (register_select[2])
@@ -246,8 +240,6 @@ module sample_0 (
     .SHADOW_INDEX_WIDTH (1),
     .SHADOW_INDEX_VALUE (1'h0)
   ) u_register_3_address_decoder (
-    .i_read         (read),
-    .i_write        (write),
     .i_address      (address[7:2]),
     .i_shadow_index (1'h0),
     .o_select       (register_select[3])
@@ -270,8 +262,6 @@ module sample_0 (
         .SHADOW_INDEX_WIDTH (1),
         .SHADOW_INDEX_VALUE (1'h0)
       ) u_register_4_address_decoder (
-        .i_read         (read),
-        .i_write        (write),
         .i_address      (address[7:2]),
         .i_shadow_index (1'h0),
         .o_select       (register_select[4+g_i])
@@ -312,8 +302,6 @@ module sample_0 (
           .SHADOW_INDEX_WIDTH (33),
           .SHADOW_INDEX_VALUE ({1'h1, g_i[15:0], g_j[15:0]})
         ) u_register_5_address_decoder (
-          .i_read         (read),
-          .i_write        (write),
           .i_address      (address[7:2]),
           .i_shadow_index (register_5_shadow_index[g_i][g_j]),
           .o_select       (register_select[8+4*g_i+g_j])
@@ -350,21 +338,20 @@ module sample_0 (
     .SHADOW_INDEX_WIDTH (1),
     .SHADOW_INDEX_VALUE (1'h0)
   ) u_register_6_address_decoder (
-    .i_read         (read),
-    .i_write        (write),
     .i_address      (address[7:2]),
     .i_shadow_index (1'h0),
     .o_select       (register_select[16])
   );
   assign register_read_data[16] = {23'h000000, bit_field_6_0_value, 7'h00, bit_field_6_1_value};
-  rggen_bit_field_w0c_w1c #(
-    .WIDTH          (1),
-    .INITIAL_VALUE  (1'h0),
-    .CLEAR_VALUE    (1'b0)
+  rggen_bit_field_w01s_w01c #(
+    .WIDTH            (1),
+    .INITIAL_VALUE    (1'h0),
+    .SET_MODE         (0),
+    .SET_CLEAR_VALUE  (0)
   ) u_bit_field_6_0 (
     .clk              (clk),
     .rst_n            (rst_n),
-    .i_set            (i_bit_field_6_0_set),
+    .i_set_or_clear   (i_bit_field_6_0_set),
     .i_command_valid  (command_valid),
     .i_select         (register_select[16]),
     .i_write          (write),
@@ -372,14 +359,15 @@ module sample_0 (
     .i_write_mask     (write_mask[8]),
     .o_value          (bit_field_6_0_value)
   );
-  rggen_bit_field_w0c_w1c #(
-    .WIDTH          (1),
-    .INITIAL_VALUE  (1'h0),
-    .CLEAR_VALUE    (1'b1)
+  rggen_bit_field_w01s_w01c #(
+    .WIDTH            (1),
+    .INITIAL_VALUE    (1'h0),
+    .SET_MODE         (0),
+    .SET_CLEAR_VALUE  (1)
   ) u_bit_field_6_1 (
     .clk              (clk),
     .rst_n            (rst_n),
-    .i_set            (i_bit_field_6_1_set),
+    .i_set_or_clear   (i_bit_field_6_1_set),
     .i_command_valid  (command_valid),
     .i_select         (register_select[16]),
     .i_write          (write),
@@ -395,22 +383,21 @@ module sample_0 (
     .SHADOW_INDEX_WIDTH (1),
     .SHADOW_INDEX_VALUE (1'h0)
   ) u_register_7_address_decoder (
-    .i_read         (read),
-    .i_write        (write),
     .i_address      (address[7:2]),
     .i_shadow_index (1'h0),
     .o_select       (register_select[17])
   );
   assign register_read_data[17] = {23'h000000, bit_field_7_0_value, 7'h00, bit_field_7_1_value};
   assign o_bit_field_7_0 = bit_field_7_0_value;
-  rggen_bit_field_w0s_w1s #(
-    .WIDTH          (1),
-    .INITIAL_VALUE  (1'h0),
-    .SET_VALUE      (1'b0)
+  rggen_bit_field_w01s_w01c #(
+    .WIDTH            (1),
+    .INITIAL_VALUE    (1'h0),
+    .SET_MODE         (1),
+    .SET_CLEAR_VALUE  (0)
   ) u_bit_field_7_0 (
     .clk              (clk),
     .rst_n            (rst_n),
-    .i_clear          (i_bit_field_7_0_clear),
+    .i_set_or_clear   (i_bit_field_7_0_clear),
     .i_command_valid  (command_valid),
     .i_select         (register_select[17]),
     .i_write          (write),
@@ -419,14 +406,15 @@ module sample_0 (
     .o_value          (bit_field_7_0_value)
   );
   assign o_bit_field_7_1 = bit_field_7_1_value;
-  rggen_bit_field_w0s_w1s #(
-    .WIDTH          (1),
-    .INITIAL_VALUE  (1'h0),
-    .SET_VALUE      (1'b1)
+  rggen_bit_field_w01s_w01c #(
+    .WIDTH            (1),
+    .INITIAL_VALUE    (1'h0),
+    .SET_MODE         (1),
+    .SET_CLEAR_VALUE  (1)
   ) u_bit_field_7_1 (
     .clk              (clk),
     .rst_n            (rst_n),
-    .i_clear          (i_bit_field_7_1_clear),
+    .i_set_or_clear   (i_bit_field_7_1_clear),
     .i_command_valid  (command_valid),
     .i_select         (register_select[17]),
     .i_write          (write),
@@ -442,8 +430,6 @@ module sample_0 (
     .SHADOW_INDEX_WIDTH (1),
     .SHADOW_INDEX_VALUE (1'h0)
   ) u_register_8_address_decoder (
-    .i_read         (read),
-    .i_write        (write),
     .i_address      (address[7:2]),
     .i_shadow_index (1'h0),
     .o_select       (register_select[18])
@@ -489,8 +475,6 @@ module sample_0 (
     .SHADOW_INDEX_WIDTH (1),
     .SHADOW_INDEX_VALUE (1'h0)
   ) u_register_9_address_decoder (
-    .i_read         (read),
-    .i_write        (write),
     .i_address      (address[7:2]),
     .i_shadow_index (1'h0),
     .o_select       (register_select[19])

data/sample/sample_1.sv

@@ -88,8 +88,6 @@ module sample_1 (
     .SHADOW_INDEX_WIDTH (1),
     .SHADOW_INDEX_VALUE (1'h0)
   ) u_register_0_address_decoder (
-    .i_read         (read),
-    .i_write        (write),
     .i_address      (address[6:2]),
     .i_shadow_index (1'h0),
     .o_select       (register_select[0])
@@ -123,8 +121,6 @@ module sample_1 (
     .SHADOW_INDEX_WIDTH (1),
     .SHADOW_INDEX_VALUE (1'h0)
   ) u_register_1_address_decoder (
-    .i_read         (read),
-    .i_write        (write),
     .i_address      (address[6:2]),
     .i_shadow_index (1'h0),
     .o_select       (register_select[1])
@@ -152,8 +148,6 @@ module sample_1 (
     .SHADOW_INDEX_WIDTH (1),
     .SHADOW_INDEX_VALUE (1'h0)
   ) u_register_2_address_decoder (
-    .i_read         (read),
-    .i_write        (write),
     .i_address      (address[6:2]),
     .i_shadow_index (1'h0),
     .o_select       (register_select[2])

metadata

@@ -1,14 +1,14 @@
 --- !ruby/object:Gem::Specification
 name: rggen
 version: !ruby/object:Gem::Version
-  version: 0.4.2
+  version: 0.4.3
 platform: ruby
 authors:
 - Taichi Ishitani
 autorequire: 
 bindir: bin
 cert_chain: []
-date: 2016-07-14 00:00:00.000000000 Z
+date: 2016-08-23 00:00:00.000000000 Z
 dependencies:
 - !ruby/object:Gem::Dependency
   name: baby_erubis
@@ -227,6 +227,7 @@ files:
 - lib/rggen/core_components/rtl/component.rb
 - lib/rggen/core_components/rtl/item.rb
 - lib/rggen/core_components/rtl/setup.rb
+- lib/rggen/core_extensions/array.rb
 - lib/rggen/core_extensions/facets.rb
 - lib/rggen/core_extensions/forwardable.rb
 - lib/rggen/core_extensions/integer.rb
@@ -265,11 +266,11 @@ files:
 - ral/rggen_ral_pkg.sv
 - ral/rggen_ral_reg.svh
 - ral/rggen_ral_shadow_reg.svh
+- rtl/bit_field/rggen_bit_field_common.svh
 - rtl/bit_field/rggen_bit_field_ro.sv
 - rtl/bit_field/rggen_bit_field_rw.sv
 - rtl/bit_field/rggen_bit_field_rwl_rwe.sv
-- rtl/bit_field/rggen_bit_field_w0c_w1c.sv
-- rtl/bit_field/rggen_bit_field_w0s_w1s.sv
+- rtl/bit_field/rggen_bit_field_w01s_w01c.sv
 - rtl/compile.f
 - rtl/register/rggen_address_decoder.sv
 - rtl/register/rggen_bus_exporter.sv

data/rtl/bit_field/rggen_bit_field_w0c_w1c.sv

@@ -1,36 +0,0 @@
-module rggen_bit_field_w0c_w1c #(
-  parameter WIDTH         = 1,
-  parameter INITIAL_VALUE = 1'b0,
-  parameter CLEAR_VALUE   = 1'b0
-)(
-  input               clk,
-  input               rst_n,
-  input   [WIDTH-1:0] i_set,
-  input               i_command_valid,
-  input               i_select,
-  input               i_write,
-  input   [WIDTH-1:0] i_write_data,
-  input   [WIDTH-1:0] i_write_mask,
-  output  [WIDTH-1:0] o_value
-);
-  logic [WIDTH-1:0] value;
-  logic             write_valid;
-
-  assign  o_value     = value;
-  assign  write_valid = (i_command_valid && i_select && i_write) ? 1'b1 : 1'b0;
-  always_ff @(posedge clk or negedge rst_n) begin
-    if (!rst_n) begin
-      value <= INITIAL_VALUE;
-    end
-    else begin
-      for (int i = 0;i < WIDTH;i++) begin
-        if (i_set[i]) begin
-          value[i]  <= 1'b1;
-        end
-        else if (write_valid && i_write_mask[i] && (i_write_data[i] == CLEAR_VALUE)) begin
-          value[i]  <= 1'b0;
-        end
-      end
-    end
-  end
-endmodule

data/rtl/bit_field/rggen_bit_field_w0s_w1s.sv

@@ -1,36 +0,0 @@
-module rggen_bit_field_w0s_w1s #(
-  parameter WIDTH         = 1,
-  parameter INITIAL_VALUE = 1'b0,
-  parameter SET_VALUE     = 1'b0
-)(
-  input               clk,
-  input               rst_n,
-  input   [WIDTH-1:0] i_clear,
-  input               i_command_valid,
-  input               i_select,
-  input               i_write,
-  input   [WIDTH-1:0] i_write_data,
-  input   [WIDTH-1:0] i_write_mask,
-  output  [WIDTH-1:0] o_value
-);
-  logic [WIDTH-1:0] value;
-  logic             write_valid;
-
-  assign  o_value     = value;
-  assign  write_valid = (i_command_valid && i_select && i_write) ? 1'b1 : 1'b0;
-  always_ff @(posedge clk or negedge rst_n) begin
-    if (!rst_n) begin
-      value <= INITIAL_VALUE;
-    end
-    else begin
-      for (int i = 0;i < WIDTH;i++) begin
-        if (write_valid && i_write_mask[i] && (i_write_data[i] == SET_VALUE)) begin
-          value[i]  <= 1'b1;
-        end
-        else if (i_clear[i]) begin
-          value[i]  <= 1'b0;
-        end
-      end
-    end
-  end
-endmodule